| /drivers/bus/ |
| D | omap_l3_smx.h | 43 static const u64 shift = 1; variable
45 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
46 #define L3_STATUS_0_MPUIA_RSP (shift << 1)
47 #define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48 #define L3_STATUS_0_IVAIA_BRST (shift << 6)
49 #define L3_STATUS_0_IVAIA_RSP (shift << 7)
50 #define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51 #define L3_STATUS_0_SGXIA_BRST (shift << 9)
52 #define L3_STATUS_0_SGXIA_RSP (shift << 10)
53 #define L3_STATUS_0_SGXIA_MERROR (shift << 11)
[all …]
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| /drivers/memory/tegra/ |
| D | tegra114.c | 31 .shift = 0,
45 .shift = 0,
59 .shift = 16,
73 .shift = 16,
87 .shift = 0,
101 .shift = 0,
115 .shift = 0,
129 .shift = 0,
143 .shift = 16,
157 .shift = 0,
[all …]
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| D | tegra30.c | 31 .shift = 0,
45 .shift = 0,
59 .shift = 16,
73 .shift = 16,
87 .shift = 0,
101 .shift = 0,
115 .shift = 16,
129 .shift = 16,
143 .shift = 0,
157 .shift = 0,
[all …]
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| D | tegra210.c | 33 .shift = 0,
47 .shift = 0,
61 .shift = 16,
75 .shift = 16,
89 .shift = 0,
103 .shift = 0,
117 .shift = 0,
131 .shift = 0,
145 .shift = 0,
159 .shift = 0,
[all …]
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| D | tegra124.c | 73 .shift = 0,
87 .shift = 0,
101 .shift = 16,
115 .shift = 16,
129 .shift = 0,
143 .shift = 0,
157 .shift = 0,
171 .shift = 0,
185 .shift = 0,
199 .shift = 0,
[all …]
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| /drivers/clk/imx/ |
| D | clk.h | 52 void __iomem *reg, u8 shift, u32 exclusive_mask);
58 void __iomem *reg, u8 shift, u8 width,
61 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
66 void __iomem *reg, u8 shift, u8 width,
70 u8 shift, u8 width, const char **parents,
86 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider() argument
89 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider()
93 const char *parent, void __iomem *reg, u8 shift, u8 width, in imx_clk_divider_flags() argument
97 reg, shift, width, 0, &imx_ccm_lock); in imx_clk_divider_flags()
101 void __iomem *reg, u8 shift, u8 width) in imx_clk_divider2() argument
[all …]
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| D | clk-busy.c | 21 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
25 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
36 u8 shift; member
70 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_divider_set_rate()
82 void __iomem *reg, u8 shift, u8 width, in imx_clk_busy_divider() argument
94 busy->shift = busy_shift; in imx_clk_busy_divider()
97 busy->div.shift = shift; in imx_clk_busy_divider()
121 u8 shift; member
145 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_mux_set_parent()
155 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, in imx_clk_busy_mux() argument
[all …]
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| /drivers/mfd/ |
| D | tmio_core.c | 12 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_enable() argument
15 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_enable()
16 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_enable()
19 sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01); in tmio_core_mmc_enable()
22 sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f); in tmio_core_mmc_enable()
25 sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00); in tmio_core_mmc_enable()
31 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_resume() argument
35 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_resume()
36 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_resume()
42 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state) in tmio_core_mmc_pwr() argument
[all …]
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| /drivers/video/fbdev/core/ |
| D | sysimgblt.c | 57 u32 color = 0, val, shift; in color_imageblit() local
67 shift = 0; in color_imageblit()
74 shift = start_index; in color_imageblit()
83 val |= FB_SHIFT_HIGH(p, color, shift); in color_imageblit()
84 if (shift >= null_bits) { in color_imageblit()
87 val = (shift == null_bits) ? 0 : in color_imageblit()
88 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
90 shift += bpp; in color_imageblit()
91 shift &= (32 - 1); in color_imageblit()
94 if (shift) { in color_imageblit()
[all …]
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| D | cfbimgblt.c | 82 u32 color = 0, val, shift; in color_imageblit() local
93 shift = 0; in color_imageblit()
100 shift = start_index; in color_imageblit()
109 val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask); in color_imageblit()
110 if (shift >= null_bits) { in color_imageblit()
113 val = (shift == null_bits) ? 0 : in color_imageblit()
114 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
116 shift += bpp; in color_imageblit()
117 shift &= (32 - 1); in color_imageblit()
120 if (shift) { in color_imageblit()
[all …]
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| /drivers/soc/fsl/qe/ |
| D | ucc.c | 94 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
100 *shift = 16 - 8 * (ucc_num & 2); in get_cmxucr_reg()
107 unsigned int shift; in ucc_mux_set_grant_tsa_bkpt() local
113 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
116 setbits32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
118 clrbits32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
128 unsigned int shift; in ucc_set_qe_mux_rxtx() local
139 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_set_qe_mux_rxtx()
212 shift += 4; in ucc_set_qe_mux_rxtx()
214 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, in ucc_set_qe_mux_rxtx()
[all …]
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_qmath.c | 109 s32 qm_shl32(s32 op, int shift) in qm_shl32() argument
114 if (shift > 31) in qm_shl32()
115 shift = 31; in qm_shl32()
116 else if (shift < -31) in qm_shl32()
117 shift = -31; in qm_shl32()
118 if (shift >= 0) { in qm_shl32()
119 for (i = 0; i < shift; i++) in qm_shl32()
122 result = result >> (-shift); in qm_shl32()
134 s16 qm_shl16(s16 op, int shift) in qm_shl16() argument
139 if (shift > 15) in qm_shl16()
[all …]
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| /drivers/md/persistent-data/ |
| D | dm-btree-remove.c | 56 static void node_shift(struct btree_node *n, int shift) in node_shift() argument
61 if (shift < 0) { in node_shift()
62 shift = -shift; in node_shift()
63 BUG_ON(shift > nr_entries); in node_shift()
64 BUG_ON((void *) key_ptr(n, shift) >= value_ptr(n, shift)); in node_shift()
66 key_ptr(n, shift), in node_shift()
67 (nr_entries - shift) * sizeof(__le64)); in node_shift()
69 value_ptr(n, shift), in node_shift()
70 (nr_entries - shift) * value_size); in node_shift()
72 BUG_ON(nr_entries + shift > le32_to_cpu(n->header.max_entries)); in node_shift()
[all …]
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| /drivers/infiniband/core/ |
| D | packer.c | 71 int shift; in ib_pack() local
76 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
80 structure) << shift; in ib_pack()
84 mask = cpu_to_be32(((1ull << desc[i].size_bits) - 1) << shift); in ib_pack()
88 int shift; in ib_pack() local
93 shift = 64 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
97 structure) << shift; in ib_pack()
101 mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); in ib_pack()
160 int shift; in ib_unpack() local
165 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_unpack()
[all …]
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| /drivers/clk/meson/ |
| D | clkc.h | 22 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
23 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
25 #define PARM_GET(width, shift, reg) \ argument
26 (((reg) & SETPMASK(width, shift)) >> (shift))
27 #define PARM_SET(width, shift, reg, val) \ argument
28 (((reg) & CLRPMASK(width, shift)) | (val << (shift)))
34 u8 shift; member
|
| /drivers/media/platform/davinci/ |
| D | vpss.c | 242 u32 utemp, mask = 0x1, shift = 0; in dm355_enable_clock() local
249 shift = 2; in dm355_enable_clock()
252 shift = 3; in dm355_enable_clock()
255 shift = 4; in dm355_enable_clock()
258 shift = 5; in dm355_enable_clock()
261 shift = 6; in dm355_enable_clock()
272 utemp &= ~(mask << shift); in dm355_enable_clock()
274 utemp |= (mask << shift); in dm355_enable_clock()
284 u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR; in dm365_enable_clock() local
292 shift = 1; in dm365_enable_clock()
[all …]
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| /drivers/clk/sunxi-ng/ |
| D | ccu_nkmp.c | 90 n = reg >> nkmp->n.shift; in ccu_nkmp_recalc_rate()
93 k = reg >> nkmp->k.shift; in ccu_nkmp_recalc_rate()
96 m = reg >> nkmp->m.shift; in ccu_nkmp_recalc_rate()
99 p = reg >> nkmp->p.shift; in ccu_nkmp_recalc_rate()
139 reg &= ~GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift); in ccu_nkmp_set_rate()
140 reg &= ~GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift); in ccu_nkmp_set_rate()
141 reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift); in ccu_nkmp_set_rate()
142 reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift); in ccu_nkmp_set_rate()
144 reg |= (_nkmp.n - 1) << nkmp->n.shift; in ccu_nkmp_set_rate()
145 reg |= (_nkmp.k - 1) << nkmp->k.shift; in ccu_nkmp_set_rate()
[all …]
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| /drivers/regulator/ |
| D | max8998.c | 117 int *reg, int *shift) in max8998_get_enable_register() argument
124 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
128 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
132 *shift = 7 - (ldo - MAX8998_LDO14); in max8998_get_enable_register()
136 *shift = 7 - (ldo - MAX8998_BUCK1); in max8998_get_enable_register()
140 *shift = 7 - (ldo - MAX8998_EN32KHZ_AP); in max8998_get_enable_register()
144 *shift = 7 - (ldo - MAX8998_ESAFEOUT1); in max8998_get_enable_register()
157 int ret, reg, shift = 8; in max8998_ldo_is_enabled() local
160 ret = max8998_get_enable_register(rdev, ®, &shift); in max8998_ldo_is_enabled()
168 return val & (1 << shift); in max8998_ldo_is_enabled()
[all …]
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| /drivers/clk/ |
| D | clk-axm5516.c | 81 u32 shift; member
97 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); in axxia_divclk_recalc_rate()
116 u32 shift; member
131 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); in axxia_clkmux_get_parent()
219 .shift = 0,
233 .shift = 4,
247 .shift = 8,
261 .shift = 12,
275 .shift = 0,
289 .shift = 4,
[all …]
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| D | clk-mux.c | 42 val = clk_readl(mux->reg) >> mux->shift; in clk_mux_get_parent()
88 val = mux->mask << (mux->shift + 16); in clk_mux_set_parent()
91 val &= ~(mux->mask << mux->shift); in clk_mux_set_parent()
93 val |= index << mux->shift; in clk_mux_set_parent()
119 void __iomem *reg, u8 shift, u32 mask, in clk_hw_register_mux_table() argument
130 if (width + shift > 16) { in clk_hw_register_mux_table()
154 mux->shift = shift; in clk_hw_register_mux_table()
175 void __iomem *reg, u8 shift, u32 mask, in clk_register_mux_table() argument
181 flags, reg, shift, mask, clk_mux_flags, in clk_register_mux_table()
192 void __iomem *reg, u8 shift, u8 width, in clk_register_mux() argument
[all …]
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| /drivers/net/ethernet/ti/ |
| D | cpsw_ale.c | 463 int shift, port_shift; member
472 .shift = 31,
480 .shift = 30,
488 .shift = 29,
496 .shift = 8,
504 .shift = 7,
512 .shift = 6,
520 .shift = 5,
528 .shift = 4,
536 .shift = 3,
[all …]
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | item.h | 47 unsigned char shift; /* shift in bits */ member
83 tmp >>= item->shift; in __mlxsw_item_get16()
86 tmp <<= item->shift; in __mlxsw_item_get16()
96 u16 mask = GENMASK(item->size.bits - 1, 0) << item->shift; in __mlxsw_item_set16()
100 val <<= item->shift; in __mlxsw_item_set16()
116 tmp >>= item->shift; in __mlxsw_item_get32()
119 tmp <<= item->shift; in __mlxsw_item_get32()
129 u32 mask = GENMASK(item->size.bits - 1, 0) << item->shift; in __mlxsw_item_set32()
133 val <<= item->shift; in __mlxsw_item_set32()
149 tmp >>= item->shift; in __mlxsw_item_get64()
[all …]
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| /drivers/s390/char/ |
| D | defkeymap.map | 145 shift control keycode 65 = F13
146 shift control keycode 66 = F14
147 shift control keycode 67 = F15
148 shift control keycode 68 = F16
149 shift control keycode 69 = F17
150 shift control keycode 70 = F18
151 shift control keycode 71 = F19
152 shift control keycode 72 = F20
153 shift control keycode 73 = F21
154 shift control keycode 113 = F1
[all …]
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| /drivers/reset/ |
| D | reset-pistachio.c | 71 int shift; in pistachio_reset_assert() local
74 shift = pistachio_reset_shift(id); in pistachio_reset_assert()
75 if (shift < 0) in pistachio_reset_assert()
76 return shift; in pistachio_reset_assert()
77 mask = BIT(shift); in pistachio_reset_assert()
88 int shift; in pistachio_reset_deassert() local
91 shift = pistachio_reset_shift(id); in pistachio_reset_deassert()
92 if (shift < 0) in pistachio_reset_deassert()
93 return shift; in pistachio_reset_deassert()
94 mask = BIT(shift); in pistachio_reset_deassert()
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| /drivers/clk/sunxi/ |
| D | clk-sun6i-ar100.c | 29 int shift; in sun6i_get_ar100_factors() local
38 shift = 0; in sun6i_get_ar100_factors()
40 shift = 1; in sun6i_get_ar100_factors()
42 shift = 2; in sun6i_get_ar100_factors()
44 shift = 3; in sun6i_get_ar100_factors()
46 div >>= shift; in sun6i_get_ar100_factors()
51 req->rate = (req->parent_rate >> shift) / div; in sun6i_get_ar100_factors()
53 req->p = shift; in sun6i_get_ar100_factors()
|