Searched refs:socfpgaclk (Results 1 – 6 of 6) sorted by relevance
35 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local38 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()39 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()40 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()42 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()51 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local56 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()58 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()90 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) in socfpga_clk_prepare()[all …]
34 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local37 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()38 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()39 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()40 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()41 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()44 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()52 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local55 clk_src = readl(socfpgaclk->hw.reg); in clk_periclk_get_parent()
101 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local104 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()105 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()106 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()107 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()108 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_recalc_rate()110 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()121 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local127 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()135 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
30 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local33 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()34 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()36 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()37 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()38 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()41 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
51 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local56 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()71 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local73 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
48 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local53 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()63 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local66 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()