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Searched refs:src_h (Results 1 – 25 of 52) sorted by relevance

123

/drivers/media/platform/ti-vpe/
Dsc.c113 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h, in sc_set_vs_coeffs() argument
122 if (dst_h > src_h) { in sc_set_vs_coeffs()
124 } else if (dst_h == src_h) { in sc_set_vs_coeffs()
127 sixteenths = (dst_h << 4) / src_h; in sc_set_vs_coeffs()
154 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
184 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
219 if (dst_h < (src_h >> 2)) { in sc_config_scaler()
228 factor = (u16) ((dst_h << 10) / src_h); in sc_config_scaler()
244 src_h, dst_h, factor, row_acc_init_rav, in sc_config_scaler()
248 row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1); in sc_config_scaler()
[all …]
Dsc.h201 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
204 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
/drivers/media/pci/ivtv/
Divtv-yuv.c53 y_decode_height = uv_decode_height = f->src_h + f->src_y; in ivtv_yuv_prep_user_dma()
407 f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y); in ivtv_yuv_handle_vertical()
437 reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y); in ivtv_yuv_handle_vertical()
439 reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1); in ivtv_yuv_handle_vertical()
442 reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1); in ivtv_yuv_handle_vertical()
444 reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv); in ivtv_yuv_handle_vertical()
446 reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
447 reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
449 if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) { in ivtv_yuv_handle_vertical()
450 master_height = (f->src_h * 0x00400000) / f->dst_h; in ivtv_yuv_handle_vertical()
[all …]
/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_plane.c59 uint32_t src_w, uint32_t src_h);
147 state->src_w, state->src_h); in mdp4_plane_atomic_update()
220 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
243 src_h = src_h >> 16; in mdp4_plane_mode_set()
246 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
256 if (src_h > (crtc_h * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
266 if (crtc_h > (src_h * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
287 if (src_h != crtc_h) { in mdp4_plane_mode_set()
293 if (crtc_h > src_h) in mdp4_plane_mode_set()
295 else if (crtc_h <= (src_h / 4)) in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/vc4/
Dvc4_plane.c59 u32 src_w[2], src_h[2]; member
311 (state->src_h & subpixel_src_mask)) { in vc4_plane_setup_clipping_and_scaling()
318 vc4_state->src_h[0] = state->src_h >> 16; in vc4_plane_setup_clipping_and_scaling()
327 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], in vc4_plane_setup_clipping_and_scaling()
336 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; in vc4_plane_setup_clipping_and_scaling()
342 vc4_get_scaling_mode(vc4_state->src_h[1], in vc4_plane_setup_clipping_and_scaling()
390 vc4_state->src_h[0] += vc4_state->crtc_y; in vc4_plane_setup_clipping_and_scaling()
391 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample; in vc4_plane_setup_clipping_and_scaling()
471 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
484 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
[all …]
/drivers/gpu/drm/i915/
Dintel_sprite.c244 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in skl_update_plane() local
271 src_h--; in skl_update_plane()
277 I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w); in skl_update_plane()
391 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in vlv_update_plane() local
449 src_h--; in vlv_update_plane()
460 y += src_h; in vlv_update_plane()
530 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; in ivb_update_plane() local
576 src_h--; in ivb_update_plane()
580 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
581 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; in ivb_update_plane()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c472 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
505 src_h = c->top.input_viewport_size >> 16; in hqvdp_dbg_dump_cmd()
506 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
532 if (dst_h > src_h) in hqvdp_dbg_dump_cmd()
533 seq_printf(s, " %d/1", dst_h / src_h); in hqvdp_dbg_dump_cmd()
535 seq_printf(s, " 1/%d", src_h / dst_h); in hqvdp_dbg_dump_cmd()
727 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
736 inv_zy = DIV_ROUND_UP(src_h, dst_h); in sti_hqvdp_check_hw_scaling()
1020 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1036 src_h = state->src_h >> 16; in sti_hqvdp_atomic_check()
[all …]
Dsti_cursor.c192 int src_w, src_h; in sti_cursor_atomic_check() local
206 src_h = state->src_h >> 16; in sti_cursor_atomic_check()
209 src_h < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
211 src_h > STI_CURS_MAX_SIZE) { in sti_cursor_atomic_check()
213 src_w, src_h); in sti_cursor_atomic_check()
220 (cursor->height != src_h)) { in sti_cursor_atomic_check()
222 cursor->height = src_h; in sti_cursor_atomic_check()
Dsti_gdp.c621 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
639 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_check()
700 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
715 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
738 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_update()
769 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); in sti_gdp_atomic_update()
780 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
Dsti_vid.c147 int src_h = state->src_h >> 16; in sti_vid_commit() local
169 if (src_h >= VID_MIN_HD_HEIGHT) { in sti_vid_commit()
/drivers/gpu/drm/arm/
Dmalidp_planes.c90 u32 src_w, src_h; in malidp_de_plane_check() local
101 src_h = state->src_h >> 16; in malidp_de_plane_check()
107 (state->crtc_w != src_w) || (state->crtc_h != src_h)) in malidp_de_plane_check()
140 u32 format, src_w, src_h, dest_w, dest_h, val = 0; in malidp_de_plane_update() local
152 src_h = plane->state->src_h >> 16; in malidp_de_plane_update()
169 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
Dhdlcd_crtc.c208 u32 src_w, src_h; in hdlcd_plane_atomic_check() local
211 src_h = state->src_h >> 16; in hdlcd_plane_atomic_check()
214 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) in hdlcd_plane_atomic_check()
226 u32 src_w, src_h, dest_w, dest_h; in hdlcd_plane_atomic_update() local
234 src_h = plane->state->src_h >> 16; in hdlcd_plane_atomic_update()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c97 uint32_t src_w, uint32_t src_h) in nv10_update_plane() argument
115 src_h >>= 16; in nv10_update_plane()
123 if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) in nv10_update_plane()
126 if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) in nv10_update_plane()
141 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
144 nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); in nv10_update_plane()
348 uint32_t src_w, uint32_t src_h) in nv04_update_plane() argument
363 src_h >>= 16; in nv04_update_plane()
374 if (crtc_w < src_w || crtc_h < src_h) in nv04_update_plane()
396 …(uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - … in nv04_update_plane()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c51 uint32_t src_h; member
281 ((state->src_h - 1) << 16)); in atmel_hlcdc_plane_update_pos_and_size()
291 if (state->crtc_w != state->src_w || state->crtc_h != state->src_h) { in atmel_hlcdc_plane_update_pos_and_size()
317 if (state->crtc_h != state->src_h) { in atmel_hlcdc_plane_update_pos_and_size()
323 if (state->crtc_h < state->src_h) in atmel_hlcdc_plane_update_pos_and_size()
330 factor = ((8 * 256 * state->src_h) - (256 * 4)) / in atmel_hlcdc_plane_update_pos_and_size()
335 if (max_memsize > state->src_h) in atmel_hlcdc_plane_update_pos_and_size()
464 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
609 state->src_h = s->src_h; in atmel_hlcdc_plane_atomic_check()
615 if ((state->src_x | state->src_y | state->src_w | state->src_h) & in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_plane.c43 uint32_t src_w, uint32_t src_h);
303 ((state->src_h >> 16) != state->crtc_h))) { in mdp5_plane_atomic_check()
305 state->src_w >> 16, state->src_h >> 16, in mdp5_plane_atomic_check()
367 state->src_w, state->src_h); in mdp5_plane_atomic_update()
605 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) in mdp5_write_pixel_ext() argument
613 uint32_t roi_h = src_h; in mdp5_write_pixel_ext()
668 uint32_t src_w, uint32_t src_h) in mdp5_plane_mode_set() argument
699 src_h = src_h >> 16; in mdp5_plane_mode_set()
702 fb->base.id, src_x, src_y, src_w, src_h, in mdp5_plane_mode_set()
726 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step); in mdp5_plane_mode_set()
[all …]
/drivers/gpu/drm/
Ddrm_plane_helper.c136 src->y2 = state->src_y + state->src_h; in drm_plane_helper_check_state()
243 .src_h = drm_rect_height(src), in drm_plane_helper_check_update()
309 uint32_t src_w, uint32_t src_h) in drm_primary_helper_update() argument
322 .y2 = src_y + src_h, in drm_primary_helper_update()
551 uint32_t src_w, uint32_t src_h) in drm_plane_helper_update() argument
575 plane_state->src_h = src_h; in drm_plane_helper_update()
Ddrm_rect.c162 int src_h = drm_rect_height(src); in drm_rect_calc_vscale() local
164 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale()
249 int src_h = drm_rect_height(src); in drm_rect_calc_vscale_relaxed() local
251 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale_relaxed()
257 int max_dst_h = src_h / min_vscale; in drm_rect_calc_vscale_relaxed()
267 drm_rect_adjust_size(src, 0, max_src_h - src_h); in drm_rect_calc_vscale_relaxed()
Ddrm_plane.c456 uint32_t src_w, uint32_t src_h) in __setplane_internal() argument
500 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_internal()
507 src_x, src_y, src_w, src_h); in __setplane_internal()
533 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
540 src_x, src_y, src_w, src_h); in setplane_internal()
592 plane_req->src_w, plane_req->src_h); in drm_mode_setplane()
610 uint32_t src_w = 0, src_h = 0; in drm_mode_cursor_universal() local
651 src_h = fb->height << 16; in drm_mode_cursor_universal()
660 0, 0, src_w, src_h); in drm_mode_cursor_universal()
848 state->src_h, in drm_mode_page_flip_ioctl()
Ddrm_framebuffer.c66 uint32_t src_w, uint32_t src_h, in drm_framebuffer_check_src_coords() argument
77 src_h > fb_height || in drm_framebuffer_check_src_coords()
78 src_y > fb_height - src_h) { in drm_framebuffer_check_src_coords()
82 src_h >> 16, ((src_h & 0xffff) * 15625) >> 10, in drm_framebuffer_check_src_coords()
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c90 cpu_to_le32(plane->state->src_h >> 16), in virtio_gpu_primary_plane_update()
102 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
107 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
114 plane->state->src_h >> 16); in virtio_gpu_primary_plane_update()
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c70 unsigned int src_w, src_h; in exynos_plane_mode_set() local
88 src_h = state->src_h >> 16; in exynos_plane_mode_set()
92 exynos_state->v_ratio = (src_h << 16) / crtc_h; in exynos_plane_mode_set()
/drivers/gpu/drm/omapdrm/
Domap_plane.c114 win.src_w = state->src_h >> 16; in omap_plane_atomic_update()
115 win.src_h = state->src_w >> 16; in omap_plane_atomic_update()
119 win.src_h = state->src_h >> 16; in omap_plane_atomic_update()
/drivers/gpu/drm/imx/
Dipuv3-plane.c282 state->src_h >> 16 != state->crtc_h) in ipu_plane_atomic_check()
324 state->src_h != old_state->src_h || in ipu_plane_atomic_check()
449 state->src_h >> 16); in ipu_plane_atomic_update()
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c776 u32 src_y, u32 src_w, u32 src_h) in ade_update_channel() argument
786 ch + 1, src_x, src_y, src_w, src_h, in ade_update_channel()
791 in_h = src_h; in ade_update_channel()
832 u32 src_h = state->src_h >> 16; in ade_plane_atomic_check() local
850 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
856 src_y + src_h > fb->height) in ade_plane_atomic_check()
878 state->src_w >> 16, state->src_h >> 16); in ade_plane_atomic_update()
/drivers/gpu/drm/rcar-du/
Drcar_du_vsp.c45 .src_h = mode->vdisplay << 16, in rcar_du_vsp_enable()
162 cfg.src.height = state->state.src_h >> 16; in rcar_du_vsp_plane_setup()
199 state->src_h >> 16 != state->crtc_h) { in rcar_du_vsp_plane_atomic_check()

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