| /drivers/media/platform/ti-vpe/ |
| D | sc.c | 60 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w, in sc_set_hs_coeffs() argument
69 if (dst_w > src_w) { in sc_set_hs_coeffs()
72 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
74 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
77 if (dst_w == src_w) { in sc_set_hs_coeffs()
80 sixteenths = (dst_w << 4) / src_w; in sc_set_hs_coeffs()
154 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
184 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
196 dcm_x = src_w / dst_w; in sc_config_scaler()
208 lin_acc_inc = div64_u64(((u64)(src_w >> dcm_shift) - 1) << 24, lltmp); in sc_config_scaler()
[all …]
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| D | sc.h | 199 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
204 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
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| /drivers/media/pci/ivtv/ |
| D | ivtv-yuv.c | 241 f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x); in ivtv_yuv_handle_horizontal()
244 x_cutoff = f->src_w + f->src_x; in ivtv_yuv_handle_horizontal()
268 if (f->dst_w >= f->src_w) in ivtv_yuv_handle_horizontal()
274 if (f->dst_w < f->src_w) in ivtv_yuv_handle_horizontal()
280 reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19; in ivtv_yuv_handle_horizontal()
282 if (f->dst_w >= f->src_w) { in ivtv_yuv_handle_horizontal()
284 master_width = (f->src_w * 0x00200000) / (f->dst_w); in ivtv_yuv_handle_horizontal()
285 if (master_width * f->dst_w != f->src_w * 0x00200000) in ivtv_yuv_handle_horizontal()
297 if (f->dst_w > f->src_w) in ivtv_yuv_handle_horizontal()
298 reg_2870_base = ((f->dst_w - f->src_w)<<16) / (f->src_w <<14); in ivtv_yuv_handle_horizontal()
[all …]
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| /drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4_plane.c | 59 uint32_t src_w, uint32_t src_h);
147 state->src_w, state->src_h); in mdp4_plane_atomic_update()
220 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
242 src_w = src_w >> 16; in mdp4_plane_mode_set()
246 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
251 if (src_w > (crtc_w * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
261 if (crtc_w > (src_w * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
271 if (src_w != crtc_w) { in mdp4_plane_mode_set()
276 if (crtc_w > src_w) in mdp4_plane_mode_set()
278 else if (crtc_w <= (src_w / 4)) in mdp4_plane_mode_set()
[all …]
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| /drivers/gpu/drm/vc4/ |
| D | vc4_plane.c | 59 u32 src_w[2], src_h[2]; member
310 (state->src_w & subpixel_src_mask) || in vc4_plane_setup_clipping_and_scaling()
317 vc4_state->src_w[0] = state->src_w >> 16; in vc4_plane_setup_clipping_and_scaling()
325 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], in vc4_plane_setup_clipping_and_scaling()
335 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; in vc4_plane_setup_clipping_and_scaling()
339 vc4_get_scaling_mode(vc4_state->src_w[1], in vc4_plane_setup_clipping_and_scaling()
378 vc4_state->src_w[0] += vc4_state->crtc_x; in vc4_plane_setup_clipping_and_scaling()
379 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample; in vc4_plane_setup_clipping_and_scaling()
432 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); in vc4_lbm_size()
465 vc4_state->src_w[channel], vc4_state->crtc_w); in vc4_write_scaling_parameters()
[all …]
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| /drivers/gpu/drm/i915/ |
| D | intel_sprite.c | 243 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in skl_update_plane() local
270 src_w--; in skl_update_plane()
277 I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w); in skl_update_plane()
390 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in vlv_update_plane() local
448 src_w--; in vlv_update_plane()
459 x += src_w; in vlv_update_plane()
529 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; in ivb_update_plane() local
575 src_w--; in ivb_update_plane()
580 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
581 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; in ivb_update_plane()
[all …]
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| D | intel_overlay.c | 507 short src_w; member
823 tmp_width = packed_width_bytes(params->format, params->src_w); in intel_overlay_do_put_image()
825 tmp_width = params->src_w; in intel_overlay_do_put_image()
827 swidth = params->src_w; in intel_overlay_do_put_image()
837 swidth |= (params->src_w/uv_hscale) << 16; in intel_overlay_do_put_image()
839 params->src_w/uv_hscale); in intel_overlay_do_put_image()
841 params->src_w/uv_hscale); in intel_overlay_do_put_image()
1204 params->src_w = put_image_rec->src_width; in intel_overlay_put_image_ioctl()
1209 params->src_scan_w > params->src_w) { in intel_overlay_put_image_ioctl()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | overlay.c | 97 uint32_t src_w, uint32_t src_h) in nv10_update_plane() argument
114 src_w >>= 16; in nv10_update_plane()
117 format = ALIGN(src_w * 4, 0x100); in nv10_update_plane()
123 if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) in nv10_update_plane()
126 if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) in nv10_update_plane()
141 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
143 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
348 uint32_t src_w, uint32_t src_h) in nv04_update_plane() argument
362 src_w >>= 16; in nv04_update_plane()
365 pitch = ALIGN(src_w * 4, 0x100); in nv04_update_plane()
[all …]
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| /drivers/gpu/drm/sti/ |
| D | sti_hqvdp.c | 472 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
504 src_w = c->top.input_viewport_size & 0x0000FFFF; in hqvdp_dbg_dump_cmd()
506 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
526 if (dst_w > src_w) in hqvdp_dbg_dump_cmd()
527 seq_printf(s, " %d/1", dst_w / src_w); in hqvdp_dbg_dump_cmd()
529 seq_printf(s, " 1/%d", src_w / dst_w); in hqvdp_dbg_dump_cmd()
727 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
734 lfw /= max(src_w, dst_w) * mode->clock / 1000; in sti_hqvdp_check_hw_scaling()
1020 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1035 src_w = state->src_w >> 16; in sti_hqvdp_atomic_check()
[all …]
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| D | sti_cursor.c | 192 int src_w, src_h; in sti_cursor_atomic_check() local
205 src_w = state->src_w >> 16; in sti_cursor_atomic_check()
208 if (src_w < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
210 src_w > STI_CURS_MAX_SIZE || in sti_cursor_atomic_check()
213 src_w, src_h); in sti_cursor_atomic_check()
219 (cursor->width != src_w) || in sti_cursor_atomic_check()
221 cursor->width = src_w; in sti_cursor_atomic_check()
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| D | sti_gdp.c | 621 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
638 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); in sti_gdp_atomic_check()
700 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
715 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
737 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); in sti_gdp_atomic_update()
768 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); in sti_gdp_atomic_update()
778 src_w = dst_w; in sti_gdp_atomic_update()
780 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
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| /drivers/gpu/drm/arm/ |
| D | malidp_planes.c | 90 u32 src_w, src_h; in malidp_de_plane_check() local
100 src_w = state->src_w >> 16; in malidp_de_plane_check()
107 (state->crtc_w != src_w) || (state->crtc_h != src_h)) in malidp_de_plane_check()
140 u32 format, src_w, src_h, dest_w, dest_h, val = 0; in malidp_de_plane_update() local
151 src_w = plane->state->src_w >> 16; in malidp_de_plane_update()
169 malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), in malidp_de_plane_update()
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| D | hdlcd_crtc.c | 208 u32 src_w, src_h; in hdlcd_plane_atomic_check() local
210 src_w = state->src_w >> 16; in hdlcd_plane_atomic_check()
214 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) in hdlcd_plane_atomic_check()
226 u32 src_w, src_h, dest_w, dest_h; in hdlcd_plane_atomic_update() local
233 src_w = plane->state->src_w >> 16; in hdlcd_plane_atomic_update()
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_plane.c | 43 uint32_t src_w, uint32_t src_h);
302 (((state->src_w >> 16) != state->crtc_w) || in mdp5_plane_atomic_check()
305 state->src_w >> 16, state->src_h >> 16, in mdp5_plane_atomic_check()
328 if (state->src_w != old_state->src_w) { in mdp5_plane_atomic_check()
367 state->src_w, state->src_h); in mdp5_plane_atomic_update()
604 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], in mdp5_write_pixel_ext() argument
612 uint32_t roi_w = src_w; in mdp5_write_pixel_ext()
668 uint32_t src_w, uint32_t src_h) in mdp5_plane_mode_set() argument
698 src_w = src_w >> 16; in mdp5_plane_mode_set()
702 fb->base.id, src_x, src_y, src_w, src_h, in mdp5_plane_mode_set()
[all …]
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| /drivers/gpu/drm/atmel-hlcdc/ |
| D | atmel_hlcdc_plane.c | 50 uint32_t src_w; member
280 (state->src_w - 1) | in atmel_hlcdc_plane_update_pos_and_size()
291 if (state->crtc_w != state->src_w || state->crtc_h != state->src_h) { in atmel_hlcdc_plane_update_pos_and_size()
294 if (state->crtc_w != state->src_w) { in atmel_hlcdc_plane_update_pos_and_size()
300 if (state->crtc_w < state->src_w) in atmel_hlcdc_plane_update_pos_and_size()
307 factor = ((8 * 256 * state->src_w) - (256 * 4)) / in atmel_hlcdc_plane_update_pos_and_size()
312 if (max_memsize > state->src_w) in atmel_hlcdc_plane_update_pos_and_size()
464 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
610 state->src_w = s->src_w; in atmel_hlcdc_plane_atomic_check()
615 if ((state->src_x | state->src_y | state->src_w | state->src_h) & in atmel_hlcdc_plane_atomic_check()
[all …]
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| /drivers/gpu/drm/ |
| D | drm_plane_helper.c | 135 src->x2 = state->src_x + state->src_w; in drm_plane_helper_check_state()
242 .src_w = drm_rect_width(src), in drm_plane_helper_check_update()
309 uint32_t src_w, uint32_t src_h) in drm_primary_helper_update() argument
321 .x2 = src_x + src_w, in drm_primary_helper_update()
551 uint32_t src_w, uint32_t src_h) in drm_plane_helper_update() argument
576 plane_state->src_w = src_w; in drm_plane_helper_update()
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| D | drm_rect.c | 131 int src_w = drm_rect_width(src); in drm_rect_calc_hscale() local
133 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale()
199 int src_w = drm_rect_width(src); in drm_rect_calc_hscale_relaxed() local
201 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale_relaxed()
207 int max_dst_w = src_w / min_hscale; in drm_rect_calc_hscale_relaxed()
217 drm_rect_adjust_size(src, max_src_w - src_w, 0); in drm_rect_calc_hscale_relaxed()
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| D | drm_plane.c | 456 uint32_t src_w, uint32_t src_h) in __setplane_internal() argument
500 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_internal()
507 src_x, src_y, src_w, src_h); in __setplane_internal()
533 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
540 src_x, src_y, src_w, src_h); in setplane_internal()
592 plane_req->src_w, plane_req->src_h); in drm_mode_setplane()
610 uint32_t src_w = 0, src_h = 0; in drm_mode_cursor_universal() local
650 src_w = fb->width << 16; in drm_mode_cursor_universal()
660 0, 0, src_w, src_h); in drm_mode_cursor_universal()
847 state->src_w, in drm_mode_page_flip_ioctl()
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| D | drm_framebuffer.c | 66 uint32_t src_w, uint32_t src_h, in drm_framebuffer_check_src_coords() argument
75 if (src_w > fb_width || in drm_framebuffer_check_src_coords()
76 src_x > fb_width - src_w || in drm_framebuffer_check_src_coords()
81 src_w >> 16, ((src_w & 0xffff) * 15625) >> 10, in drm_framebuffer_check_src_coords()
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| /drivers/gpu/drm/virtio/ |
| D | virtgpu_plane.c | 89 cpu_to_le32(plane->state->src_w >> 16), in virtio_gpu_primary_plane_update()
101 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
106 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
113 plane->state->src_w >> 16, in virtio_gpu_primary_plane_update()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_plane.c | 70 unsigned int src_w, src_h; in exynos_plane_mode_set() local
87 src_w = state->src_w >> 16; in exynos_plane_mode_set()
91 exynos_state->h_ratio = (src_w << 16) / crtc_w; in exynos_plane_mode_set()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_plane.c | 114 win.src_w = state->src_h >> 16; in omap_plane_atomic_update()
115 win.src_h = state->src_w >> 16; in omap_plane_atomic_update()
118 win.src_w = state->src_w >> 16; in omap_plane_atomic_update()
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| /drivers/gpu/drm/imx/ |
| D | ipuv3-plane.c | 281 if (state->src_w >> 16 != state->crtc_w || in ipu_plane_atomic_check()
323 if (old_fb && (state->src_w != old_state->src_w || in ipu_plane_atomic_check()
448 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, state->src_w >> 16, in ipu_plane_atomic_update()
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_drm_ade.c | 776 u32 src_y, u32 src_w, u32 src_h) in ade_update_channel() argument
786 ch + 1, src_x, src_y, src_w, src_h, in ade_update_channel()
790 in_w = src_w; in ade_update_channel()
831 u32 src_w = state->src_w >> 16; in ade_plane_atomic_check() local
850 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
855 if (src_x + src_w > fb->width || in ade_plane_atomic_check()
878 state->src_w >> 16, state->src_h >> 16); in ade_plane_atomic_update()
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_du_vsp.c | 44 .src_w = mode->hdisplay << 16, in rcar_du_vsp_enable()
161 cfg.src.width = state->state.src_w >> 16; in rcar_du_vsp_plane_setup()
198 if (state->src_w >> 16 != state->crtc_w || in rcar_du_vsp_plane_atomic_check()
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