| /drivers/tty/serial/ |
| D | etraxfs-uart.c | 656 reg_ser_rw_tr_ctrl tx_ctrl = {0}; in etraxfs_uart_set_termios() local
669 tx_ctrl.base_freq = regk_ser_f29_493; in etraxfs_uart_set_termios()
670 tx_ctrl.en = 0; in etraxfs_uart_set_termios()
671 tx_ctrl.stop = 0; in etraxfs_uart_set_termios()
672 tx_ctrl.auto_rts = regk_ser_no; in etraxfs_uart_set_termios()
673 tx_ctrl.txd = 1; in etraxfs_uart_set_termios()
674 tx_ctrl.auto_cts = 0; in etraxfs_uart_set_termios()
683 tx_ctrl.data_bits = regk_ser_bits8; in etraxfs_uart_set_termios()
685 tx_ctrl.par = regk_ser_even; in etraxfs_uart_set_termios()
687 tx_ctrl.par_en = regk_ser_no; in etraxfs_uart_set_termios()
[all …]
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| D | crisv10.c | 245 .tx_ctrl = DEF_TX,
297 .tx_ctrl = DEF_TX,
352 .tx_ctrl = DEF_TX,
405 .tx_ctrl = DEF_TX,
2727 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40); in shutdown()
2860 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) | in change_speed()
2868 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); in change_speed()
2874 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits); in change_speed()
2879 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); in change_speed()
2885 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick); in change_speed()
[all …]
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| D | crisv10.h | 57 u8 tx_ctrl; /* shadow for R_SERIALx_TR_CTRL */ member
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| /drivers/net/ethernet/hisilicon/hns/ |
| D | hns_dsaf_gmac.c | 197 u32 tx_ctrl; in hns_gmac_port_mode_get() local
204 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_port_mode_get()
215 port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B); in hns_gmac_port_mode_get()
216 port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B); in hns_gmac_port_mode_get()
217 port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B); in hns_gmac_port_mode_get()
252 u32 tx_ctrl; in hns_gmac_adjust_link() local
281 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_adjust_link()
282 dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1); in hns_gmac_adjust_link()
283 dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1); in hns_gmac_adjust_link()
284 dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); in hns_gmac_adjust_link()
[all …]
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| D | hns_dsaf_mac.h | 303 u64 tx_ctrl; /* only for xgmac */ member
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| D | hns_dsaf_xgmac.c | 47 {"xgmac_tx_mac_ctrol_frame", MAC_STATS_FIELD_OFF(tx_ctrl)},
354 hw_stats->tx_ctrl = hns_mac_reg_read64(drv, XGMAC_TX_MACCTRLPKTS); in hns_xgmac_update_stats()
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| /drivers/net/ethernet/seeq/ |
| D | sgiseeq.c | 134 hregs->rx_ctrl = hregs->tx_ctrl = 0; in reset_hpc3_and_seeq()
279 hregs->tx_cbptr, hregs->tx_ndptr, hregs->tx_ctrl); in sgiseeq_dump_rings()
446 hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; in kick_tx()
455 unsigned long status = hregs->tx_ctrl; in sgiseeq_tx()
480 hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; in sgiseeq_tx()
636 if (!(hregs->tx_ctrl & HPC3_ETXCTRL_ACTIVE)) in sgiseeq_start_xmit()
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| /drivers/net/hippi/ |
| D | rrunner.c | 605 rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc); in rr_init1()
606 rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES; in rr_init1()
607 rrpriv->info->tx_ctrl.mode = 0; in rr_init1()
608 rrpriv->info->tx_ctrl.pi = 0; in rr_init1()
609 set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma); in rr_init1()
1091 (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES) in rr_interrupt()
1280 rrpriv->info->tx_ctrl.pi); in rr_dump()
1368 rrpriv->info->tx_ctrl.entries = 0; in rr_close()
1436 txctrl = &rrpriv->info->tx_ctrl; in rr_start_xmit()
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| D | rrunner.h | 787 struct ring_ctrl tx_ctrl; member
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| /drivers/net/ethernet/nvidia/ |
| D | forcedeth.c | 1575 u32 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_start_tx() local
1577 tx_ctrl |= NVREG_XMITCTL_START; in nv_start_tx()
1579 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; in nv_start_tx()
1580 writel(tx_ctrl, base + NvRegTransmitterControl); in nv_start_tx()
1588 u32 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_stop_tx() local
1591 tx_ctrl &= ~NVREG_XMITCTL_START; in nv_stop_tx()
1593 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; in nv_stop_tx()
1594 writel(tx_ctrl, base + NvRegTransmitterControl); in nv_stop_tx()
5273 u32 tx_ctrl, mgmt_sema; in nv_mgmt_acquire_sema() local
5286 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_mgmt_acquire_sema()
[all …]
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| /drivers/net/ethernet/qualcomm/emac/ |
| D | emac.h | 207 u64 tx_ctrl; /* control packets other than pause frame */ member
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| /drivers/net/ethernet/atheros/atl1e/ |
| D | atl1e.h | 292 …unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding P… member
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| /drivers/net/ethernet/atheros/alx/ |
| D | hw.h | 426 u64 tx_ctrl; /* TX control frames, excluding pause frames */ member
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| D | hw.c | 1102 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); in alx_update_hw_stats()
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| /drivers/net/ethernet/atheros/atl1c/ |
| D | atl1c.h | 345 …unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause f… member
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| /drivers/net/ethernet/atheros/atlx/ |
| D | atl1.h | 355 u32 tx_ctrl; /* TX control frames, excluding pause frames */ member
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| /drivers/net/ethernet/alteon/ |
| D | acenic.h | 579 struct ring_ctrl tx_ctrl; member
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| D | acenic.c | 1291 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); in ace_init()
1296 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); in ace_init()
1299 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); in ace_init()
1310 info->tx_ctrl.flags = tmp; in ace_init()
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| /drivers/net/wireless/ti/wlcore/ |
| D | acx.h | 529 __le32 tx_ctrl; member
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