Home
last modified time | relevance | path

Searched refs:vddc_dependency_on_mclk (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/powerplay/hwmgr/
Dprocesspptables.c1180 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1290 &hwmgr->dyn_state.vddc_dependency_on_mclk, table); in init_clock_voltage_dependency()
1301 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && in init_clock_voltage_dependency()
1302 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) in init_clock_voltage_dependency()
1304 hwmgr->dyn_state.vddc_dependency_on_mclk); in init_clock_voltage_dependency()
1618 if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) { in pp_tables_uninitialize()
1619 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); in pp_tables_uninitialize()
1620 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in pp_tables_uninitialize()
Dsmu7_hwmgr.c289 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
663 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
2175 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_patch_dependency_tables_with_leakage()
2228 …clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_set_private_data_based_on_pptable_v0()
4288 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_get_mclks()
/drivers/gpu/drm/radeon/
Dr600_dpm.c944 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in r600_parse_extended_power_table()
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); in r600_parse_extended_power_table()
1302 kfree(dyn_state->vddc_dependency_on_mclk.entries); in r600_free_extended_power_table()
Dbtc_dpm.c2212 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in btc_apply_state_adjust_rules()
2221 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in btc_apply_state_adjust_rules()
2230 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in btc_apply_state_adjust_rules()
Dci_dpm.c2129 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2583 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2584 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2865 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2867 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
3429 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
4903 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5049 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
Dsi_dpm.c3107 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
4031 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
5960 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
Dni_dpm.c879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
Dradeon.h1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; member
/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smc.c1106 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { in iceland_populate_single_memory_level()
1108 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); in iceland_populate_single_memory_level()
1726 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count); in iceland_populate_smc_initial_state()
1729 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk in iceland_populate_smc_initial_state()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_dpm.c389 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
757 kfree(dyn_state->vddc_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
Dci_dpm.c2259 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2710 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2711 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2997 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2999 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
3562 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
5049 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5195 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
Dsi_dpm.c3585 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3693 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
4512 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
6436 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
Damdgpu.h1481 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; member
/drivers/gpu/drm/amd/powerplay/inc/
Dhwmgr.h499 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; member