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1 #ifndef _QIB_KERNEL_H
2 #define _QIB_KERNEL_H
3 /*
4  * Copyright (c) 2012, 2013 Intel Corporation.  All rights reserved.
5  * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
6  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7  *
8  * This software is available to you under a choice of one of two
9  * licenses.  You may choose to be licensed under the terms of the GNU
10  * General Public License (GPL) Version 2, available from the file
11  * COPYING in the main directory of this source tree, or the
12  * OpenIB.org BSD license below:
13  *
14  *     Redistribution and use in source and binary forms, with or
15  *     without modification, are permitted provided that the following
16  *     conditions are met:
17  *
18  *      - Redistributions of source code must retain the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer.
21  *
22  *      - Redistributions in binary form must reproduce the above
23  *        copyright notice, this list of conditions and the following
24  *        disclaimer in the documentation and/or other materials
25  *        provided with the distribution.
26  *
27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34  * SOFTWARE.
35  */
36 
37 /*
38  * This header file is the base header file for qlogic_ib kernel code
39  * qib_user.h serves a similar purpose for user code.
40  */
41 
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/mutex.h>
46 #include <linux/list.h>
47 #include <linux/scatterlist.h>
48 #include <linux/slab.h>
49 #include <linux/io.h>
50 #include <linux/fs.h>
51 #include <linux/completion.h>
52 #include <linux/kref.h>
53 #include <linux/sched.h>
54 #include <linux/kthread.h>
55 #include <rdma/ib_hdrs.h>
56 #include <rdma/rdma_vt.h>
57 
58 #include "qib_common.h"
59 #include "qib_verbs.h"
60 
61 /* only s/w major version of QLogic_IB we can handle */
62 #define QIB_CHIP_VERS_MAJ 2U
63 
64 /* don't care about this except printing */
65 #define QIB_CHIP_VERS_MIN 0U
66 
67 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
68 #define QIB_OUI 0x001175
69 #define QIB_OUI_LSB 40
70 
71 /*
72  * per driver stats, either not device nor port-specific, or
73  * summed over all of the devices and ports.
74  * They are described by name via ipathfs filesystem, so layout
75  * and number of elements can change without breaking compatibility.
76  * If members are added or deleted qib_statnames[] in qib_fs.c must
77  * change to match.
78  */
79 struct qlogic_ib_stats {
80 	__u64 sps_ints; /* number of interrupts handled */
81 	__u64 sps_errints; /* number of error interrupts */
82 	__u64 sps_txerrs; /* tx-related packet errors */
83 	__u64 sps_rcverrs; /* non-crc rcv packet errors */
84 	__u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
85 	__u64 sps_nopiobufs; /* no pio bufs avail from kernel */
86 	__u64 sps_ctxts; /* number of contexts currently open */
87 	__u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
88 	__u64 sps_buffull;
89 	__u64 sps_hdrfull;
90 };
91 
92 extern struct qlogic_ib_stats qib_stats;
93 extern const struct pci_error_handlers qib_pci_err_handler;
94 
95 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
96 /*
97  * First-cut critierion for "device is active" is
98  * two thousand dwords combined Tx, Rx traffic per
99  * 5-second interval. SMA packets are 64 dwords,
100  * and occur "a few per second", presumably each way.
101  */
102 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
103 
104 /*
105  * Struct used to indicate which errors are logged in each of the
106  * error-counters that are logged to EEPROM. A counter is incremented
107  * _once_ (saturating at 255) for each event with any bits set in
108  * the error or hwerror register masks below.
109  */
110 #define QIB_EEP_LOG_CNT (4)
111 struct qib_eep_log_mask {
112 	u64 errs_to_log;
113 	u64 hwerrs_to_log;
114 };
115 
116 /*
117  * Below contains all data related to a single context (formerly called port).
118  */
119 
120 #ifdef CONFIG_DEBUG_FS
121 struct qib_opcode_stats_perctx;
122 #endif
123 
124 struct qib_ctxtdata {
125 	void **rcvegrbuf;
126 	dma_addr_t *rcvegrbuf_phys;
127 	/* rcvhdrq base, needs mmap before useful */
128 	void *rcvhdrq;
129 	/* kernel virtual address where hdrqtail is updated */
130 	void *rcvhdrtail_kvaddr;
131 	/*
132 	 * temp buffer for expected send setup, allocated at open, instead
133 	 * of each setup call
134 	 */
135 	void *tid_pg_list;
136 	/*
137 	 * Shared page for kernel to signal user processes that send buffers
138 	 * need disarming.  The process should call QIB_CMD_DISARM_BUFS
139 	 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
140 	 */
141 	unsigned long *user_event_mask;
142 	/* when waiting for rcv or pioavail */
143 	wait_queue_head_t wait;
144 	/*
145 	 * rcvegr bufs base, physical, must fit
146 	 * in 44 bits so 32 bit programs mmap64 44 bit works)
147 	 */
148 	dma_addr_t rcvegr_phys;
149 	/* mmap of hdrq, must fit in 44 bits */
150 	dma_addr_t rcvhdrq_phys;
151 	dma_addr_t rcvhdrqtailaddr_phys;
152 
153 	/*
154 	 * number of opens (including slave sub-contexts) on this instance
155 	 * (ignoring forks, dup, etc. for now)
156 	 */
157 	int cnt;
158 	/*
159 	 * how much space to leave at start of eager TID entries for
160 	 * protocol use, on each TID
161 	 */
162 	/* instead of calculating it */
163 	unsigned ctxt;
164 	/* local node of context */
165 	int node_id;
166 	/* non-zero if ctxt is being shared. */
167 	u16 subctxt_cnt;
168 	/* non-zero if ctxt is being shared. */
169 	u16 subctxt_id;
170 	/* number of eager TID entries. */
171 	u16 rcvegrcnt;
172 	/* index of first eager TID entry. */
173 	u16 rcvegr_tid_base;
174 	/* number of pio bufs for this ctxt (all procs, if shared) */
175 	u32 piocnt;
176 	/* first pio buffer for this ctxt */
177 	u32 pio_base;
178 	/* chip offset of PIO buffers for this ctxt */
179 	u32 piobufs;
180 	/* how many alloc_pages() chunks in rcvegrbuf_pages */
181 	u32 rcvegrbuf_chunks;
182 	/* how many egrbufs per chunk */
183 	u16 rcvegrbufs_perchunk;
184 	/* ilog2 of above */
185 	u16 rcvegrbufs_perchunk_shift;
186 	/* order for rcvegrbuf_pages */
187 	size_t rcvegrbuf_size;
188 	/* rcvhdrq size (for freeing) */
189 	size_t rcvhdrq_size;
190 	/* per-context flags for fileops/intr communication */
191 	unsigned long flag;
192 	/* next expected TID to check when looking for free */
193 	u32 tidcursor;
194 	/* WAIT_RCV that timed out, no interrupt */
195 	u32 rcvwait_to;
196 	/* WAIT_PIO that timed out, no interrupt */
197 	u32 piowait_to;
198 	/* WAIT_RCV already happened, no wait */
199 	u32 rcvnowait;
200 	/* WAIT_PIO already happened, no wait */
201 	u32 pionowait;
202 	/* total number of polled urgent packets */
203 	u32 urgent;
204 	/* saved total number of polled urgent packets for poll edge trigger */
205 	u32 urgent_poll;
206 	/* pid of process using this ctxt */
207 	pid_t pid;
208 	pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
209 	/* same size as task_struct .comm[], command that opened context */
210 	char comm[16];
211 	/* pkeys set by this use of this ctxt */
212 	u16 pkeys[4];
213 	/* so file ops can get at unit */
214 	struct qib_devdata *dd;
215 	/* so funcs that need physical port can get it easily */
216 	struct qib_pportdata *ppd;
217 	/* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
218 	void *subctxt_uregbase;
219 	/* An array of pages for the eager receive buffers * N */
220 	void *subctxt_rcvegrbuf;
221 	/* An array of pages for the eager header queue entries * N */
222 	void *subctxt_rcvhdr_base;
223 	/* The version of the library which opened this ctxt */
224 	u32 userversion;
225 	/* Bitmask of active slaves */
226 	u32 active_slaves;
227 	/* Type of packets or conditions we want to poll for */
228 	u16 poll_type;
229 	/* receive packet sequence counter */
230 	u8 seq_cnt;
231 	u8 redirect_seq_cnt;
232 	/* ctxt rcvhdrq head offset */
233 	u32 head;
234 	/* QPs waiting for context processing */
235 	struct list_head qp_wait_list;
236 #ifdef CONFIG_DEBUG_FS
237 	/* verbs stats per CTX */
238 	struct qib_opcode_stats_perctx *opstats;
239 #endif
240 };
241 
242 struct rvt_sge_state;
243 
244 struct qib_sdma_txreq {
245 	int                 flags;
246 	int                 sg_count;
247 	dma_addr_t          addr;
248 	void              (*callback)(struct qib_sdma_txreq *, int);
249 	u16                 start_idx;  /* sdma private */
250 	u16                 next_descq_idx;  /* sdma private */
251 	struct list_head    list;       /* sdma private */
252 };
253 
254 struct qib_sdma_desc {
255 	__le64 qw[2];
256 };
257 
258 struct qib_verbs_txreq {
259 	struct qib_sdma_txreq   txreq;
260 	struct rvt_qp           *qp;
261 	struct rvt_swqe         *wqe;
262 	u32                     dwords;
263 	u16                     hdr_dwords;
264 	u16                     hdr_inx;
265 	struct qib_pio_header	*align_buf;
266 	struct rvt_mregion	*mr;
267 	struct rvt_sge_state    *ss;
268 };
269 
270 #define QIB_SDMA_TXREQ_F_USELARGEBUF  0x1
271 #define QIB_SDMA_TXREQ_F_HEADTOHOST   0x2
272 #define QIB_SDMA_TXREQ_F_INTREQ       0x4
273 #define QIB_SDMA_TXREQ_F_FREEBUF      0x8
274 #define QIB_SDMA_TXREQ_F_FREEDESC     0x10
275 
276 #define QIB_SDMA_TXREQ_S_OK        0
277 #define QIB_SDMA_TXREQ_S_SENDERROR 1
278 #define QIB_SDMA_TXREQ_S_ABORTED   2
279 #define QIB_SDMA_TXREQ_S_SHUTDOWN  3
280 
281 /*
282  * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
283  * Mostly for MADs that set or query link parameters, also ipath
284  * config interfaces
285  */
286 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
287 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
288 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */
289 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
290 #define QIB_IB_CFG_SPD 5 /* current Link spd */
291 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
292 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
293 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
294 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
295 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
296 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
297 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
298 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
299 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
300 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
301 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */
302 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
303 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
304 #define QIB_IB_CFG_VL_HIGH_LIMIT 19
305 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
306 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
307 
308 /*
309  * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
310  * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
311  * QIB_IB_CFG_LINKDEFAULT cmd
312  */
313 #define   IB_LINKCMD_DOWN   (0 << 16)
314 #define   IB_LINKCMD_ARMED  (1 << 16)
315 #define   IB_LINKCMD_ACTIVE (2 << 16)
316 #define   IB_LINKINITCMD_NOP     0
317 #define   IB_LINKINITCMD_POLL    1
318 #define   IB_LINKINITCMD_SLEEP   2
319 #define   IB_LINKINITCMD_DISABLE 3
320 
321 /*
322  * valid states passed to qib_set_linkstate() user call
323  */
324 #define QIB_IB_LINKDOWN         0
325 #define QIB_IB_LINKARM          1
326 #define QIB_IB_LINKACTIVE       2
327 #define QIB_IB_LINKDOWN_ONLY    3
328 #define QIB_IB_LINKDOWN_SLEEP   4
329 #define QIB_IB_LINKDOWN_DISABLE 5
330 
331 /*
332  * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
333  * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
334  * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs.  They
335  * are also the the possible values for qib_link_speed_enabled and active
336  * The values were chosen to match values used within the IB spec.
337  */
338 #define QIB_IB_SDR 1
339 #define QIB_IB_DDR 2
340 #define QIB_IB_QDR 4
341 
342 #define QIB_DEFAULT_MTU 4096
343 
344 /* max number of IB ports supported per HCA */
345 #define QIB_MAX_IB_PORTS 2
346 
347 /*
348  * Possible IB config parameters for f_get/set_ib_table()
349  */
350 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
351 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
352 
353 /*
354  * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
355  * these are bits so they can be combined, e.g.
356  * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
357  */
358 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
359 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
360 #define QIB_RCVCTRL_CTXT_ENB 0x04
361 #define QIB_RCVCTRL_CTXT_DIS 0x08
362 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
363 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
364 #define QIB_RCVCTRL_PKEY_ENB 0x40  /* Note, default is enabled */
365 #define QIB_RCVCTRL_PKEY_DIS 0x80
366 #define QIB_RCVCTRL_BP_ENB 0x0100
367 #define QIB_RCVCTRL_BP_DIS 0x0200
368 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
369 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
370 
371 /*
372  * Possible "operations" for f_sendctrl(ppd, op, var)
373  * these are bits so they can be combined, e.g.
374  * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
375  * Some operations (e.g. DISARM, ABORT) are known to
376  * be "one-shot", so do not modify shadow.
377  */
378 #define QIB_SENDCTRL_DISARM       (0x1000)
379 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
380 	/* available (0x2000) */
381 #define QIB_SENDCTRL_AVAIL_DIS    (0x4000)
382 #define QIB_SENDCTRL_AVAIL_ENB    (0x8000)
383 #define QIB_SENDCTRL_AVAIL_BLIP  (0x10000)
384 #define QIB_SENDCTRL_SEND_DIS    (0x20000)
385 #define QIB_SENDCTRL_SEND_ENB    (0x40000)
386 #define QIB_SENDCTRL_FLUSH       (0x80000)
387 #define QIB_SENDCTRL_CLEAR      (0x100000)
388 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
389 
390 /*
391  * These are the generic indices for requesting per-port
392  * counter values via the f_portcntr function.  They
393  * are always returned as 64 bit values, although most
394  * are 32 bit counters.
395  */
396 /* send-related counters */
397 #define QIBPORTCNTR_PKTSEND         0U
398 #define QIBPORTCNTR_WORDSEND        1U
399 #define QIBPORTCNTR_PSXMITDATA      2U
400 #define QIBPORTCNTR_PSXMITPKTS      3U
401 #define QIBPORTCNTR_PSXMITWAIT      4U
402 #define QIBPORTCNTR_SENDSTALL       5U
403 /* receive-related counters */
404 #define QIBPORTCNTR_PKTRCV          6U
405 #define QIBPORTCNTR_PSRCVDATA       7U
406 #define QIBPORTCNTR_PSRCVPKTS       8U
407 #define QIBPORTCNTR_RCVEBP          9U
408 #define QIBPORTCNTR_RCVOVFL         10U
409 #define QIBPORTCNTR_WORDRCV         11U
410 /* IB link related error counters */
411 #define QIBPORTCNTR_RXLOCALPHYERR   12U
412 #define QIBPORTCNTR_RXVLERR         13U
413 #define QIBPORTCNTR_ERRICRC         14U
414 #define QIBPORTCNTR_ERRVCRC         15U
415 #define QIBPORTCNTR_ERRLPCRC        16U
416 #define QIBPORTCNTR_BADFORMAT       17U
417 #define QIBPORTCNTR_ERR_RLEN        18U
418 #define QIBPORTCNTR_IBSYMBOLERR     19U
419 #define QIBPORTCNTR_INVALIDRLEN     20U
420 #define QIBPORTCNTR_UNSUPVL         21U
421 #define QIBPORTCNTR_EXCESSBUFOVFL   22U
422 #define QIBPORTCNTR_ERRLINK         23U
423 #define QIBPORTCNTR_IBLINKDOWN      24U
424 #define QIBPORTCNTR_IBLINKERRRECOV  25U
425 #define QIBPORTCNTR_LLI             26U
426 /* other error counters */
427 #define QIBPORTCNTR_RXDROPPKT       27U
428 #define QIBPORTCNTR_VL15PKTDROP     28U
429 #define QIBPORTCNTR_ERRPKEY         29U
430 #define QIBPORTCNTR_KHDROVFL        30U
431 /* sampling counters (these are actually control registers) */
432 #define QIBPORTCNTR_PSINTERVAL      31U
433 #define QIBPORTCNTR_PSSTART         32U
434 #define QIBPORTCNTR_PSSTAT          33U
435 
436 /* how often we check for packet activity for "power on hours (in seconds) */
437 #define ACTIVITY_TIMER 5
438 
439 #define MAX_NAME_SIZE 64
440 
441 #ifdef CONFIG_INFINIBAND_QIB_DCA
442 struct qib_irq_notify;
443 #endif
444 
445 struct qib_msix_entry {
446 	struct msix_entry msix;
447 	void *arg;
448 #ifdef CONFIG_INFINIBAND_QIB_DCA
449 	int dca;
450 	int rcv;
451 	struct qib_irq_notify *notifier;
452 #endif
453 	char name[MAX_NAME_SIZE];
454 	cpumask_var_t mask;
455 };
456 
457 /* Below is an opaque struct. Each chip (device) can maintain
458  * private data needed for its operation, but not germane to the
459  * rest of the driver.  For convenience, we define another that
460  * is chip-specific, per-port
461  */
462 struct qib_chip_specific;
463 struct qib_chipport_specific;
464 
465 enum qib_sdma_states {
466 	qib_sdma_state_s00_hw_down,
467 	qib_sdma_state_s10_hw_start_up_wait,
468 	qib_sdma_state_s20_idle,
469 	qib_sdma_state_s30_sw_clean_up_wait,
470 	qib_sdma_state_s40_hw_clean_up_wait,
471 	qib_sdma_state_s50_hw_halt_wait,
472 	qib_sdma_state_s99_running,
473 };
474 
475 enum qib_sdma_events {
476 	qib_sdma_event_e00_go_hw_down,
477 	qib_sdma_event_e10_go_hw_start,
478 	qib_sdma_event_e20_hw_started,
479 	qib_sdma_event_e30_go_running,
480 	qib_sdma_event_e40_sw_cleaned,
481 	qib_sdma_event_e50_hw_cleaned,
482 	qib_sdma_event_e60_hw_halted,
483 	qib_sdma_event_e70_go_idle,
484 	qib_sdma_event_e7220_err_halted,
485 	qib_sdma_event_e7322_err_halted,
486 	qib_sdma_event_e90_timer_tick,
487 };
488 
489 extern char *qib_sdma_state_names[];
490 extern char *qib_sdma_event_names[];
491 
492 struct sdma_set_state_action {
493 	unsigned op_enable:1;
494 	unsigned op_intenable:1;
495 	unsigned op_halt:1;
496 	unsigned op_drain:1;
497 	unsigned go_s99_running_tofalse:1;
498 	unsigned go_s99_running_totrue:1;
499 };
500 
501 struct qib_sdma_state {
502 	struct kref          kref;
503 	struct completion    comp;
504 	enum qib_sdma_states current_state;
505 	struct sdma_set_state_action *set_state_action;
506 	unsigned             current_op;
507 	unsigned             go_s99_running;
508 	unsigned             first_sendbuf;
509 	unsigned             last_sendbuf; /* really last +1 */
510 	/* debugging/devel */
511 	enum qib_sdma_states previous_state;
512 	unsigned             previous_op;
513 	enum qib_sdma_events last_event;
514 };
515 
516 struct xmit_wait {
517 	struct timer_list timer;
518 	u64 counter;
519 	u8 flags;
520 	struct cache {
521 		u64 psxmitdata;
522 		u64 psrcvdata;
523 		u64 psxmitpkts;
524 		u64 psrcvpkts;
525 		u64 psxmitwait;
526 	} counter_cache;
527 };
528 
529 /*
530  * The structure below encapsulates data relevant to a physical IB Port.
531  * Current chips support only one such port, but the separation
532  * clarifies things a bit. Note that to conform to IB conventions,
533  * port-numbers are one-based. The first or only port is port1.
534  */
535 struct qib_pportdata {
536 	struct qib_ibport ibport_data;
537 
538 	struct qib_devdata *dd;
539 	struct qib_chippport_specific *cpspec; /* chip-specific per-port */
540 	struct kobject pport_kobj;
541 	struct kobject pport_cc_kobj;
542 	struct kobject sl2vl_kobj;
543 	struct kobject diagc_kobj;
544 
545 	/* GUID for this interface, in network order */
546 	__be64 guid;
547 
548 	/* QIB_POLL, etc. link-state specific flags, per port */
549 	u32 lflags;
550 	/* qib_lflags driver is waiting for */
551 	u32 state_wanted;
552 	spinlock_t lflags_lock;
553 
554 	/* ref count for each pkey */
555 	atomic_t pkeyrefs[4];
556 
557 	/*
558 	 * this address is mapped readonly into user processes so they can
559 	 * get status cheaply, whenever they want.  One qword of status per port
560 	 */
561 	u64 *statusp;
562 
563 	/* SendDMA related entries */
564 
565 	/* read mostly */
566 	struct qib_sdma_desc *sdma_descq;
567 	struct workqueue_struct *qib_wq;
568 	struct qib_sdma_state sdma_state;
569 	dma_addr_t       sdma_descq_phys;
570 	volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
571 	dma_addr_t       sdma_head_phys;
572 	u16                   sdma_descq_cnt;
573 
574 	/* read/write using lock */
575 	spinlock_t            sdma_lock ____cacheline_aligned_in_smp;
576 	struct list_head      sdma_activelist;
577 	struct list_head      sdma_userpending;
578 	u64                   sdma_descq_added;
579 	u64                   sdma_descq_removed;
580 	u16                   sdma_descq_tail;
581 	u16                   sdma_descq_head;
582 	u8                    sdma_generation;
583 	u8                    sdma_intrequest;
584 
585 	struct tasklet_struct sdma_sw_clean_up_task
586 		____cacheline_aligned_in_smp;
587 
588 	wait_queue_head_t state_wait; /* for state_wanted */
589 
590 	/* HoL blocking for SMP replies */
591 	unsigned          hol_state;
592 	struct timer_list hol_timer;
593 
594 	/*
595 	 * Shadow copies of registers; size indicates read access size.
596 	 * Most of them are readonly, but some are write-only register,
597 	 * where we manipulate the bits in the shadow copy, and then write
598 	 * the shadow copy to qlogic_ib.
599 	 *
600 	 * We deliberately make most of these 32 bits, since they have
601 	 * restricted range.  For any that we read, we won't to generate 32
602 	 * bit accesses, since Opteron will generate 2 separate 32 bit HT
603 	 * transactions for a 64 bit read, and we want to avoid unnecessary
604 	 * bus transactions.
605 	 */
606 
607 	/* This is the 64 bit group */
608 	/* last ibcstatus.  opaque outside chip-specific code */
609 	u64 lastibcstat;
610 
611 	/* these are the "32 bit" regs */
612 
613 	/*
614 	 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
615 	 * all expect bit fields to be "unsigned long"
616 	 */
617 	unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
618 	unsigned long p_sendctrl; /* shadow per-port sendctrl */
619 
620 	u32 ibmtu; /* The MTU programmed for this unit */
621 	/*
622 	 * Current max size IB packet (in bytes) including IB headers, that
623 	 * we can send. Changes when ibmtu changes.
624 	 */
625 	u32 ibmaxlen;
626 	/*
627 	 * ibmaxlen at init time, limited by chip and by receive buffer
628 	 * size.  Not changed after init.
629 	 */
630 	u32 init_ibmaxlen;
631 	/* LID programmed for this instance */
632 	u16 lid;
633 	/* list of pkeys programmed; 0 if not set */
634 	u16 pkeys[4];
635 	/* LID mask control */
636 	u8 lmc;
637 	u8 link_width_supported;
638 	u8 link_speed_supported;
639 	u8 link_width_enabled;
640 	u8 link_speed_enabled;
641 	u8 link_width_active;
642 	u8 link_speed_active;
643 	u8 vls_supported;
644 	u8 vls_operational;
645 	/* Rx Polarity inversion (compensate for ~tx on partner) */
646 	u8 rx_pol_inv;
647 
648 	u8 hw_pidx;     /* physical port index */
649 	u8 port;        /* IB port number and index into dd->pports - 1 */
650 
651 	u8 delay_mult;
652 
653 	/* used to override LED behavior */
654 	u8 led_override;  /* Substituted for normal value, if non-zero */
655 	u16 led_override_timeoff; /* delta to next timer event */
656 	u8 led_override_vals[2]; /* Alternates per blink-frame */
657 	u8 led_override_phase; /* Just counts, LSB picks from vals[] */
658 	atomic_t led_override_timer_active;
659 	/* Used to flash LEDs in override mode */
660 	struct timer_list led_override_timer;
661 	struct xmit_wait cong_stats;
662 	struct timer_list symerr_clear_timer;
663 
664 	/* Synchronize access between driver writes and sysfs reads */
665 	spinlock_t cc_shadow_lock
666 		____cacheline_aligned_in_smp;
667 
668 	/* Shadow copy of the congestion control table */
669 	struct cc_table_shadow *ccti_entries_shadow;
670 
671 	/* Shadow copy of the congestion control entries */
672 	struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;
673 
674 	/* List of congestion control table entries */
675 	struct ib_cc_table_entry_shadow *ccti_entries;
676 
677 	/* 16 congestion entries with each entry corresponding to a SL */
678 	struct ib_cc_congestion_entry_shadow *congestion_entries;
679 
680 	/* Maximum number of congestion control entries that the agent expects
681 	 * the manager to send.
682 	 */
683 	u16 cc_supported_table_entries;
684 
685 	/* Total number of congestion control table entries */
686 	u16 total_cct_entry;
687 
688 	/* Bit map identifying service level */
689 	u16 cc_sl_control_map;
690 
691 	/* maximum congestion control table index */
692 	u16 ccti_limit;
693 
694 	/* CA's max number of 64 entry units in the congestion control table */
695 	u8 cc_max_table_entries;
696 };
697 
698 /* Observers. Not to be taken lightly, possibly not to ship. */
699 /*
700  * If a diag read or write is to (bottom <= offset <= top),
701  * the "hoook" is called, allowing, e.g. shadows to be
702  * updated in sync with the driver. struct diag_observer
703  * is the "visible" part.
704  */
705 struct diag_observer;
706 
707 typedef int (*diag_hook) (struct qib_devdata *dd,
708 	const struct diag_observer *op,
709 	u32 offs, u64 *data, u64 mask, int only_32);
710 
711 struct diag_observer {
712 	diag_hook hook;
713 	u32 bottom;
714 	u32 top;
715 };
716 
717 extern int qib_register_observer(struct qib_devdata *dd,
718 	const struct diag_observer *op);
719 
720 /* Only declared here, not defined. Private to diags */
721 struct diag_observer_list_elt;
722 
723 /* device data struct now contains only "general per-device" info.
724  * fields related to a physical IB port are in a qib_pportdata struct,
725  * described above) while fields only used by a particular chip-type are in
726  * a qib_chipdata struct, whose contents are opaque to this file.
727  */
728 struct qib_devdata {
729 	struct qib_ibdev verbs_dev;     /* must be first */
730 	struct list_head list;
731 	/* pointers to related structs for this device */
732 	/* pci access data structure */
733 	struct pci_dev *pcidev;
734 	struct cdev *user_cdev;
735 	struct cdev *diag_cdev;
736 	struct device *user_device;
737 	struct device *diag_device;
738 
739 	/* mem-mapped pointer to base of chip regs */
740 	u64 __iomem *kregbase;
741 	/* end of mem-mapped chip space excluding sendbuf and user regs */
742 	u64 __iomem *kregend;
743 	/* physical address of chip for io_remap, etc. */
744 	resource_size_t physaddr;
745 	/* qib_cfgctxts pointers */
746 	struct qib_ctxtdata **rcd; /* Receive Context Data */
747 
748 	/* qib_pportdata, points to array of (physical) port-specific
749 	 * data structs, indexed by pidx (0..n-1)
750 	 */
751 	struct qib_pportdata *pport;
752 	struct qib_chip_specific *cspec; /* chip-specific */
753 
754 	/* kvirt address of 1st 2k pio buffer */
755 	void __iomem *pio2kbase;
756 	/* kvirt address of 1st 4k pio buffer */
757 	void __iomem *pio4kbase;
758 	/* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
759 	void __iomem *piobase;
760 	/* mem-mapped pointer to base of user chip regs (if using WC PAT) */
761 	u64 __iomem *userbase;
762 	void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
763 	/*
764 	 * points to area where PIOavail registers will be DMA'ed.
765 	 * Has to be on a page of it's own, because the page will be
766 	 * mapped into user program space.  This copy is *ONLY* ever
767 	 * written by DMA, not by the driver!  Need a copy per device
768 	 * when we get to multiple devices
769 	 */
770 	volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
771 	/* physical address where updates occur */
772 	dma_addr_t pioavailregs_phys;
773 
774 	/* device-specific implementations of functions needed by
775 	 * common code. Contrary to previous consensus, we can't
776 	 * really just point to a device-specific table, because we
777 	 * may need to "bend", e.g. *_f_put_tid
778 	 */
779 	/* fallback to alternate interrupt type if possible */
780 	int (*f_intr_fallback)(struct qib_devdata *);
781 	/* hard reset chip */
782 	int (*f_reset)(struct qib_devdata *);
783 	void (*f_quiet_serdes)(struct qib_pportdata *);
784 	int (*f_bringup_serdes)(struct qib_pportdata *);
785 	int (*f_early_init)(struct qib_devdata *);
786 	void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
787 	void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
788 				u32, unsigned long);
789 	void (*f_cleanup)(struct qib_devdata *);
790 	void (*f_setextled)(struct qib_pportdata *, u32);
791 	/* fill out chip-specific fields */
792 	int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
793 	/* free irq */
794 	void (*f_free_irq)(struct qib_devdata *);
795 	struct qib_message_header *(*f_get_msgheader)
796 					(struct qib_devdata *, __le32 *);
797 	void (*f_config_ctxts)(struct qib_devdata *);
798 	int (*f_get_ib_cfg)(struct qib_pportdata *, int);
799 	int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
800 	int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
801 	int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
802 	int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
803 	u32 (*f_iblink_state)(u64);
804 	u8 (*f_ibphys_portstate)(u64);
805 	void (*f_xgxs_reset)(struct qib_pportdata *);
806 	/* per chip actions needed for IB Link up/down changes */
807 	int (*f_ib_updown)(struct qib_pportdata *, int, u64);
808 	u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
809 	/* Read/modify/write of GPIO pins (potentially chip-specific */
810 	int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
811 		u32 mask);
812 	/* Enable writes to config EEPROM (if supported) */
813 	int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
814 	/*
815 	 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
816 	 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
817 	 * (ctxt == -1) means "all contexts", only meaningful for
818 	 * clearing. Could remove if chip_spec shutdown properly done.
819 	 */
820 	void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
821 		int ctxt);
822 	/* Read/modify/write sendctrl appropriately for op and port. */
823 	void (*f_sendctrl)(struct qib_pportdata *, u32 op);
824 	void (*f_set_intr_state)(struct qib_devdata *, u32);
825 	void (*f_set_armlaunch)(struct qib_devdata *, u32);
826 	void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
827 	int (*f_late_initreg)(struct qib_devdata *);
828 	int (*f_init_sdma_regs)(struct qib_pportdata *);
829 	u16 (*f_sdma_gethead)(struct qib_pportdata *);
830 	int (*f_sdma_busy)(struct qib_pportdata *);
831 	void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
832 	void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
833 	void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
834 	void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
835 	void (*f_sdma_hw_start_up)(struct qib_pportdata *);
836 	void (*f_sdma_init_early)(struct qib_pportdata *);
837 	void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
838 	void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
839 	u32 (*f_hdrqempty)(struct qib_ctxtdata *);
840 	u64 (*f_portcntr)(struct qib_pportdata *, u32);
841 	u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
842 		u64 **);
843 	u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
844 		char **, u64 **);
845 	u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
846 	void (*f_initvl15_bufs)(struct qib_devdata *);
847 	void (*f_init_ctxt)(struct qib_ctxtdata *);
848 	void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
849 		struct qib_ctxtdata *);
850 	void (*f_writescratch)(struct qib_devdata *, u32);
851 	int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
852 #ifdef CONFIG_INFINIBAND_QIB_DCA
853 	int (*f_notify_dca)(struct qib_devdata *, unsigned long event);
854 #endif
855 
856 	char *boardname; /* human readable board info */
857 
858 	/* template for writing TIDs  */
859 	u64 tidtemplate;
860 	/* value to write to free TIDs */
861 	u64 tidinvalid;
862 
863 	/* number of registers used for pioavail */
864 	u32 pioavregs;
865 	/* device (not port) flags, basically device capabilities */
866 	u32 flags;
867 	/* last buffer for user use */
868 	u32 lastctxt_piobuf;
869 
870 	/* reset value */
871 	u64 z_int_counter;
872 	/* percpu intcounter */
873 	u64 __percpu *int_counter;
874 
875 	/* pio bufs allocated per ctxt */
876 	u32 pbufsctxt;
877 	/* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
878 	u32 ctxts_extrabuf;
879 	/*
880 	 * number of ctxts configured as max; zero is set to number chip
881 	 * supports, less gives more pio bufs/ctxt, etc.
882 	 */
883 	u32 cfgctxts;
884 	/*
885 	 * number of ctxts available for PSM open
886 	 */
887 	u32 freectxts;
888 
889 	/*
890 	 * hint that we should update pioavailshadow before
891 	 * looking for a PIO buffer
892 	 */
893 	u32 upd_pio_shadow;
894 
895 	/* internal debugging stats */
896 	u32 maxpkts_call;
897 	u32 avgpkts_call;
898 	u64 nopiobufs;
899 
900 	/* PCI Vendor ID (here for NodeInfo) */
901 	u16 vendorid;
902 	/* PCI Device ID (here for NodeInfo) */
903 	u16 deviceid;
904 	/* for write combining settings */
905 	int wc_cookie;
906 	unsigned long wc_base;
907 	unsigned long wc_len;
908 
909 	/* shadow copy of struct page *'s for exp tid pages */
910 	struct page **pageshadow;
911 	/* shadow copy of dma handles for exp tid pages */
912 	dma_addr_t *physshadow;
913 	u64 __iomem *egrtidbase;
914 	spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
915 	/* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
916 	spinlock_t uctxt_lock; /* rcd and user context changes */
917 	/*
918 	 * per unit status, see also portdata statusp
919 	 * mapped readonly into user processes so they can get unit and
920 	 * IB link status cheaply
921 	 */
922 	u64 *devstatusp;
923 	char *freezemsg; /* freeze msg if hw error put chip in freeze */
924 	u32 freezelen; /* max length of freezemsg */
925 	/* timer used to prevent stats overflow, error throttling, etc. */
926 	struct timer_list stats_timer;
927 
928 	/* timer to verify interrupts work, and fallback if possible */
929 	struct timer_list intrchk_timer;
930 	unsigned long ureg_align; /* user register alignment */
931 
932 	/*
933 	 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
934 	 * pio_writing.
935 	 */
936 	spinlock_t pioavail_lock;
937 	/*
938 	 * index of last buffer to optimize search for next
939 	 */
940 	u32 last_pio;
941 	/*
942 	 * min kernel pio buffer to optimize search
943 	 */
944 	u32 min_kernel_pio;
945 	/*
946 	 * Shadow copies of registers; size indicates read access size.
947 	 * Most of them are readonly, but some are write-only register,
948 	 * where we manipulate the bits in the shadow copy, and then write
949 	 * the shadow copy to qlogic_ib.
950 	 *
951 	 * We deliberately make most of these 32 bits, since they have
952 	 * restricted range.  For any that we read, we won't to generate 32
953 	 * bit accesses, since Opteron will generate 2 separate 32 bit HT
954 	 * transactions for a 64 bit read, and we want to avoid unnecessary
955 	 * bus transactions.
956 	 */
957 
958 	/* This is the 64 bit group */
959 
960 	unsigned long pioavailshadow[6];
961 	/* bitmap of send buffers available for the kernel to use with PIO. */
962 	unsigned long pioavailkernel[6];
963 	/* bitmap of send buffers which need to be disarmed. */
964 	unsigned long pio_need_disarm[3];
965 	/* bitmap of send buffers which are being written to. */
966 	unsigned long pio_writing[3];
967 	/* kr_revision shadow */
968 	u64 revision;
969 	/* Base GUID for device (from eeprom, network order) */
970 	__be64 base_guid;
971 
972 	/*
973 	 * kr_sendpiobufbase value (chip offset of pio buffers), and the
974 	 * base of the 2KB buffer s(user processes only use 2K)
975 	 */
976 	u64 piobufbase;
977 	u32 pio2k_bufbase;
978 
979 	/* these are the "32 bit" regs */
980 
981 	/* number of GUIDs in the flash for this interface */
982 	u32 nguid;
983 	/*
984 	 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
985 	 * all expect bit fields to be "unsigned long"
986 	 */
987 	unsigned long rcvctrl; /* shadow per device rcvctrl */
988 	unsigned long sendctrl; /* shadow per device sendctrl */
989 
990 	/* value we put in kr_rcvhdrcnt */
991 	u32 rcvhdrcnt;
992 	/* value we put in kr_rcvhdrsize */
993 	u32 rcvhdrsize;
994 	/* value we put in kr_rcvhdrentsize */
995 	u32 rcvhdrentsize;
996 	/* kr_ctxtcnt value */
997 	u32 ctxtcnt;
998 	/* kr_pagealign value */
999 	u32 palign;
1000 	/* number of "2KB" PIO buffers */
1001 	u32 piobcnt2k;
1002 	/* size in bytes of "2KB" PIO buffers */
1003 	u32 piosize2k;
1004 	/* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
1005 	u32 piosize2kmax_dwords;
1006 	/* number of "4KB" PIO buffers */
1007 	u32 piobcnt4k;
1008 	/* size in bytes of "4KB" PIO buffers */
1009 	u32 piosize4k;
1010 	/* kr_rcvegrbase value */
1011 	u32 rcvegrbase;
1012 	/* kr_rcvtidbase value */
1013 	u32 rcvtidbase;
1014 	/* kr_rcvtidcnt value */
1015 	u32 rcvtidcnt;
1016 	/* kr_userregbase */
1017 	u32 uregbase;
1018 	/* shadow the control register contents */
1019 	u32 control;
1020 
1021 	/* chip address space used by 4k pio buffers */
1022 	u32 align4k;
1023 	/* size of each rcvegrbuffer */
1024 	u16 rcvegrbufsize;
1025 	/* log2 of above */
1026 	u16 rcvegrbufsize_shift;
1027 	/* localbus width (1, 2,4,8,16,32) from config space  */
1028 	u32 lbus_width;
1029 	/* localbus speed in MHz */
1030 	u32 lbus_speed;
1031 	int unit; /* unit # of this chip */
1032 
1033 	/* start of CHIP_SPEC move to chipspec, but need code changes */
1034 	/* low and high portions of MSI capability/vector */
1035 	u32 msi_lo;
1036 	/* saved after PCIe init for restore after reset */
1037 	u32 msi_hi;
1038 	/* MSI data (vector) saved for restore */
1039 	u16 msi_data;
1040 	/* so we can rewrite it after a chip reset */
1041 	u32 pcibar0;
1042 	/* so we can rewrite it after a chip reset */
1043 	u32 pcibar1;
1044 	u64 rhdrhead_intr_off;
1045 
1046 	/*
1047 	 * ASCII serial number, from flash, large enough for original
1048 	 * all digit strings, and longer QLogic serial number format
1049 	 */
1050 	u8 serial[16];
1051 	/* human readable board version */
1052 	u8 boardversion[96];
1053 	u8 lbus_info[32]; /* human readable localbus info */
1054 	/* chip major rev, from qib_revision */
1055 	u8 majrev;
1056 	/* chip minor rev, from qib_revision */
1057 	u8 minrev;
1058 
1059 	/* Misc small ints */
1060 	/* Number of physical ports available */
1061 	u8 num_pports;
1062 	/* Lowest context number which can be used by user processes */
1063 	u8 first_user_ctxt;
1064 	u8 n_krcv_queues;
1065 	u8 qpn_mask;
1066 	u8 skip_kctxt_mask;
1067 
1068 	u16 rhf_offset; /* offset of RHF within receive header entry */
1069 
1070 	/*
1071 	 * GPIO pins for twsi-connected devices, and device code for eeprom
1072 	 */
1073 	u8 gpio_sda_num;
1074 	u8 gpio_scl_num;
1075 	u8 twsi_eeprom_dev;
1076 	u8 board_atten;
1077 
1078 	/* Support (including locks) for EEPROM logging of errors and time */
1079 	/* control access to actual counters, timer */
1080 	spinlock_t eep_st_lock;
1081 	/* control high-level access to EEPROM */
1082 	struct mutex eep_lock;
1083 	uint64_t traffic_wds;
1084 	/*
1085 	 * masks for which bits of errs, hwerrs that cause
1086 	 * each of the counters to increment.
1087 	 */
1088 	struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1089 	struct qib_diag_client *diag_client;
1090 	spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1091 	struct diag_observer_list_elt *diag_observer_list;
1092 
1093 	u8 psxmitwait_supported;
1094 	/* cycle length of PS* counters in HW (in picoseconds) */
1095 	u16 psxmitwait_check_rate;
1096 	/* high volume overflow errors defered to tasklet */
1097 	struct tasklet_struct error_tasklet;
1098 
1099 	int assigned_node_id; /* NUMA node closest to HCA */
1100 };
1101 
1102 /* hol_state values */
1103 #define QIB_HOL_UP       0
1104 #define QIB_HOL_INIT     1
1105 
1106 #define QIB_SDMA_SENDCTRL_OP_ENABLE    (1U << 0)
1107 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1108 #define QIB_SDMA_SENDCTRL_OP_HALT      (1U << 2)
1109 #define QIB_SDMA_SENDCTRL_OP_CLEANUP   (1U << 3)
1110 #define QIB_SDMA_SENDCTRL_OP_DRAIN     (1U << 4)
1111 
1112 /* operation types for f_txchk_change() */
1113 #define TXCHK_CHG_TYPE_DIS1  3
1114 #define TXCHK_CHG_TYPE_ENAB1 2
1115 #define TXCHK_CHG_TYPE_KERN  1
1116 #define TXCHK_CHG_TYPE_USER  0
1117 
1118 #define QIB_CHASE_TIME msecs_to_jiffies(145)
1119 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1120 
1121 /* Private data for file operations */
1122 struct qib_filedata {
1123 	struct qib_ctxtdata *rcd;
1124 	unsigned subctxt;
1125 	unsigned tidcursor;
1126 	struct qib_user_sdma_queue *pq;
1127 	int rec_cpu_num; /* for cpu affinity; -1 if none */
1128 };
1129 
1130 extern struct list_head qib_dev_list;
1131 extern spinlock_t qib_devs_lock;
1132 extern struct qib_devdata *qib_lookup(int unit);
1133 extern u32 qib_cpulist_count;
1134 extern unsigned long *qib_cpulist;
1135 extern unsigned qib_cc_table_size;
1136 
1137 int qib_init(struct qib_devdata *, int);
1138 int init_chip_wc_pat(struct qib_devdata *dd, u32);
1139 int qib_enable_wc(struct qib_devdata *dd);
1140 void qib_disable_wc(struct qib_devdata *dd);
1141 int qib_count_units(int *npresentp, int *nupp);
1142 int qib_count_active_units(void);
1143 
1144 int qib_cdev_init(int minor, const char *name,
1145 		  const struct file_operations *fops,
1146 		  struct cdev **cdevp, struct device **devp);
1147 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1148 int qib_dev_init(void);
1149 void qib_dev_cleanup(void);
1150 
1151 int qib_diag_add(struct qib_devdata *);
1152 void qib_diag_remove(struct qib_devdata *);
1153 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1154 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1155 
1156 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1157 void qib_bad_intrstatus(struct qib_devdata *);
1158 void qib_handle_urcv(struct qib_devdata *, u64);
1159 
1160 /* clean up any per-chip chip-specific stuff */
1161 void qib_chip_cleanup(struct qib_devdata *);
1162 /* clean up any chip type-specific stuff */
1163 void qib_chip_done(void);
1164 
1165 /* check to see if we have to force ordering for write combining */
1166 int qib_unordered_wc(void);
1167 void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1168 
1169 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1170 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1171 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1172 void qib_cancel_sends(struct qib_pportdata *);
1173 
1174 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1175 int qib_setup_eagerbufs(struct qib_ctxtdata *);
1176 void qib_set_ctxtcnt(struct qib_devdata *);
1177 int qib_create_ctxts(struct qib_devdata *dd);
1178 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int);
1179 int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1180 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1181 
1182 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1183 int qib_reset_device(int);
1184 int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1185 int qib_set_linkstate(struct qib_pportdata *, u8);
1186 int qib_set_mtu(struct qib_pportdata *, u16);
1187 int qib_set_lid(struct qib_pportdata *, u32, u8);
1188 void qib_hol_down(struct qib_pportdata *);
1189 void qib_hol_init(struct qib_pportdata *);
1190 void qib_hol_up(struct qib_pportdata *);
1191 void qib_hol_event(unsigned long);
1192 void qib_disable_after_error(struct qib_devdata *);
1193 int qib_set_uevent_bits(struct qib_pportdata *, const int);
1194 
1195 /* for use in system calls, where we want to know device type, etc. */
1196 #define ctxt_fp(fp) \
1197 	(((struct qib_filedata *)(fp)->private_data)->rcd)
1198 #define subctxt_fp(fp) \
1199 	(((struct qib_filedata *)(fp)->private_data)->subctxt)
1200 #define tidcursor_fp(fp) \
1201 	(((struct qib_filedata *)(fp)->private_data)->tidcursor)
1202 #define user_sdma_queue_fp(fp) \
1203 	(((struct qib_filedata *)(fp)->private_data)->pq)
1204 
dd_from_ppd(struct qib_pportdata * ppd)1205 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1206 {
1207 	return ppd->dd;
1208 }
1209 
dd_from_dev(struct qib_ibdev * dev)1210 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1211 {
1212 	return container_of(dev, struct qib_devdata, verbs_dev);
1213 }
1214 
dd_from_ibdev(struct ib_device * ibdev)1215 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1216 {
1217 	return dd_from_dev(to_idev(ibdev));
1218 }
1219 
ppd_from_ibp(struct qib_ibport * ibp)1220 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1221 {
1222 	return container_of(ibp, struct qib_pportdata, ibport_data);
1223 }
1224 
to_iport(struct ib_device * ibdev,u8 port)1225 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1226 {
1227 	struct qib_devdata *dd = dd_from_ibdev(ibdev);
1228 	unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1229 
1230 	WARN_ON(pidx >= dd->num_pports);
1231 	return &dd->pport[pidx].ibport_data;
1232 }
1233 
1234 /*
1235  * values for dd->flags (_device_ related flags) and
1236  */
1237 #define QIB_HAS_LINK_LATENCY  0x1 /* supports link latency (IB 1.2) */
1238 #define QIB_INITTED           0x2 /* chip and driver up and initted */
1239 #define QIB_DOING_RESET       0x4  /* in the middle of doing chip reset */
1240 #define QIB_PRESENT           0x8  /* chip accesses can be done */
1241 #define QIB_PIO_FLUSH_WC      0x10 /* Needs Write combining flush for PIO */
1242 #define QIB_HAS_THRESH_UPDATE 0x40
1243 #define QIB_HAS_SDMA_TIMEOUT  0x80
1244 #define QIB_USE_SPCL_TRIG     0x100 /* SpecialTrigger launch enabled */
1245 #define QIB_NODMA_RTAIL       0x200 /* rcvhdrtail register DMA enabled */
1246 #define QIB_HAS_INTX          0x800 /* Supports INTx interrupts */
1247 #define QIB_HAS_SEND_DMA      0x1000 /* Supports Send DMA */
1248 #define QIB_HAS_VLSUPP        0x2000 /* Supports multiple VLs; PBC different */
1249 #define QIB_HAS_HDRSUPP       0x4000 /* Supports header suppression */
1250 #define QIB_BADINTR           0x8000 /* severe interrupt problems */
1251 #define QIB_DCA_ENABLED       0x10000 /* Direct Cache Access enabled */
1252 #define QIB_HAS_QSFP          0x20000 /* device (card instance) has QSFP */
1253 
1254 /*
1255  * values for ppd->lflags (_ib_port_ related flags)
1256  */
1257 #define QIBL_LINKV             0x1 /* IB link state valid */
1258 #define QIBL_LINKDOWN          0x8 /* IB link is down */
1259 #define QIBL_LINKINIT          0x10 /* IB link level is up */
1260 #define QIBL_LINKARMED         0x20 /* IB link is ARMED */
1261 #define QIBL_LINKACTIVE        0x40 /* IB link is ACTIVE */
1262 /* leave a gap for more IB-link state */
1263 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1264 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1265 #define QIBL_IB_LINK_DISABLED  0x4000 /* Linkdown-disable forced,
1266 				       * Do not try to bring up */
1267 #define QIBL_IB_FORCE_NOTIFY   0x8000 /* force notify on next ib change */
1268 
1269 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1270 #define QIB_PBC_LENGTH_MASK                     ((1 << 11) - 1)
1271 
1272 
1273 /* ctxt_flag bit offsets */
1274 		/* waiting for a packet to arrive */
1275 #define QIB_CTXT_WAITING_RCV   2
1276 		/* master has not finished initializing */
1277 #define QIB_CTXT_MASTER_UNINIT 4
1278 		/* waiting for an urgent packet to arrive */
1279 #define QIB_CTXT_WAITING_URG 5
1280 
1281 /* free up any allocated data at closes */
1282 void qib_free_data(struct qib_ctxtdata *dd);
1283 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1284 			    u32, struct qib_ctxtdata *);
1285 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1286 					   const struct pci_device_id *);
1287 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1288 					   const struct pci_device_id *);
1289 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1290 					   const struct pci_device_id *);
1291 void qib_free_devdata(struct qib_devdata *);
1292 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1293 
1294 #define QIB_TWSI_NO_DEV 0xFF
1295 /* Below qib_twsi_ functions must be called with eep_lock held */
1296 int qib_twsi_reset(struct qib_devdata *dd);
1297 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1298 		    int len);
1299 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1300 		    const void *buffer, int len);
1301 void qib_get_eeprom_info(struct qib_devdata *);
1302 #define qib_inc_eeprom_err(dd, eidx, incr)
1303 void qib_dump_lookup_output_queue(struct qib_devdata *);
1304 void qib_force_pio_avail_update(struct qib_devdata *);
1305 void qib_clear_symerror_on_linkup(unsigned long opaque);
1306 
1307 /*
1308  * Set LED override, only the two LSBs have "public" meaning, but
1309  * any non-zero value substitutes them for the Link and LinkTrain
1310  * LED states.
1311  */
1312 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1313 #define QIB_LED_LOG 2  /* Logical (link) YELLOW LED */
1314 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1315 
1316 /* send dma routines */
1317 int qib_setup_sdma(struct qib_pportdata *);
1318 void qib_teardown_sdma(struct qib_pportdata *);
1319 void __qib_sdma_intr(struct qib_pportdata *);
1320 void qib_sdma_intr(struct qib_pportdata *);
1321 void qib_user_sdma_send_desc(struct qib_pportdata *dd,
1322 			struct list_head *pktlist);
1323 int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *,
1324 			u32, struct qib_verbs_txreq *);
1325 /* ppd->sdma_lock should be locked before calling this. */
1326 int qib_sdma_make_progress(struct qib_pportdata *dd);
1327 
qib_sdma_empty(const struct qib_pportdata * ppd)1328 static inline int qib_sdma_empty(const struct qib_pportdata *ppd)
1329 {
1330 	return ppd->sdma_descq_added == ppd->sdma_descq_removed;
1331 }
1332 
1333 /* must be called under qib_sdma_lock */
qib_sdma_descq_freecnt(const struct qib_pportdata * ppd)1334 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1335 {
1336 	return ppd->sdma_descq_cnt -
1337 		(ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1338 }
1339 
__qib_sdma_running(struct qib_pportdata * ppd)1340 static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1341 {
1342 	return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1343 }
1344 int qib_sdma_running(struct qib_pportdata *);
1345 void dump_sdma_state(struct qib_pportdata *ppd);
1346 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1347 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1348 
1349 /*
1350  * number of words used for protocol header if not set by qib_userinit();
1351  */
1352 #define QIB_DFLT_RCVHDRSIZE 9
1353 
1354 /*
1355  * We need to be able to handle an IB header of at least 24 dwords.
1356  * We need the rcvhdrq large enough to handle largest IB header, but
1357  * still have room for a 2KB MTU standard IB packet.
1358  * Additionally, some processor/memory controller combinations
1359  * benefit quite strongly from having the DMA'ed data be cacheline
1360  * aligned and a cacheline multiple, so we set the size to 32 dwords
1361  * (2 64-byte primary cachelines for pretty much all processors of
1362  * interest).  The alignment hurts nothing, other than using somewhat
1363  * more memory.
1364  */
1365 #define QIB_RCVHDR_ENTSIZE 32
1366 
1367 int qib_get_user_pages(unsigned long, size_t, struct page **);
1368 void qib_release_user_pages(struct page **, size_t);
1369 int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1370 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1371 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1372 void qib_sendbuf_done(struct qib_devdata *, unsigned);
1373 
qib_clear_rcvhdrtail(const struct qib_ctxtdata * rcd)1374 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1375 {
1376 	*((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1377 }
1378 
qib_get_rcvhdrtail(const struct qib_ctxtdata * rcd)1379 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1380 {
1381 	/*
1382 	 * volatile because it's a DMA target from the chip, routine is
1383 	 * inlined, and don't want register caching or reordering.
1384 	 */
1385 	return (u32) le64_to_cpu(
1386 		*((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1387 }
1388 
qib_get_hdrqtail(const struct qib_ctxtdata * rcd)1389 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1390 {
1391 	const struct qib_devdata *dd = rcd->dd;
1392 	u32 hdrqtail;
1393 
1394 	if (dd->flags & QIB_NODMA_RTAIL) {
1395 		__le32 *rhf_addr;
1396 		u32 seq;
1397 
1398 		rhf_addr = (__le32 *) rcd->rcvhdrq +
1399 			rcd->head + dd->rhf_offset;
1400 		seq = qib_hdrget_seq(rhf_addr);
1401 		hdrqtail = rcd->head;
1402 		if (seq == rcd->seq_cnt)
1403 			hdrqtail++;
1404 	} else
1405 		hdrqtail = qib_get_rcvhdrtail(rcd);
1406 
1407 	return hdrqtail;
1408 }
1409 
1410 /*
1411  * sysfs interface.
1412  */
1413 
1414 extern const char ib_qib_version[];
1415 
1416 int qib_device_create(struct qib_devdata *);
1417 void qib_device_remove(struct qib_devdata *);
1418 
1419 int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1420 			  struct kobject *kobj);
1421 int qib_verbs_register_sysfs(struct qib_devdata *);
1422 void qib_verbs_unregister_sysfs(struct qib_devdata *);
1423 /* Hook for sysfs read of QSFP */
1424 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1425 
1426 int __init qib_init_qibfs(void);
1427 int __exit qib_exit_qibfs(void);
1428 
1429 int qibfs_add(struct qib_devdata *);
1430 int qibfs_remove(struct qib_devdata *);
1431 
1432 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1433 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1434 		    const struct pci_device_id *);
1435 void qib_pcie_ddcleanup(struct qib_devdata *);
1436 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *);
1437 int qib_reinit_intr(struct qib_devdata *);
1438 void qib_enable_intx(struct pci_dev *);
1439 void qib_nomsi(struct qib_devdata *);
1440 void qib_nomsix(struct qib_devdata *);
1441 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1442 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1443 /* interrupts for device */
1444 u64 qib_int_counter(struct qib_devdata *);
1445 /* interrupt for all devices */
1446 u64 qib_sps_ints(void);
1447 
1448 /*
1449  * dma_addr wrappers - all 0's invalid for hw
1450  */
1451 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1452 			  size_t, int);
1453 const char *qib_get_unit_name(int unit);
1454 const char *qib_get_card_name(struct rvt_dev_info *rdi);
1455 struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi);
1456 
1457 /*
1458  * Flush write combining store buffers (if present) and perform a write
1459  * barrier.
1460  */
qib_flush_wc(void)1461 static inline void qib_flush_wc(void)
1462 {
1463 #if defined(CONFIG_X86_64)
1464 	asm volatile("sfence" : : : "memory");
1465 #else
1466 	wmb(); /* no reorder around wc flush */
1467 #endif
1468 }
1469 
1470 /* global module parameter variables */
1471 extern unsigned qib_ibmtu;
1472 extern ushort qib_cfgctxts;
1473 extern ushort qib_num_cfg_vls;
1474 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1475 extern unsigned qib_n_krcv_queues;
1476 extern unsigned qib_sdma_fetch_arb;
1477 extern unsigned qib_compat_ddr_negotiate;
1478 extern int qib_special_trigger;
1479 extern unsigned qib_numa_aware;
1480 
1481 extern struct mutex qib_mutex;
1482 
1483 /* Number of seconds before our card status check...  */
1484 #define STATUS_TIMEOUT 60
1485 
1486 #define QIB_DRV_NAME            "ib_qib"
1487 #define QIB_USER_MINOR_BASE     0
1488 #define QIB_TRACE_MINOR         127
1489 #define QIB_DIAGPKT_MINOR       128
1490 #define QIB_DIAG_MINOR_BASE     129
1491 #define QIB_NMINORS             255
1492 
1493 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1494 #define PCI_VENDOR_ID_QLOGIC 0x1077
1495 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1496 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1497 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1498 
1499 /*
1500  * qib_early_err is used (only!) to print early errors before devdata is
1501  * allocated, or when dd->pcidev may not be valid, and at the tail end of
1502  * cleanup when devdata may have been freed, etc.  qib_dev_porterr is
1503  * the same as qib_dev_err, but is used when the message really needs
1504  * the IB port# to be definitive as to what's happening..
1505  * All of these go to the trace log, and the trace log entry is done
1506  * first to avoid possible serial port delays from printk.
1507  */
1508 #define qib_early_err(dev, fmt, ...) \
1509 	dev_err(dev, fmt, ##__VA_ARGS__)
1510 
1511 #define qib_dev_err(dd, fmt, ...) \
1512 	dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1513 		qib_get_unit_name((dd)->unit), ##__VA_ARGS__)
1514 
1515 #define qib_dev_warn(dd, fmt, ...) \
1516 	dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1517 		qib_get_unit_name((dd)->unit), ##__VA_ARGS__)
1518 
1519 #define qib_dev_porterr(dd, port, fmt, ...) \
1520 	dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1521 		qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1522 		##__VA_ARGS__)
1523 
1524 #define qib_devinfo(pcidev, fmt, ...) \
1525 	dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__)
1526 
1527 /*
1528  * this is used for formatting hw error messages...
1529  */
1530 struct qib_hwerror_msgs {
1531 	u64 mask;
1532 	const char *msg;
1533 	size_t sz;
1534 };
1535 
1536 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1537 
1538 /* in qib_intr.c... */
1539 void qib_format_hwerrors(u64 hwerrs,
1540 			 const struct qib_hwerror_msgs *hwerrmsgs,
1541 			 size_t nhwerrmsgs, char *msg, size_t lmsg);
1542 
1543 void qib_stop_send_queue(struct rvt_qp *qp);
1544 void qib_quiesce_qp(struct rvt_qp *qp);
1545 void qib_flush_qp_waiters(struct rvt_qp *qp);
1546 int qib_mtu_to_path_mtu(u32 mtu);
1547 u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu);
1548 void qib_notify_error_qp(struct rvt_qp *qp);
1549 int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
1550 			   struct ib_qp_attr *attr);
1551 
1552 #endif                          /* _QIB_KERNEL_H */
1553