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Searched refs:wr32 (Results 1 – 25 of 64) sorted by relevance

123

/drivers/net/ethernet/intel/igb/
Digb_ptp.c145 wr32(E1000_SYSTIML, ts->tv_nsec); in igb_ptp_write_i210()
146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec); in igb_ptp_write_i210()
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); in igb_ptp_adjfreq_82576()
250 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfreq_82580()
403 wr32(E1000_TSSDP, tssdp); in igb_pin_extts()
404 wr32(E1000_CTRL, ctrl); in igb_pin_extts()
405 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_extts()
469 wr32(E1000_TSSDP, tssdp); in igb_pin_perout()
470 wr32(E1000_CTRL, ctrl); in igb_pin_perout()
471 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pin_perout()
[all …]
De1000_82575.c222 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_init_phy_params_82575()
533 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); in igb_set_sfp_media_type_82575()
579 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_set_sfp_media_type_82575()
701 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_invariants_82575()
907 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
939 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
1095 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d0_lplu_state_82580()
1139 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d3_lplu_state_82580()
1223 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
1248 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
[all …]
De1000_mac.c262 wr32(E1000_VLVF(vlvf_index), 0); in igb_vfta_set()
285 wr32(E1000_VLVF(vlvf_index), bits | vlan | E1000_VLVF_VLANID_ENABLE); in igb_vfta_set()
396 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
398 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
704 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
705 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
706 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
708 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
734 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
768 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
[all …]
Digb_main.c603 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
628 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
902 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
919 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
927 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1158 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1489 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1490 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1492 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1495 wr32(E1000_IAM, 0); in igb_irq_disable()
[all …]
De1000_i210.c84 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); in igb_get_hw_semaphore_i210()
168 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
192 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
270 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
698 wr32(E1000_EECD, flup); in igb_update_flash_i210()
856 wr32(E1000_MDICNFG, reg_val); in igb_pll_workaround_i210()
877 wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST); in igb_pll_workaround_i210()
881 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_pll_workaround_i210()
883 wr32(E1000_WUC, 0); in igb_pll_workaround_i210()
885 wr32(E1000_EEARBC_I210, reg_val); in igb_pll_workaround_i210()
[all …]
De1000_nvm.c39 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
54 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
85 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
97 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
184 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
197 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
219 wr32(E1000_EECD, eecd); in igb_standby_nvm()
223 wr32(E1000_EECD, eecd); in igb_standby_nvm()
261 wr32(E1000_EECD, eecd); in igb_release_nvm()
282 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
De1000_mbx.c249 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
307 wr32(E1000_VFLRE, BIT(vf_number)); in igb_check_for_rst_pf()
329 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
372 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
409 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
Digb_ethtool.c1210 wr32(reg, (_test[pat] & write)); in reg_pattern_test()
1230 wr32(reg, write & mask); in reg_set_and_check()
1294 wr32(E1000_STATUS, toggle); in igb_reg_test()
1304 wr32(E1000_STATUS, before); in igb_reg_test()
1422 wr32(E1000_IMC, ~0); in igb_intr_test()
1466 wr32(E1000_ICR, ~0); in igb_intr_test()
1468 wr32(E1000_IMC, mask); in igb_intr_test()
1469 wr32(E1000_ICS, mask); in igb_intr_test()
1488 wr32(E1000_ICR, ~0); in igb_intr_test()
1490 wr32(E1000_IMS, mask); in igb_intr_test()
[all …]
/drivers/net/ethernet/intel/i40evf/
Di40e_adminq.c295 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
296 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
299 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
301 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
302 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
324 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
325 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
328 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
330 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
331 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
Di40e_hmc.h132 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
133 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
134 wr32((hw), I40E_PFHMC_SDCMD, val3); \
151 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
152 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
153 wr32((hw), I40E_PFHMC_SDCMD, val3); \
163 wr32((hw), I40E_PFHMC_PDINV, \
Di40evf_main.c210 wr32(hw, I40E_VFINT_DYN_CTL01, 0); in i40evf_misc_irq_disable()
226 wr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK | in i40evf_misc_irq_enable()
228 wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK); in i40evf_misc_irq_enable()
247 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), 0); in i40evf_irq_disable()
266 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), in i40evf_irq_enable_queues()
290 wr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl); in i40evf_fire_sw_int()
298 wr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl); in i40evf_fire_sw_int()
337 wr32(hw, I40E_VFINT_DYN_CTL01, val); in i40evf_msix_aq()
384 wr32(hw, I40E_VFINT_ITRN1(I40E_RX_ITR, v_idx - 1), q_vector->rx.itr); in i40evf_map_vector_to_rxq()
409 wr32(hw, I40E_VFINT_ITRN1(I40E_TX_ITR, v_idx - 1), q_vector->tx.itr); in i40evf_map_vector_to_txq()
[all …]
/drivers/net/ethernet/intel/i40e/
Di40e_adminq.c298 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
299 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
302 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
304 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
305 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
327 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
328 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
331 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
333 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
334 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
[all …]
Di40e_hmc.h132 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
133 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
134 wr32((hw), I40E_PFHMC_SDCMD, val3); \
151 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
152 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
153 wr32((hw), I40E_PFHMC_SDCMD, val3); \
163 wr32((hw), I40E_PFHMC_PDINV, \
Di40e_ptp.c91 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); in i40e_ptp_write()
92 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); in i40e_ptp_write()
144 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); in i40e_ptp_adjfreq()
145 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); in i40e_ptp_adjfreq()
416 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); in i40e_ptp_set_increment()
417 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); in i40e_ptp_set_increment()
530 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_set_timestamp_mode()
537 wr32(hw, I40E_PFINT_ICR0_ENA, regval); in i40e_ptp_set_timestamp_mode()
550 wr32(hw, I40E_PRTTSYN_CTL1, regval); in i40e_ptp_set_timestamp_mode()
683 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_init()
[all …]
Di40e_virtchnl_pf.c275 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
298 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
335 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
346 wr32(hw, I40E_GLINT_CTL, reg); in i40e_config_irq_link_list()
397 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg); in i40e_release_iwarp_qvlist()
458 wr32(hw, I40E_VPINT_CEQCTL(reg_idx), reg); in i40e_config_iwarp_qvlist()
465 wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg); in i40e_config_iwarp_qvlist()
473 wr32(hw, I40E_VPINT_AEQCTL(vf->vf_id), reg); in i40e_config_iwarp_qvlist()
554 wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl); in i40e_config_vsi_tx_queue()
746 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg); in i40e_enable_vf_mappings()
[all …]
Di40e_diag.c46 wr32(hw, reg, (pat & mask)); in i40e_diag_reg_pattern_test()
56 wr32(hw, reg, orig_val); in i40e_diag_reg_pattern_test()
Di40e_lan_hmc.c509 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
511 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
515 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id), in i40e_configure_lan_hmc()
517 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
521 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id), in i40e_configure_lan_hmc()
523 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
527 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id), in i40e_configure_lan_hmc()
529 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt); in i40e_configure_lan_hmc()
Di40e_main.c2893 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); in i40e_configure_tx_ring()
3155 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), in i40e_vsi_configure_msix()
3159 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), in i40e_vsi_configure_msix()
3161 wr32(hw, I40E_PFINT_RATEN(vector - 1), in i40e_vsi_configure_msix()
3165 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); in i40e_vsi_configure_msix()
3176 wr32(hw, I40E_QINT_RQCTL(qp), val); in i40e_vsi_configure_msix()
3190 wr32(hw, I40E_QINT_TQCTL(qp), val); in i40e_vsi_configure_msix()
3208 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ in i40e_enable_misc_int_causes()
3226 wr32(hw, I40E_PFINT_ICR0_ENA, val); in i40e_enable_misc_int_causes()
3229 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | in i40e_enable_misc_int_causes()
[all …]
/drivers/net/fjes/
Dfjes_hw.c75 wr32(XSCT_DCTL, dctl.reg); in fjes_hw_reset()
191 wr32(XSCT_REQBL, (__le32)(param->req_len)); in fjes_hw_init_command_registers()
193 wr32(XSCT_RESPBL, (__le32)(param->res_len)); in fjes_hw_init_command_registers()
196 wr32(XSCT_REQBAL, in fjes_hw_init_command_registers()
198 wr32(XSCT_REQBAH, in fjes_hw_init_command_registers()
202 wr32(XSCT_RESPBAL, in fjes_hw_init_command_registers()
204 wr32(XSCT_RESPBAH, in fjes_hw_init_command_registers()
208 wr32(XSCT_SHSTSAL, in fjes_hw_init_command_registers()
210 wr32(XSCT_SHSTSAH, in fjes_hw_init_command_registers()
379 wr32(XSCT_CR, cr.reg); in fjes_hw_issue_request_command()
[all …]
/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c69 .wr32 = nvkm_gpuobj_wr32_fast,
76 .wr32 = nvkm_gpuobj_heap_wr32,
120 .wr32 = nvkm_gpuobj_wr32_fast,
127 .wr32 = nvkm_gpuobj_wr32,
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dmemory.h27 void (*wr32)(struct nvkm_memory *, u64 offset, u32 data); member
46 #define nvkm_wo32(o,a,d) (o)->func->wr32((o), (a), (d))
/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dbase.c116 .wr32 = nvkm_instobj_wr32,
169 .wr32 = nvkm_instobj_wr32_slow,
232 return imem->func->wr32(imem, addr, data); in nvkm_instmem_wr32()
Dnv04.c112 .wr32 = nv04_instobj_wr32,
210 .wr32 = nv04_instmem_wr32,
/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dbase.c46 pci->func->wr32(pci, addr, data); in nvkm_pci_wr32()
53 pci->func->wr32(pci, addr, (data & ~mask) | value); in nvkm_pci_mask()
Dnv4c.c30 .wr32 = nv40_pci_wr32,

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