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Searched refs:writel (Results 1 – 25 of 1393) sorted by relevance

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/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
50 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
64 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
75 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
82 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
83 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); in analogix_dp_init_analog_param()
84 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); in analogix_dp_init_analog_param()
85 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); in analogix_dp_init_analog_param()
[all …]
/drivers/video/fbdev/via/
Daccel.c48 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
105 writel(tmp, engine + 0x08); in hw_bitblt_1()
114 writel(tmp, engine + 0x0C); in hw_bitblt_1()
122 writel(tmp, engine + 0x10); in hw_bitblt_1()
125 writel(fg_color, engine + 0x18); in hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
138 writel(tmp, engine + 0x30); in hw_bitblt_1()
147 writel(tmp, engine + 0x34); in hw_bitblt_1()
159 writel(tmp, engine + 0x38); in hw_bitblt_1()
172 writel(ge_cmd, engine); in hw_bitblt_1()
[all …]
/drivers/net/ethernet/chelsio/cxgb/
Despi.c65 writel(V_WRITE_DATA(wr_data) | in tricn_write()
71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
111 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init()
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
[all …]
Dtp.c31 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init()
32 writel(F_TP_OUT_CSPI_CPL | in tp_init()
36 writel(V_IP_TTL(64) | in tp_init()
46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init()
77 writel(0xffffffff, in t1_tp_intr_enable()
79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable()
85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
86 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable()
98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable()
99 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable()
[all …]
/drivers/video/fbdev/
Dwmt_ge_rops.c67 writel(p->var.bits_per_pixel == 32 ? 3 : in wmt_ge_fillrect()
69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect()
70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect()
71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect()
72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect()
73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect()
74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect()
75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect()
76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect()
78 writel(pat, regbase + GE_PAT0C_OFF); in wmt_ge_fillrect()
[all …]
Dw100fb.c133 writel(param, remapped_regs + regs); in w100fb_reg_write()
297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); in w100_init_graphic_engine()
298 writel(par->xres, remapped_regs + mmDST_PITCH); in w100_init_graphic_engine()
299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); in w100_init_graphic_engine()
300 writel(par->xres, remapped_regs + mmSRC_PITCH); in w100_init_graphic_engine()
303 writel(0, remapped_regs + mmSC_TOP_LEFT); in w100_init_graphic_engine()
304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); in w100_init_graphic_engine()
305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); in w100_init_graphic_engine()
315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); in w100_init_graphic_engine()
332 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); in w100_init_graphic_engine()
[all …]
/drivers/clocksource/
Dtimer-u300.c193 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_shutdown()
196 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_shutdown()
214 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_oneshot()
217 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_oneshot()
223 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); in u300_set_oneshot()
225 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, in u300_set_oneshot()
228 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, in u300_set_oneshot()
231 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, in u300_set_oneshot()
242 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_periodic()
245 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_periodic()
[all …]
/drivers/media/platform/s5p-jpeg/
Djpeg-hw-exynos3250.c26 writel(1, regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
38 writel(1, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
44 writel(0, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
49 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); in exynos3250_jpeg_poweron()
54 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & in exynos3250_jpeg_set_dma_num()
69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
120 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_input_raw_fmt()
132 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16()
146 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode()
168 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode()
[all …]
Djpeg-hw-exynos4.c24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
129 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_img_fmt()
162 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_enc_out_fmt()
171 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt()
175 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt()
204 writel(reg | EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
207 writel(reg & ~EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
[all …]
Djpeg-hw-s5p.c24 writel(1, regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
35 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); in s5p_jpeg_poweron()
51 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
66 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
81 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
96 writel(reg, regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
101 writel(reg, regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
111 writel(reg, regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
122 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
133 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_dc()
[all …]
/drivers/scsi/bfa/
Dbfa_ioc_ct.c74 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
76 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
77 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
96 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
105 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
107 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
125 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
129 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
139 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
140 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
[all …]
Dbfa_ioc_cb.c122 writel(~0U, ioc->ioc_regs.err_set); in bfa_ioc_cb_notify_fail()
235 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_start()
236 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); in bfa_ioc_cb_sync_start()
256 writel(1, ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_cb_ownership_reset()
268 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_join()
277 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_leave()
286 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_cur_ioc_fwstate()
303 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_alt_ioc_fwstate()
379 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_cb_pll_init()
382 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_cb_pll_init()
[all …]
/drivers/net/ethernet/brocade/bna/
Dbfa_ioc_ct.c139 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
141 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
165 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
190 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
199 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
200 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
427 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
437 writel(1, ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
460 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron()
465 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | in bfa_nw_ioc_ct2_poweron()
[all …]
/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr_v6.c38 #undef writel
39 #define writel(v, r) \ macro
416 writel(strm_size, mfc_regs->d_stream_data_size); in s5p_mfc_set_dec_stream_buffer_v6()
417 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); in s5p_mfc_set_dec_stream_buffer_v6()
418 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); in s5p_mfc_set_dec_stream_buffer_v6()
419 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); in s5p_mfc_set_dec_stream_buffer_v6()
443 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); in s5p_mfc_set_dec_frame_buffer_v6()
444 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
445 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
447 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); in s5p_mfc_set_dec_frame_buffer_v6()
[all …]
/drivers/phy/
Dphy-rockchip-typec.c342 writel(0x830, tcphy->base + PMA_CMN_CTRL1); in tcphy_cfg_24m()
348 writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i)); in tcphy_cfg_24m()
349 writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i)); in tcphy_cfg_24m()
350 writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i)); in tcphy_cfg_24m()
356 writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL); in tcphy_cfg_24m()
365 writel(usb3_pll_cfg[i].value, in tcphy_cfg_usb3_pll()
374 writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR, in tcphy_cfg_dp_pll()
379 writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr); in tcphy_cfg_dp_pll()
384 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
385 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
[all …]
Dphy-mt65xx-usb3.c169 writel(tmp, instance->port_base + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
175 writel(tmp, sif_base + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
182 writel(tmp, sif_base + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
187 writel(tmp, sif_base + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
198 writel(tmp, sif_base + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
203 writel(tmp, sif_base + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
221 writel(tmp, instance->port_base + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
226 writel(tmp, instance->port_base + U3P_USBPHYACR5); in hs_slew_rate_calibrate()
240 writel(tmp, port_base + U3P_U2PHYDTM0); in phy_instance_init()
244 writel(tmp, port_base + U3P_U2PHYDTM1); in phy_instance_init()
[all …]
/drivers/net/hippi/
Drrunner.c189 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, in rr_init_one()
231 writel(HALT_NIC, &rr->regs->HostCtrl); in rr_remove_one()
272 writel(*(u32*)(cmd), &regs->CmdRing[idx]); in rr_issue_cmd()
300 writel(0x01000000, &regs->TX_state); in rr_reset()
301 writel(0xff800000, &regs->RX_state); in rr_reset()
302 writel(0, &regs->AssistState); in rr_reset()
303 writel(CLEAR_INTA, &regs->LocalCtrl); in rr_reset()
304 writel(0x01, &regs->BrkPt); in rr_reset()
305 writel(0, &regs->Timer); in rr_reset()
306 writel(0, &regs->TimerRef); in rr_reset()
[all …]
/drivers/spi/
Dspi-sirf.c307 writel(readl(sspi->base + sspi->regs->usp_mode1) & in sirfsoc_usp_hwinit()
309 writel(readl(sspi->base + sspi->regs->usp_mode1) | in sirfsoc_usp_hwinit()
337 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u8()
366 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u16()
396 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u32()
409 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
410 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
422 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
425 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq()
428 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
[all …]
/drivers/video/fbdev/geode/
Ddisplay_gx1.c90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode()
138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); in gx1_set_mode()
139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, in gx1_set_mode()
166 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode()
168 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode()
[all …]
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac4_lib.c24 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
40 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(0)); in dwmac4_set_rx_tail_ptr()
45 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(0)); in dwmac4_set_tx_tail_ptr()
53 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_start_tx()
57 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
65 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_stop_tx()
69 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_stop_tx()
78 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_start_rx()
82 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
90 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_stop_rx()
[all …]
/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_dma.c41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
69 writel(upper_32_bits(dma_tx), in sxgbe_dma_channel_init()
71 writel(lower_32_bits(dma_tx), in sxgbe_dma_channel_init()
74 writel(upper_32_bits(dma_rx), in sxgbe_dma_channel_init()
76 writel(lower_32_bits(dma_rx), in sxgbe_dma_channel_init()
84 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
88 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
[all …]
/drivers/media/platform/exynos-gsc/
Dgsc-regs.c20 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
47 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
59 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
71 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK); in gsc_hw_set_input_buf_masking()
72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK); in gsc_hw_set_input_buf_masking()
73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK); in gsc_hw_set_input_buf_masking()
85 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); in gsc_hw_set_output_buf_masking()
86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK); in gsc_hw_set_output_buf_masking()
87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK); in gsc_hw_set_output_buf_masking()
95 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index)); in gsc_hw_set_input_addr()
[all …]
/drivers/media/platform/exynos4-is/
Dfimc-reg.c28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
103 writel(flip, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation()
142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
147 writel(cfg, dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); in fimc_hw_set_out_dma_size()
165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
179 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); in fimc_hw_set_out_dma()
[all …]
/drivers/irqchip/
Dirq-sun4i.c46 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_irq_ack()
57 writel(val & ~(1 << irq_off), in sun4i_irq_mask()
69 writel(val | (1 << irq_off), in sun4i_irq_unmask()
104 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); in sun4i_of_init()
105 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); in sun4i_of_init()
106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); in sun4i_of_init()
109 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); in sun4i_of_init()
110 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); in sun4i_of_init()
111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); in sun4i_of_init()
114 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_of_init()
[all …]
/drivers/net/ethernet/sun/
Dsungem.c127 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_read()
165 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_write()
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints()
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints()
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset()
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset()
391 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
405 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset()
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset()
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset()
[all …]

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