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Searched refs:writereg (Results 1 – 25 of 25) sorted by relevance

/drivers/video/fbdev/
Dgxt4500.c141 #define writereg(par, reg, val) writel((val), (par)->regs + (reg)) macro
395 writereg(par, DTG_CONTROL, ctrlreg); in gxt4500_set_par()
407 writereg(par, PLL_C, tmp); in gxt4500_set_par()
408 writereg(par, PLL_M, mdivtab[par->pll_m - 1]); in gxt4500_set_par()
409 writereg(par, PLL_N, ndivtab[par->pll_n - 2]); in gxt4500_set_par()
413 writereg(par, PLL_POSTDIV, tmp | 0x9); in gxt4500_set_par()
416 writereg(par, PLL_POSTDIV, tmp); in gxt4500_set_par()
420 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF); in gxt4500_set_par()
423 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16)); in gxt4500_set_par()
425 writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16); in gxt4500_set_par()
[all …]
/drivers/net/ethernet/cirrus/
Dmac89x0.c162 writereg(struct net_device *dev, int portno, int value) in writereg() function
305 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
331 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); in net_open()
339 writereg(dev, PP_CS8900_ISAINT, 0); in net_open()
341 writereg(dev, PP_CS8920_ISAINT, 0); in net_open()
345 writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); in net_open()
348 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); in net_open()
352 writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); in net_open()
356 writereg(dev, PP_RxCFG, lp->curr_rx_cfg); in net_open()
358 writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | in net_open()
[all …]
Dcs89x0.c233 writereg(struct net_device *dev, u16 regno, u16 value) in writereg() function
265 writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); in get_eeprom_data()
307 writereg(dev, PP_CS8900_ISAINT, i); in write_irq()
309 writereg(dev, PP_CS8920_ISAINT, irq); in write_irq()
364 writereg(dev, PP_CS8900_ISADMA, dma - 5); in write_dma()
366 writereg(dev, PP_CS8920_ISADMA, dma); in write_dma()
502 writereg(dev, PP_SelfCTL, selfcontrol); in control_dc_dc()
522 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); in send_test_pkt()
574 writereg(dev, PP_LineCTL, lp->linectl & ~AUI_ONLY); in detect_tp()
601 writereg(dev, PP_TestCTL, in detect_tp()
[all …]
/drivers/isdn/hisax/
Dasuscom.c62 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); in WriteISAC()
110 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80, value); in WriteISAC_IPAC()
135 writereg(cs->hw.asus.adr, in WriteHSCX()
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \
184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); in asuscom_interrupt()
185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); in asuscom_interrupt()
186 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF); in asuscom_interrupt()
187 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0); in asuscom_interrupt()
188 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); in asuscom_interrupt()
[all …]
Dsedlbauer.c138 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
162 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); in WriteISAC()
186 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80, value); in WriteISAC_IPAC()
211 writereg(cs->hw.sedl.adr, in WriteHSCX()
235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); in WriteISAR()
249 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \
296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); in sedlbauer_interrupt()
297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); in sedlbauer_interrupt()
298 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); in sedlbauer_interrupt()
299 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); in sedlbauer_interrupt()
[all …]
Dmic.c50 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); in WriteISAC()
99 writereg(cs->hw.mic.adr, in WriteHSCX()
109 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); in mic_interrupt()
149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); in mic_interrupt()
150 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF); in mic_interrupt()
151 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0); in mic_interrupt()
152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); in mic_interrupt()
153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); in mic_interrupt()
Ds0box.c22 writereg(unsigned int padr, signed int addr, u_char off, u_char val) { in writereg() function
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); in WriteISAC()
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, d…
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in s0box_interrupt()
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in s0box_interrupt()
177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF); in s0box_interrupt()
178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0); in s0box_interrupt()
179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); in s0box_interrupt()
180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); in s0box_interrupt()
Dsaphir.c52 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in WriteHSCX()
107 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); in saphir_interrupt()
152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); in saphir_interrupt()
153 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); in saphir_interrupt()
154 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); in saphir_interrupt()
155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); in saphir_interrupt()
156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); in saphir_interrupt()
Davm_a1.c35 writereg(unsigned int adr, u_char off, u_char data) in writereg() function
64 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
88 writereg(cs->hw.avm.hscx[hscx], offset, value); in WriteHSCX()
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); in avm_a1_interrupt()
128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); in avm_a1_interrupt()
129 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); in avm_a1_interrupt()
130 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); in avm_a1_interrupt()
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); in avm_a1_interrupt()
132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); in avm_a1_interrupt()
Dix1_micro.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
109 writereg(cs->hw.ix1.hscx_ale, in WriteHSCX()
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); in ix1micro_interrupt()
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); in ix1micro_interrupt()
156 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); in ix1micro_interrupt()
157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); in ix1micro_interrupt()
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); in ix1micro_interrupt()
159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); in ix1micro_interrupt()
Dbkm_a8.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); in WriteISAC()
111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, in set_ipac_active()
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
184 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); in bkm_interrupt_ipac()
185 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); in bkm_interrupt_ipac()
380 writereg(pci_ioaddr5, pci_ioaddr5 + 4, in setup_sct_quadro()
382 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c, in setup_sct_quadro()
384 writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14, in setup_sct_quadro()
[all …]
Dniccy.c62 static inline void writereg(unsigned int ale, unsigned int adr, u_char off, in writereg() function
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
107 writereg(cs->hw.niccy.hscx_ale, in WriteHSCX()
113 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); in niccy_interrupt()
163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, in niccy_interrupt()
165 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); in niccy_interrupt()
166 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); in niccy_interrupt()
167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); in niccy_interrupt()
168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); in niccy_interrupt()
Delsa.c160 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
184 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); in WriteISAC()
208 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset | 0x80, value); in WriteISAC_IPAC()
233 writereg(cs->hw.elsa.ale, in WriteHSCX()
272 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \
333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); in elsa_interrupt()
334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); in elsa_interrupt()
335 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF); in elsa_interrupt()
355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); in elsa_interrupt()
356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); in elsa_interrupt()
[all …]
Dteles3.c35 writereg(unsigned int adr, u_char off, u_char data) in writereg() function
64 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
88 writereg(cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in teles3_interrupt()
136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in teles3_interrupt()
137 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); in teles3_interrupt()
138 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); in teles3_interrupt()
139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); in teles3_interrupt()
140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); in teles3_interrupt()
Dbkm_a4t.c51 writereg(unsigned int ale, unsigned long adr, u_char off, u_char data) in writereg() function
67 writereg(ale, adr, off, *data++); in writefifo()
82 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value); in WriteISAC()
106 …writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)),… in WriteJADE()
115 #define WRITEJADE(cs, nr, reg, data) writereg(cs->hw.ax.jade_ale, \
Ddiva.c100 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); in WriteISAC()
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value); in WriteISAC_IPAC()
189 writereg(cs->hw.diva.hscx_adr, in WriteHSCX()
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); in diva_interrupt()
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); in diva_interrupt()
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); in diva_interrupt()
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); in diva_interrupt()
313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); in diva_interrupt()
[all …]
Dteleint.c64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); in WriteISAC()
175 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF); in TeleInt_interrupt()
176 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0); in TeleInt_interrupt()
Dgazel.c51 writereg(unsigned int adr, u_short off, u_char data) in writereg() function
129 writereg(cs->hw.gazel.isac, off2, value); in WriteISAC()
224 writereg(cs->hw.gazel.hscx[hscx], off2, value); in WriteHSCX()
354 writereg(addr, 0, 0); in reset_gazel()
356 writereg(addr, 0, 1); in reset_gazel()
/drivers/net/ethernet/amd/
Ddeclance.c294 static inline void writereg(volatile unsigned short *regptr, short value) in writereg() function
311 writereg(&ll->rap, LE_CSR1); in load_csrs()
312 writereg(&ll->rdp, (leptr & 0xFFFF)); in load_csrs()
313 writereg(&ll->rap, LE_CSR2); in load_csrs()
314 writereg(&ll->rdp, leptr >> 16); in load_csrs()
315 writereg(&ll->rap, LE_CSR3); in load_csrs()
316 writereg(&ll->rdp, lp->busmaster_regval); in load_csrs()
319 writereg(&ll->rap, LE_CSR0); in load_csrs()
530 writereg(&ll->rap, LE_CSR0); in init_restart_lance()
531 writereg(&ll->rdp, LE_C0_INIT); in init_restart_lance()
[all …]
Dni65.c159 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
166 #define writedatareg(val) { writereg(val,CSR0); }
169 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} macro
171 #define writedatareg(val) { writereg(val,CSR0); }
273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ in ni65_set_performance()
282 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */ in ni65_set_performance()
538 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()
577 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); in ni65_init_lance()
588 writereg(0,CSR3); /* busmaster/no word-swap */ in ni65_init_lance()
590 writereg(pib & 0xffff,CSR1); in ni65_init_lance()
[all …]
/drivers/media/pci/zoran/
Dzr36016.c104 if (ptr->codec->master_data->writereg) { in zr36016_write()
105 ptr->codec->master_data->writereg(ptr->codec, reg, value); in zr36016_write()
123 if ((ptr->codec->master_data->writereg) && in zr36016_readi()
125 ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F); // ADDR in zr36016_readi()
147 if (ptr->codec->master_data->writereg) { in zr36016_writei()
148 ptr->codec->master_data->writereg(ptr->codec, ZR016_IADDR, reg & 0x0F); // ADDR in zr36016_writei()
149 ptr->codec->master_data->writereg(ptr->codec, ZR016_IDATA, value & 0x0FF); // DATA in zr36016_writei()
Dvideocodec.h327 void (*writereg) (struct videocodec * codec, member
Dzr36050.c101 if (ptr->codec->master_data->writereg) in zr36050_write()
102 ptr->codec->master_data->writereg(ptr->codec, reg, value); in zr36050_write()
Dzr36060.c104 if (ptr->codec->master_data->writereg) in zr36060_write()
105 ptr->codec->master_data->writereg(ptr->codec, reg, value); in zr36060_write()
Dzoran_card.c1159 m->writereg = zr36060_write; in zoran_setup_videocodec()
1164 m->writereg = zr36050_write; in zoran_setup_videocodec()
1169 m->writereg = zr36016_write; in zoran_setup_videocodec()