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1 /*
2  *
3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
4  *
5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6  *  Copyright (c) 2006 ATI Technologies Inc.
7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10  *
11  *  Authors:
12  *			Wu Fengguang <wfg@linux.intel.com>
13  *
14  *  Maintained by:
15  *			Wu Fengguang <wfg@linux.intel.com>
16  *
17  *  This program is free software; you can redistribute it and/or modify it
18  *  under the terms of the GNU General Public License as published by the Free
19  *  Software Foundation; either version 2 of the License, or (at your option)
20  *  any later version.
21  *
22  *  This program is distributed in the hope that it will be useful, but
23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25  *  for more details.
26  *
27  *  You should have received a copy of the GNU General Public License
28  *  along with this program; if not, write to the Free Software Foundation,
29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
30  */
31 
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
45 #include "hda_jack.h"
46 
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50 
51 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 				|| is_skylake(codec) || is_broxton(codec) \
58 				|| is_kabylake(codec))
59 
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
63 
64 struct hdmi_spec_per_cvt {
65 	hda_nid_t cvt_nid;
66 	int assigned;
67 	unsigned int channels_min;
68 	unsigned int channels_max;
69 	u32 rates;
70 	u64 formats;
71 	unsigned int maxbps;
72 };
73 
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS	32
76 
77 struct hdmi_spec_per_pin {
78 	hda_nid_t pin_nid;
79 	/* pin idx, different device entries on the same pin use the same idx */
80 	int pin_nid_idx;
81 	int num_mux_nids;
82 	hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
83 	int mux_idx;
84 	hda_nid_t cvt_nid;
85 
86 	struct hda_codec *codec;
87 	struct hdmi_eld sink_eld;
88 	struct mutex lock;
89 	struct delayed_work work;
90 	struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
91 	int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
92 	int repoll_count;
93 	bool setup; /* the stream has been set up by prepare callback */
94 	int channels; /* current number of channels */
95 	bool non_pcm;
96 	bool chmap_set;		/* channel-map override by ALSA API? */
97 	unsigned char chmap[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 	struct snd_info_entry *proc_entry;
100 #endif
101 };
102 
103 /* operations used by generic code that can be overridden by patches */
104 struct hdmi_ops {
105 	int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 			   unsigned char *buf, int *eld_size);
107 
108 	void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 				    int ca, int active_channels, int conn_type);
110 
111 	/* enable/disable HBR (HD passthrough) */
112 	int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
113 
114 	int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 			    hda_nid_t pin_nid, u32 stream_tag, int format);
116 
117 	void (*pin_cvt_fixup)(struct hda_codec *codec,
118 			      struct hdmi_spec_per_pin *per_pin,
119 			      hda_nid_t cvt_nid);
120 };
121 
122 struct hdmi_pcm {
123 	struct hda_pcm *pcm;
124 	struct snd_jack *jack;
125 	struct snd_kcontrol *eld_ctl;
126 };
127 
128 struct hdmi_spec {
129 	int num_cvts;
130 	struct snd_array cvts; /* struct hdmi_spec_per_cvt */
131 	hda_nid_t cvt_nids[4]; /* only for haswell fix */
132 
133 	int num_pins;
134 	struct snd_array pins; /* struct hdmi_spec_per_pin */
135 	struct hdmi_pcm pcm_rec[16];
136 	struct mutex pcm_lock;
137 	/* pcm_bitmap means which pcms have been assigned to pins*/
138 	unsigned long pcm_bitmap;
139 	int pcm_used;	/* counter of pcm_rec[] */
140 	/* bitmap shows whether the pcm is opened in user space
141 	 * bit 0 means the first playback PCM (PCM3);
142 	 * bit 1 means the second playback PCM, and so on.
143 	 */
144 	unsigned long pcm_in_use;
145 
146 	struct hdmi_eld temp_eld;
147 	struct hdmi_ops ops;
148 
149 	bool dyn_pin_out;
150 	bool dyn_pcm_assign;
151 	/*
152 	 * Non-generic VIA/NVIDIA specific
153 	 */
154 	struct hda_multi_out multiout;
155 	struct hda_pcm_stream pcm_playback;
156 
157 	/* i915/powerwell (Haswell+/Valleyview+) specific */
158 	bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
159 	struct i915_audio_component_audio_ops i915_audio_ops;
160 	bool i915_bound; /* was i915 bound in this driver? */
161 
162 	struct hdac_chmap chmap;
163 };
164 
165 #ifdef CONFIG_SND_HDA_I915
codec_has_acomp(struct hda_codec * codec)166 static inline bool codec_has_acomp(struct hda_codec *codec)
167 {
168 	struct hdmi_spec *spec = codec->spec;
169 	return spec->use_acomp_notifier;
170 }
171 #else
172 #define codec_has_acomp(codec)	false
173 #endif
174 
175 struct hdmi_audio_infoframe {
176 	u8 type; /* 0x84 */
177 	u8 ver;  /* 0x01 */
178 	u8 len;  /* 0x0a */
179 
180 	u8 checksum;
181 
182 	u8 CC02_CT47;	/* CC in bits 0:2, CT in 4:7 */
183 	u8 SS01_SF24;
184 	u8 CXT04;
185 	u8 CA;
186 	u8 LFEPBL01_LSV36_DM_INH7;
187 };
188 
189 struct dp_audio_infoframe {
190 	u8 type; /* 0x84 */
191 	u8 len;  /* 0x1b */
192 	u8 ver;  /* 0x11 << 2 */
193 
194 	u8 CC02_CT47;	/* match with HDMI infoframe from this on */
195 	u8 SS01_SF24;
196 	u8 CXT04;
197 	u8 CA;
198 	u8 LFEPBL01_LSV36_DM_INH7;
199 };
200 
201 union audio_infoframe {
202 	struct hdmi_audio_infoframe hdmi;
203 	struct dp_audio_infoframe dp;
204 	u8 bytes[0];
205 };
206 
207 /*
208  * HDMI routines
209  */
210 
211 #define get_pin(spec, idx) \
212 	((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
213 #define get_cvt(spec, idx) \
214 	((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
215 /* obtain hdmi_pcm object assigned to idx */
216 #define get_hdmi_pcm(spec, idx)	(&(spec)->pcm_rec[idx])
217 /* obtain hda_pcm object assigned to idx */
218 #define get_pcm_rec(spec, idx)	(get_hdmi_pcm(spec, idx)->pcm)
219 
pin_nid_to_pin_index(struct hda_codec * codec,hda_nid_t pin_nid)220 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
221 {
222 	struct hdmi_spec *spec = codec->spec;
223 	int pin_idx;
224 
225 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
226 		if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
227 			return pin_idx;
228 
229 	codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
230 	return -EINVAL;
231 }
232 
hinfo_to_pcm_index(struct hda_codec * codec,struct hda_pcm_stream * hinfo)233 static int hinfo_to_pcm_index(struct hda_codec *codec,
234 			struct hda_pcm_stream *hinfo)
235 {
236 	struct hdmi_spec *spec = codec->spec;
237 	int pcm_idx;
238 
239 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
240 		if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
241 			return pcm_idx;
242 
243 	codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
244 	return -EINVAL;
245 }
246 
hinfo_to_pin_index(struct hda_codec * codec,struct hda_pcm_stream * hinfo)247 static int hinfo_to_pin_index(struct hda_codec *codec,
248 			      struct hda_pcm_stream *hinfo)
249 {
250 	struct hdmi_spec *spec = codec->spec;
251 	struct hdmi_spec_per_pin *per_pin;
252 	int pin_idx;
253 
254 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
255 		per_pin = get_pin(spec, pin_idx);
256 		if (per_pin->pcm &&
257 			per_pin->pcm->pcm->stream == hinfo)
258 			return pin_idx;
259 	}
260 
261 	codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
262 	return -EINVAL;
263 }
264 
pcm_idx_to_pin(struct hdmi_spec * spec,int pcm_idx)265 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
266 						int pcm_idx)
267 {
268 	int i;
269 	struct hdmi_spec_per_pin *per_pin;
270 
271 	for (i = 0; i < spec->num_pins; i++) {
272 		per_pin = get_pin(spec, i);
273 		if (per_pin->pcm_idx == pcm_idx)
274 			return per_pin;
275 	}
276 	return NULL;
277 }
278 
cvt_nid_to_cvt_index(struct hda_codec * codec,hda_nid_t cvt_nid)279 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
280 {
281 	struct hdmi_spec *spec = codec->spec;
282 	int cvt_idx;
283 
284 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
285 		if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
286 			return cvt_idx;
287 
288 	codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
289 	return -EINVAL;
290 }
291 
hdmi_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)292 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
293 			struct snd_ctl_elem_info *uinfo)
294 {
295 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
296 	struct hdmi_spec *spec = codec->spec;
297 	struct hdmi_spec_per_pin *per_pin;
298 	struct hdmi_eld *eld;
299 	int pcm_idx;
300 
301 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
302 
303 	pcm_idx = kcontrol->private_value;
304 	mutex_lock(&spec->pcm_lock);
305 	per_pin = pcm_idx_to_pin(spec, pcm_idx);
306 	if (!per_pin) {
307 		/* no pin is bound to the pcm */
308 		uinfo->count = 0;
309 		mutex_unlock(&spec->pcm_lock);
310 		return 0;
311 	}
312 	eld = &per_pin->sink_eld;
313 	uinfo->count = eld->eld_valid ? eld->eld_size : 0;
314 	mutex_unlock(&spec->pcm_lock);
315 
316 	return 0;
317 }
318 
hdmi_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)319 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
320 			struct snd_ctl_elem_value *ucontrol)
321 {
322 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
323 	struct hdmi_spec *spec = codec->spec;
324 	struct hdmi_spec_per_pin *per_pin;
325 	struct hdmi_eld *eld;
326 	int pcm_idx;
327 
328 	pcm_idx = kcontrol->private_value;
329 	mutex_lock(&spec->pcm_lock);
330 	per_pin = pcm_idx_to_pin(spec, pcm_idx);
331 	if (!per_pin) {
332 		/* no pin is bound to the pcm */
333 		memset(ucontrol->value.bytes.data, 0,
334 		       ARRAY_SIZE(ucontrol->value.bytes.data));
335 		mutex_unlock(&spec->pcm_lock);
336 		return 0;
337 	}
338 	eld = &per_pin->sink_eld;
339 
340 	if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
341 	    eld->eld_size > ELD_MAX_SIZE) {
342 		mutex_unlock(&spec->pcm_lock);
343 		snd_BUG();
344 		return -EINVAL;
345 	}
346 
347 	memset(ucontrol->value.bytes.data, 0,
348 	       ARRAY_SIZE(ucontrol->value.bytes.data));
349 	if (eld->eld_valid)
350 		memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
351 		       eld->eld_size);
352 	mutex_unlock(&spec->pcm_lock);
353 
354 	return 0;
355 }
356 
357 static struct snd_kcontrol_new eld_bytes_ctl = {
358 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
359 	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
360 	.name = "ELD",
361 	.info = hdmi_eld_ctl_info,
362 	.get = hdmi_eld_ctl_get,
363 };
364 
hdmi_create_eld_ctl(struct hda_codec * codec,int pcm_idx,int device)365 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
366 			int device)
367 {
368 	struct snd_kcontrol *kctl;
369 	struct hdmi_spec *spec = codec->spec;
370 	int err;
371 
372 	kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
373 	if (!kctl)
374 		return -ENOMEM;
375 	kctl->private_value = pcm_idx;
376 	kctl->id.device = device;
377 
378 	/* no pin nid is associated with the kctl now
379 	 * tbd: associate pin nid to eld ctl later
380 	 */
381 	err = snd_hda_ctl_add(codec, 0, kctl);
382 	if (err < 0)
383 		return err;
384 
385 	get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
386 	return 0;
387 }
388 
389 #ifdef BE_PARANOID
hdmi_get_dip_index(struct hda_codec * codec,hda_nid_t pin_nid,int * packet_index,int * byte_index)390 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
391 				int *packet_index, int *byte_index)
392 {
393 	int val;
394 
395 	val = snd_hda_codec_read(codec, pin_nid, 0,
396 				 AC_VERB_GET_HDMI_DIP_INDEX, 0);
397 
398 	*packet_index = val >> 5;
399 	*byte_index = val & 0x1f;
400 }
401 #endif
402 
hdmi_set_dip_index(struct hda_codec * codec,hda_nid_t pin_nid,int packet_index,int byte_index)403 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
404 				int packet_index, int byte_index)
405 {
406 	int val;
407 
408 	val = (packet_index << 5) | (byte_index & 0x1f);
409 
410 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
411 }
412 
hdmi_write_dip_byte(struct hda_codec * codec,hda_nid_t pin_nid,unsigned char val)413 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
414 				unsigned char val)
415 {
416 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
417 }
418 
hdmi_init_pin(struct hda_codec * codec,hda_nid_t pin_nid)419 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
420 {
421 	struct hdmi_spec *spec = codec->spec;
422 	int pin_out;
423 
424 	/* Unmute */
425 	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
426 		snd_hda_codec_write(codec, pin_nid, 0,
427 				AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
428 
429 	if (spec->dyn_pin_out)
430 		/* Disable pin out until stream is active */
431 		pin_out = 0;
432 	else
433 		/* Enable pin out: some machines with GM965 gets broken output
434 		 * when the pin is disabled or changed while using with HDMI
435 		 */
436 		pin_out = PIN_OUT;
437 
438 	snd_hda_codec_write(codec, pin_nid, 0,
439 			    AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
440 }
441 
442 /*
443  * ELD proc files
444  */
445 
446 #ifdef CONFIG_SND_PROC_FS
print_eld_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)447 static void print_eld_info(struct snd_info_entry *entry,
448 			   struct snd_info_buffer *buffer)
449 {
450 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
451 
452 	mutex_lock(&per_pin->lock);
453 	snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
454 	mutex_unlock(&per_pin->lock);
455 }
456 
write_eld_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)457 static void write_eld_info(struct snd_info_entry *entry,
458 			   struct snd_info_buffer *buffer)
459 {
460 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
461 
462 	mutex_lock(&per_pin->lock);
463 	snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
464 	mutex_unlock(&per_pin->lock);
465 }
466 
eld_proc_new(struct hdmi_spec_per_pin * per_pin,int index)467 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
468 {
469 	char name[32];
470 	struct hda_codec *codec = per_pin->codec;
471 	struct snd_info_entry *entry;
472 	int err;
473 
474 	snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
475 	err = snd_card_proc_new(codec->card, name, &entry);
476 	if (err < 0)
477 		return err;
478 
479 	snd_info_set_text_ops(entry, per_pin, print_eld_info);
480 	entry->c.text.write = write_eld_info;
481 	entry->mode |= S_IWUSR;
482 	per_pin->proc_entry = entry;
483 
484 	return 0;
485 }
486 
eld_proc_free(struct hdmi_spec_per_pin * per_pin)487 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
488 {
489 	if (!per_pin->codec->bus->shutdown) {
490 		snd_info_free_entry(per_pin->proc_entry);
491 		per_pin->proc_entry = NULL;
492 	}
493 }
494 #else
eld_proc_new(struct hdmi_spec_per_pin * per_pin,int index)495 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
496 			       int index)
497 {
498 	return 0;
499 }
eld_proc_free(struct hdmi_spec_per_pin * per_pin)500 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
501 {
502 }
503 #endif
504 
505 /*
506  * Audio InfoFrame routines
507  */
508 
509 /*
510  * Enable Audio InfoFrame Transmission
511  */
hdmi_start_infoframe_trans(struct hda_codec * codec,hda_nid_t pin_nid)512 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
513 				       hda_nid_t pin_nid)
514 {
515 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
516 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
517 						AC_DIPXMIT_BEST);
518 }
519 
520 /*
521  * Disable Audio InfoFrame Transmission
522  */
hdmi_stop_infoframe_trans(struct hda_codec * codec,hda_nid_t pin_nid)523 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
524 				      hda_nid_t pin_nid)
525 {
526 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
527 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
528 						AC_DIPXMIT_DISABLE);
529 }
530 
hdmi_debug_dip_size(struct hda_codec * codec,hda_nid_t pin_nid)531 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
532 {
533 #ifdef CONFIG_SND_DEBUG_VERBOSE
534 	int i;
535 	int size;
536 
537 	size = snd_hdmi_get_eld_size(codec, pin_nid);
538 	codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
539 
540 	for (i = 0; i < 8; i++) {
541 		size = snd_hda_codec_read(codec, pin_nid, 0,
542 						AC_VERB_GET_HDMI_DIP_SIZE, i);
543 		codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
544 	}
545 #endif
546 }
547 
hdmi_clear_dip_buffers(struct hda_codec * codec,hda_nid_t pin_nid)548 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
549 {
550 #ifdef BE_PARANOID
551 	int i, j;
552 	int size;
553 	int pi, bi;
554 	for (i = 0; i < 8; i++) {
555 		size = snd_hda_codec_read(codec, pin_nid, 0,
556 						AC_VERB_GET_HDMI_DIP_SIZE, i);
557 		if (size == 0)
558 			continue;
559 
560 		hdmi_set_dip_index(codec, pin_nid, i, 0x0);
561 		for (j = 1; j < 1000; j++) {
562 			hdmi_write_dip_byte(codec, pin_nid, 0x0);
563 			hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
564 			if (pi != i)
565 				codec_dbg(codec, "dip index %d: %d != %d\n",
566 						bi, pi, i);
567 			if (bi == 0) /* byte index wrapped around */
568 				break;
569 		}
570 		codec_dbg(codec,
571 			"HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
572 			i, size, j);
573 	}
574 #endif
575 }
576 
hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe * hdmi_ai)577 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
578 {
579 	u8 *bytes = (u8 *)hdmi_ai;
580 	u8 sum = 0;
581 	int i;
582 
583 	hdmi_ai->checksum = 0;
584 
585 	for (i = 0; i < sizeof(*hdmi_ai); i++)
586 		sum += bytes[i];
587 
588 	hdmi_ai->checksum = -sum;
589 }
590 
hdmi_fill_audio_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,u8 * dip,int size)591 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
592 				      hda_nid_t pin_nid,
593 				      u8 *dip, int size)
594 {
595 	int i;
596 
597 	hdmi_debug_dip_size(codec, pin_nid);
598 	hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
599 
600 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
601 	for (i = 0; i < size; i++)
602 		hdmi_write_dip_byte(codec, pin_nid, dip[i]);
603 }
604 
hdmi_infoframe_uptodate(struct hda_codec * codec,hda_nid_t pin_nid,u8 * dip,int size)605 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
606 				    u8 *dip, int size)
607 {
608 	u8 val;
609 	int i;
610 
611 	if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
612 							    != AC_DIPXMIT_BEST)
613 		return false;
614 
615 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
616 	for (i = 0; i < size; i++) {
617 		val = snd_hda_codec_read(codec, pin_nid, 0,
618 					 AC_VERB_GET_HDMI_DIP_DATA, 0);
619 		if (val != dip[i])
620 			return false;
621 	}
622 
623 	return true;
624 }
625 
hdmi_pin_setup_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,int ca,int active_channels,int conn_type)626 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
627 				     hda_nid_t pin_nid,
628 				     int ca, int active_channels,
629 				     int conn_type)
630 {
631 	union audio_infoframe ai;
632 
633 	memset(&ai, 0, sizeof(ai));
634 	if (conn_type == 0) { /* HDMI */
635 		struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
636 
637 		hdmi_ai->type		= 0x84;
638 		hdmi_ai->ver		= 0x01;
639 		hdmi_ai->len		= 0x0a;
640 		hdmi_ai->CC02_CT47	= active_channels - 1;
641 		hdmi_ai->CA		= ca;
642 		hdmi_checksum_audio_infoframe(hdmi_ai);
643 	} else if (conn_type == 1) { /* DisplayPort */
644 		struct dp_audio_infoframe *dp_ai = &ai.dp;
645 
646 		dp_ai->type		= 0x84;
647 		dp_ai->len		= 0x1b;
648 		dp_ai->ver		= 0x11 << 2;
649 		dp_ai->CC02_CT47	= active_channels - 1;
650 		dp_ai->CA		= ca;
651 	} else {
652 		codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
653 			    pin_nid);
654 		return;
655 	}
656 
657 	/*
658 	 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
659 	 * sizeof(*dp_ai) to avoid partial match/update problems when
660 	 * the user switches between HDMI/DP monitors.
661 	 */
662 	if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
663 					sizeof(ai))) {
664 		codec_dbg(codec,
665 			  "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
666 			    pin_nid,
667 			    active_channels, ca);
668 		hdmi_stop_infoframe_trans(codec, pin_nid);
669 		hdmi_fill_audio_infoframe(codec, pin_nid,
670 					    ai.bytes, sizeof(ai));
671 		hdmi_start_infoframe_trans(codec, pin_nid);
672 	}
673 }
674 
hdmi_setup_audio_infoframe(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,bool non_pcm)675 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
676 				       struct hdmi_spec_per_pin *per_pin,
677 				       bool non_pcm)
678 {
679 	struct hdmi_spec *spec = codec->spec;
680 	struct hdac_chmap *chmap = &spec->chmap;
681 	hda_nid_t pin_nid = per_pin->pin_nid;
682 	int channels = per_pin->channels;
683 	int active_channels;
684 	struct hdmi_eld *eld;
685 	int ca;
686 
687 	if (!channels)
688 		return;
689 
690 	/* some HW (e.g. HSW+) needs reprogramming the amp at each time */
691 	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
692 		snd_hda_codec_write(codec, pin_nid, 0,
693 					    AC_VERB_SET_AMP_GAIN_MUTE,
694 					    AMP_OUT_UNMUTE);
695 
696 	eld = &per_pin->sink_eld;
697 
698 	ca = snd_hdac_channel_allocation(&codec->core,
699 			eld->info.spk_alloc, channels,
700 			per_pin->chmap_set, non_pcm, per_pin->chmap);
701 
702 	active_channels = snd_hdac_get_active_channels(ca);
703 
704 	chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
705 						active_channels);
706 
707 	/*
708 	 * always configure channel mapping, it may have been changed by the
709 	 * user in the meantime
710 	 */
711 	snd_hdac_setup_channel_mapping(&spec->chmap,
712 				pin_nid, non_pcm, ca, channels,
713 				per_pin->chmap, per_pin->chmap_set);
714 
715 	spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
716 				      eld->info.conn_type);
717 
718 	per_pin->non_pcm = non_pcm;
719 }
720 
721 /*
722  * Unsolicited events
723  */
724 
725 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
726 
check_presence_and_report(struct hda_codec * codec,hda_nid_t nid)727 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
728 {
729 	struct hdmi_spec *spec = codec->spec;
730 	int pin_idx = pin_nid_to_pin_index(codec, nid);
731 
732 	if (pin_idx < 0)
733 		return;
734 	if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
735 		snd_hda_jack_report_sync(codec);
736 }
737 
jack_callback(struct hda_codec * codec,struct hda_jack_callback * jack)738 static void jack_callback(struct hda_codec *codec,
739 			  struct hda_jack_callback *jack)
740 {
741 	check_presence_and_report(codec, jack->nid);
742 }
743 
hdmi_intrinsic_event(struct hda_codec * codec,unsigned int res)744 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
745 {
746 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
747 	struct hda_jack_tbl *jack;
748 	int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
749 
750 	jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
751 	if (!jack)
752 		return;
753 	jack->jack_dirty = 1;
754 
755 	codec_dbg(codec,
756 		"HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
757 		codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
758 		!!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
759 
760 	check_presence_and_report(codec, jack->nid);
761 }
762 
hdmi_non_intrinsic_event(struct hda_codec * codec,unsigned int res)763 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
764 {
765 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
766 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
767 	int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
768 	int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
769 
770 	codec_info(codec,
771 		"HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
772 		codec->addr,
773 		tag,
774 		subtag,
775 		cp_state,
776 		cp_ready);
777 
778 	/* TODO */
779 	if (cp_state)
780 		;
781 	if (cp_ready)
782 		;
783 }
784 
785 
hdmi_unsol_event(struct hda_codec * codec,unsigned int res)786 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
787 {
788 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
789 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
790 
791 	if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
792 		codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
793 		return;
794 	}
795 
796 	if (subtag == 0)
797 		hdmi_intrinsic_event(codec, res);
798 	else
799 		hdmi_non_intrinsic_event(codec, res);
800 }
801 
haswell_verify_D0(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t nid)802 static void haswell_verify_D0(struct hda_codec *codec,
803 		hda_nid_t cvt_nid, hda_nid_t nid)
804 {
805 	int pwr;
806 
807 	/* For Haswell, the converter 1/2 may keep in D3 state after bootup,
808 	 * thus pins could only choose converter 0 for use. Make sure the
809 	 * converters are in correct power state */
810 	if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
811 		snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
812 
813 	if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
814 		snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
815 				    AC_PWRST_D0);
816 		msleep(40);
817 		pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
818 		pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
819 		codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
820 	}
821 }
822 
823 /*
824  * Callbacks
825  */
826 
827 /* HBR should be Non-PCM, 8 channels */
828 #define is_hbr_format(format) \
829 	((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
830 
hdmi_pin_hbr_setup(struct hda_codec * codec,hda_nid_t pin_nid,bool hbr)831 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
832 			      bool hbr)
833 {
834 	int pinctl, new_pinctl;
835 
836 	if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
837 		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
838 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
839 
840 		if (pinctl < 0)
841 			return hbr ? -EINVAL : 0;
842 
843 		new_pinctl = pinctl & ~AC_PINCTL_EPT;
844 		if (hbr)
845 			new_pinctl |= AC_PINCTL_EPT_HBR;
846 		else
847 			new_pinctl |= AC_PINCTL_EPT_NATIVE;
848 
849 		codec_dbg(codec,
850 			  "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
851 			    pin_nid,
852 			    pinctl == new_pinctl ? "" : "new-",
853 			    new_pinctl);
854 
855 		if (pinctl != new_pinctl)
856 			snd_hda_codec_write(codec, pin_nid, 0,
857 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
858 					    new_pinctl);
859 	} else if (hbr)
860 		return -EINVAL;
861 
862 	return 0;
863 }
864 
hdmi_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,u32 stream_tag,int format)865 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
866 			      hda_nid_t pin_nid, u32 stream_tag, int format)
867 {
868 	struct hdmi_spec *spec = codec->spec;
869 	int err;
870 
871 	err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
872 
873 	if (err) {
874 		codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
875 		return err;
876 	}
877 
878 	snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
879 	return 0;
880 }
881 
882 /* Try to find an available converter
883  * If pin_idx is less then zero, just try to find an available converter.
884  * Otherwise, try to find an available converter and get the cvt mux index
885  * of the pin.
886  */
hdmi_choose_cvt(struct hda_codec * codec,int pin_idx,int * cvt_id)887 static int hdmi_choose_cvt(struct hda_codec *codec,
888 			   int pin_idx, int *cvt_id)
889 {
890 	struct hdmi_spec *spec = codec->spec;
891 	struct hdmi_spec_per_pin *per_pin;
892 	struct hdmi_spec_per_cvt *per_cvt = NULL;
893 	int cvt_idx, mux_idx = 0;
894 
895 	/* pin_idx < 0 means no pin will be bound to the converter */
896 	if (pin_idx < 0)
897 		per_pin = NULL;
898 	else
899 		per_pin = get_pin(spec, pin_idx);
900 
901 	/* Dynamically assign converter to stream */
902 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
903 		per_cvt = get_cvt(spec, cvt_idx);
904 
905 		/* Must not already be assigned */
906 		if (per_cvt->assigned)
907 			continue;
908 		if (per_pin == NULL)
909 			break;
910 		/* Must be in pin's mux's list of converters */
911 		for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
912 			if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
913 				break;
914 		/* Not in mux list */
915 		if (mux_idx == per_pin->num_mux_nids)
916 			continue;
917 		break;
918 	}
919 
920 	/* No free converters */
921 	if (cvt_idx == spec->num_cvts)
922 		return -EBUSY;
923 
924 	if (per_pin != NULL)
925 		per_pin->mux_idx = mux_idx;
926 
927 	if (cvt_id)
928 		*cvt_id = cvt_idx;
929 
930 	return 0;
931 }
932 
933 /* Assure the pin select the right convetor */
intel_verify_pin_cvt_connect(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)934 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
935 			struct hdmi_spec_per_pin *per_pin)
936 {
937 	hda_nid_t pin_nid = per_pin->pin_nid;
938 	int mux_idx, curr;
939 
940 	mux_idx = per_pin->mux_idx;
941 	curr = snd_hda_codec_read(codec, pin_nid, 0,
942 					  AC_VERB_GET_CONNECT_SEL, 0);
943 	if (curr != mux_idx)
944 		snd_hda_codec_write_cache(codec, pin_nid, 0,
945 					    AC_VERB_SET_CONNECT_SEL,
946 					    mux_idx);
947 }
948 
949 /* get the mux index for the converter of the pins
950  * converter's mux index is the same for all pins on Intel platform
951  */
intel_cvt_id_to_mux_idx(struct hdmi_spec * spec,hda_nid_t cvt_nid)952 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
953 			hda_nid_t cvt_nid)
954 {
955 	int i;
956 
957 	for (i = 0; i < spec->num_cvts; i++)
958 		if (spec->cvt_nids[i] == cvt_nid)
959 			return i;
960 	return -EINVAL;
961 }
962 
963 /* Intel HDMI workaround to fix audio routing issue:
964  * For some Intel display codecs, pins share the same connection list.
965  * So a conveter can be selected by multiple pins and playback on any of these
966  * pins will generate sound on the external display, because audio flows from
967  * the same converter to the display pipeline. Also muting one pin may make
968  * other pins have no sound output.
969  * So this function assures that an assigned converter for a pin is not selected
970  * by any other pins.
971  */
intel_not_share_assigned_cvt(struct hda_codec * codec,hda_nid_t pin_nid,int mux_idx)972 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
973 			hda_nid_t pin_nid, int mux_idx)
974 {
975 	struct hdmi_spec *spec = codec->spec;
976 	hda_nid_t nid;
977 	int cvt_idx, curr;
978 	struct hdmi_spec_per_cvt *per_cvt;
979 
980 	/* configure all pins, including "no physical connection" ones */
981 	for_each_hda_codec_node(nid, codec) {
982 		unsigned int wid_caps = get_wcaps(codec, nid);
983 		unsigned int wid_type = get_wcaps_type(wid_caps);
984 
985 		if (wid_type != AC_WID_PIN)
986 			continue;
987 
988 		if (nid == pin_nid)
989 			continue;
990 
991 		curr = snd_hda_codec_read(codec, nid, 0,
992 					  AC_VERB_GET_CONNECT_SEL, 0);
993 		if (curr != mux_idx)
994 			continue;
995 
996 		/* choose an unassigned converter. The conveters in the
997 		 * connection list are in the same order as in the codec.
998 		 */
999 		for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1000 			per_cvt = get_cvt(spec, cvt_idx);
1001 			if (!per_cvt->assigned) {
1002 				codec_dbg(codec,
1003 					  "choose cvt %d for pin nid %d\n",
1004 					cvt_idx, nid);
1005 				snd_hda_codec_write_cache(codec, nid, 0,
1006 					    AC_VERB_SET_CONNECT_SEL,
1007 					    cvt_idx);
1008 				break;
1009 			}
1010 		}
1011 	}
1012 }
1013 
1014 /* A wrapper of intel_not_share_asigned_cvt() */
intel_not_share_assigned_cvt_nid(struct hda_codec * codec,hda_nid_t pin_nid,hda_nid_t cvt_nid)1015 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1016 			hda_nid_t pin_nid, hda_nid_t cvt_nid)
1017 {
1018 	int mux_idx;
1019 	struct hdmi_spec *spec = codec->spec;
1020 
1021 	/* On Intel platform, the mapping of converter nid to
1022 	 * mux index of the pins are always the same.
1023 	 * The pin nid may be 0, this means all pins will not
1024 	 * share the converter.
1025 	 */
1026 	mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1027 	if (mux_idx >= 0)
1028 		intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1029 }
1030 
1031 /* skeleton caller of pin_cvt_fixup ops */
pin_cvt_fixup(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,hda_nid_t cvt_nid)1032 static void pin_cvt_fixup(struct hda_codec *codec,
1033 			  struct hdmi_spec_per_pin *per_pin,
1034 			  hda_nid_t cvt_nid)
1035 {
1036 	struct hdmi_spec *spec = codec->spec;
1037 
1038 	if (spec->ops.pin_cvt_fixup)
1039 		spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1040 }
1041 
1042 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1043  * in dyn_pcm_assign mode.
1044  */
hdmi_pcm_open_no_pin(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1045 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1046 			 struct hda_codec *codec,
1047 			 struct snd_pcm_substream *substream)
1048 {
1049 	struct hdmi_spec *spec = codec->spec;
1050 	struct snd_pcm_runtime *runtime = substream->runtime;
1051 	int cvt_idx, pcm_idx;
1052 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1053 	int err;
1054 
1055 	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1056 	if (pcm_idx < 0)
1057 		return -EINVAL;
1058 
1059 	err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1060 	if (err)
1061 		return err;
1062 
1063 	per_cvt = get_cvt(spec, cvt_idx);
1064 	per_cvt->assigned = 1;
1065 	hinfo->nid = per_cvt->cvt_nid;
1066 
1067 	pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1068 
1069 	set_bit(pcm_idx, &spec->pcm_in_use);
1070 	/* todo: setup spdif ctls assign */
1071 
1072 	/* Initially set the converter's capabilities */
1073 	hinfo->channels_min = per_cvt->channels_min;
1074 	hinfo->channels_max = per_cvt->channels_max;
1075 	hinfo->rates = per_cvt->rates;
1076 	hinfo->formats = per_cvt->formats;
1077 	hinfo->maxbps = per_cvt->maxbps;
1078 
1079 	/* Store the updated parameters */
1080 	runtime->hw.channels_min = hinfo->channels_min;
1081 	runtime->hw.channels_max = hinfo->channels_max;
1082 	runtime->hw.formats = hinfo->formats;
1083 	runtime->hw.rates = hinfo->rates;
1084 
1085 	snd_pcm_hw_constraint_step(substream->runtime, 0,
1086 				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1087 	return 0;
1088 }
1089 
1090 /*
1091  * HDA PCM callbacks
1092  */
hdmi_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1093 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1094 			 struct hda_codec *codec,
1095 			 struct snd_pcm_substream *substream)
1096 {
1097 	struct hdmi_spec *spec = codec->spec;
1098 	struct snd_pcm_runtime *runtime = substream->runtime;
1099 	int pin_idx, cvt_idx, pcm_idx;
1100 	struct hdmi_spec_per_pin *per_pin;
1101 	struct hdmi_eld *eld;
1102 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1103 	int err;
1104 
1105 	/* Validate hinfo */
1106 	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1107 	if (pcm_idx < 0)
1108 		return -EINVAL;
1109 
1110 	mutex_lock(&spec->pcm_lock);
1111 	pin_idx = hinfo_to_pin_index(codec, hinfo);
1112 	if (!spec->dyn_pcm_assign) {
1113 		if (snd_BUG_ON(pin_idx < 0)) {
1114 			mutex_unlock(&spec->pcm_lock);
1115 			return -EINVAL;
1116 		}
1117 	} else {
1118 		/* no pin is assigned to the PCM
1119 		 * PA need pcm open successfully when probe
1120 		 */
1121 		if (pin_idx < 0) {
1122 			err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1123 			mutex_unlock(&spec->pcm_lock);
1124 			return err;
1125 		}
1126 	}
1127 
1128 	err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1129 	if (err < 0) {
1130 		mutex_unlock(&spec->pcm_lock);
1131 		return err;
1132 	}
1133 
1134 	per_cvt = get_cvt(spec, cvt_idx);
1135 	/* Claim converter */
1136 	per_cvt->assigned = 1;
1137 
1138 	set_bit(pcm_idx, &spec->pcm_in_use);
1139 	per_pin = get_pin(spec, pin_idx);
1140 	per_pin->cvt_nid = per_cvt->cvt_nid;
1141 	hinfo->nid = per_cvt->cvt_nid;
1142 
1143 	snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1144 			    AC_VERB_SET_CONNECT_SEL,
1145 			    per_pin->mux_idx);
1146 
1147 	/* configure unused pins to choose other converters */
1148 	pin_cvt_fixup(codec, per_pin, 0);
1149 
1150 	snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1151 
1152 	/* Initially set the converter's capabilities */
1153 	hinfo->channels_min = per_cvt->channels_min;
1154 	hinfo->channels_max = per_cvt->channels_max;
1155 	hinfo->rates = per_cvt->rates;
1156 	hinfo->formats = per_cvt->formats;
1157 	hinfo->maxbps = per_cvt->maxbps;
1158 
1159 	eld = &per_pin->sink_eld;
1160 	/* Restrict capabilities by ELD if this isn't disabled */
1161 	if (!static_hdmi_pcm && eld->eld_valid) {
1162 		snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1163 		if (hinfo->channels_min > hinfo->channels_max ||
1164 		    !hinfo->rates || !hinfo->formats) {
1165 			per_cvt->assigned = 0;
1166 			hinfo->nid = 0;
1167 			snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1168 			mutex_unlock(&spec->pcm_lock);
1169 			return -ENODEV;
1170 		}
1171 	}
1172 
1173 	mutex_unlock(&spec->pcm_lock);
1174 	/* Store the updated parameters */
1175 	runtime->hw.channels_min = hinfo->channels_min;
1176 	runtime->hw.channels_max = hinfo->channels_max;
1177 	runtime->hw.formats = hinfo->formats;
1178 	runtime->hw.rates = hinfo->rates;
1179 
1180 	snd_pcm_hw_constraint_step(substream->runtime, 0,
1181 				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182 	return 0;
1183 }
1184 
1185 /*
1186  * HDA/HDMI auto parsing
1187  */
hdmi_read_pin_conn(struct hda_codec * codec,int pin_idx)1188 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1189 {
1190 	struct hdmi_spec *spec = codec->spec;
1191 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1192 	hda_nid_t pin_nid = per_pin->pin_nid;
1193 
1194 	if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1195 		codec_warn(codec,
1196 			   "HDMI: pin %d wcaps %#x does not support connection list\n",
1197 			   pin_nid, get_wcaps(codec, pin_nid));
1198 		return -EINVAL;
1199 	}
1200 
1201 	per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1202 							per_pin->mux_nids,
1203 							HDA_MAX_CONNECTIONS);
1204 
1205 	return 0;
1206 }
1207 
hdmi_find_pcm_slot(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin)1208 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1209 				struct hdmi_spec_per_pin *per_pin)
1210 {
1211 	int i;
1212 
1213 	/* try the prefer PCM */
1214 	if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1215 		return per_pin->pin_nid_idx;
1216 
1217 	/* have a second try; check the "reserved area" over num_pins */
1218 	for (i = spec->num_pins; i < spec->pcm_used; i++) {
1219 		if (!test_bit(i, &spec->pcm_bitmap))
1220 			return i;
1221 	}
1222 
1223 	/* the last try; check the empty slots in pins */
1224 	for (i = 0; i < spec->num_pins; i++) {
1225 		if (!test_bit(i, &spec->pcm_bitmap))
1226 			return i;
1227 	}
1228 	return -EBUSY;
1229 }
1230 
hdmi_attach_hda_pcm(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin)1231 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1232 				struct hdmi_spec_per_pin *per_pin)
1233 {
1234 	int idx;
1235 
1236 	/* pcm already be attached to the pin */
1237 	if (per_pin->pcm)
1238 		return;
1239 	idx = hdmi_find_pcm_slot(spec, per_pin);
1240 	if (idx == -EBUSY)
1241 		return;
1242 	per_pin->pcm_idx = idx;
1243 	per_pin->pcm = get_hdmi_pcm(spec, idx);
1244 	set_bit(idx, &spec->pcm_bitmap);
1245 }
1246 
hdmi_detach_hda_pcm(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin)1247 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1248 				struct hdmi_spec_per_pin *per_pin)
1249 {
1250 	int idx;
1251 
1252 	/* pcm already be detached from the pin */
1253 	if (!per_pin->pcm)
1254 		return;
1255 	idx = per_pin->pcm_idx;
1256 	per_pin->pcm_idx = -1;
1257 	per_pin->pcm = NULL;
1258 	if (idx >= 0 && idx < spec->pcm_used)
1259 		clear_bit(idx, &spec->pcm_bitmap);
1260 }
1261 
hdmi_get_pin_cvt_mux(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin,hda_nid_t cvt_nid)1262 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1263 		struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1264 {
1265 	int mux_idx;
1266 
1267 	for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1268 		if (per_pin->mux_nids[mux_idx] == cvt_nid)
1269 			break;
1270 	return mux_idx;
1271 }
1272 
1273 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1274 
hdmi_pcm_setup_pin(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin)1275 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1276 			   struct hdmi_spec_per_pin *per_pin)
1277 {
1278 	struct hda_codec *codec = per_pin->codec;
1279 	struct hda_pcm *pcm;
1280 	struct hda_pcm_stream *hinfo;
1281 	struct snd_pcm_substream *substream;
1282 	int mux_idx;
1283 	bool non_pcm;
1284 
1285 	if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1286 		pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1287 	else
1288 		return;
1289 	if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1290 		return;
1291 
1292 	/* hdmi audio only uses playback and one substream */
1293 	hinfo = pcm->stream;
1294 	substream = pcm->pcm->streams[0].substream;
1295 
1296 	per_pin->cvt_nid = hinfo->nid;
1297 
1298 	mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1299 	if (mux_idx < per_pin->num_mux_nids)
1300 		snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1301 				AC_VERB_SET_CONNECT_SEL,
1302 				mux_idx);
1303 	snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1304 
1305 	non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1306 	if (substream->runtime)
1307 		per_pin->channels = substream->runtime->channels;
1308 	per_pin->setup = true;
1309 	per_pin->mux_idx = mux_idx;
1310 
1311 	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1312 }
1313 
hdmi_pcm_reset_pin(struct hdmi_spec * spec,struct hdmi_spec_per_pin * per_pin)1314 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1315 			   struct hdmi_spec_per_pin *per_pin)
1316 {
1317 	if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1318 		snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1319 
1320 	per_pin->chmap_set = false;
1321 	memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1322 
1323 	per_pin->setup = false;
1324 	per_pin->channels = 0;
1325 }
1326 
1327 /* update per_pin ELD from the given new ELD;
1328  * setup info frame and notification accordingly
1329  */
update_eld(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,struct hdmi_eld * eld)1330 static void update_eld(struct hda_codec *codec,
1331 		       struct hdmi_spec_per_pin *per_pin,
1332 		       struct hdmi_eld *eld)
1333 {
1334 	struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1335 	struct hdmi_spec *spec = codec->spec;
1336 	bool old_eld_valid = pin_eld->eld_valid;
1337 	bool eld_changed;
1338 	int pcm_idx = -1;
1339 
1340 	/* for monitor disconnection, save pcm_idx firstly */
1341 	pcm_idx = per_pin->pcm_idx;
1342 	if (spec->dyn_pcm_assign) {
1343 		if (eld->eld_valid) {
1344 			hdmi_attach_hda_pcm(spec, per_pin);
1345 			hdmi_pcm_setup_pin(spec, per_pin);
1346 		} else {
1347 			hdmi_pcm_reset_pin(spec, per_pin);
1348 			hdmi_detach_hda_pcm(spec, per_pin);
1349 		}
1350 	}
1351 	/* if pcm_idx == -1, it means this is in monitor connection event
1352 	 * we can get the correct pcm_idx now.
1353 	 */
1354 	if (pcm_idx == -1)
1355 		pcm_idx = per_pin->pcm_idx;
1356 
1357 	if (eld->eld_valid)
1358 		snd_hdmi_show_eld(codec, &eld->info);
1359 
1360 	eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1361 	if (eld->eld_valid && pin_eld->eld_valid)
1362 		if (pin_eld->eld_size != eld->eld_size ||
1363 		    memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1364 			   eld->eld_size) != 0)
1365 			eld_changed = true;
1366 
1367 	pin_eld->monitor_present = eld->monitor_present;
1368 	pin_eld->eld_valid = eld->eld_valid;
1369 	pin_eld->eld_size = eld->eld_size;
1370 	if (eld->eld_valid)
1371 		memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1372 	pin_eld->info = eld->info;
1373 
1374 	/*
1375 	 * Re-setup pin and infoframe. This is needed e.g. when
1376 	 * - sink is first plugged-in
1377 	 * - transcoder can change during stream playback on Haswell
1378 	 *   and this can make HW reset converter selection on a pin.
1379 	 */
1380 	if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1381 		pin_cvt_fixup(codec, per_pin, 0);
1382 		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1383 	}
1384 
1385 	if (eld_changed && pcm_idx >= 0)
1386 		snd_ctl_notify(codec->card,
1387 			       SNDRV_CTL_EVENT_MASK_VALUE |
1388 			       SNDRV_CTL_EVENT_MASK_INFO,
1389 			       &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1390 }
1391 
1392 /* update ELD and jack state via HD-audio verbs */
hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin * per_pin,int repoll)1393 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1394 					 int repoll)
1395 {
1396 	struct hda_jack_tbl *jack;
1397 	struct hda_codec *codec = per_pin->codec;
1398 	struct hdmi_spec *spec = codec->spec;
1399 	struct hdmi_eld *eld = &spec->temp_eld;
1400 	hda_nid_t pin_nid = per_pin->pin_nid;
1401 	/*
1402 	 * Always execute a GetPinSense verb here, even when called from
1403 	 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1404 	 * response's PD bit is not the real PD value, but indicates that
1405 	 * the real PD value changed. An older version of the HD-audio
1406 	 * specification worked this way. Hence, we just ignore the data in
1407 	 * the unsolicited response to avoid custom WARs.
1408 	 */
1409 	int present;
1410 	bool ret;
1411 	bool do_repoll = false;
1412 
1413 	present = snd_hda_pin_sense(codec, pin_nid);
1414 
1415 	mutex_lock(&per_pin->lock);
1416 	eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1417 	if (eld->monitor_present)
1418 		eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1419 	else
1420 		eld->eld_valid = false;
1421 
1422 	codec_dbg(codec,
1423 		"HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1424 		codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1425 
1426 	if (eld->eld_valid) {
1427 		if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1428 						     &eld->eld_size) < 0)
1429 			eld->eld_valid = false;
1430 		else {
1431 			if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1432 						    eld->eld_size) < 0)
1433 				eld->eld_valid = false;
1434 		}
1435 		if (!eld->eld_valid && repoll)
1436 			do_repoll = true;
1437 	}
1438 
1439 	if (do_repoll)
1440 		schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1441 	else
1442 		update_eld(codec, per_pin, eld);
1443 
1444 	ret = !repoll || !eld->monitor_present || eld->eld_valid;
1445 
1446 	jack = snd_hda_jack_tbl_get(codec, pin_nid);
1447 	if (jack)
1448 		jack->block_report = !ret;
1449 
1450 	mutex_unlock(&per_pin->lock);
1451 	return ret;
1452 }
1453 
pin_idx_to_jack(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)1454 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1455 				 struct hdmi_spec_per_pin *per_pin)
1456 {
1457 	struct hdmi_spec *spec = codec->spec;
1458 	struct snd_jack *jack = NULL;
1459 	struct hda_jack_tbl *jack_tbl;
1460 
1461 	/* if !dyn_pcm_assign, get jack from hda_jack_tbl
1462 	 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1463 	 * NULL even after snd_hda_jack_tbl_clear() is called to
1464 	 * free snd_jack. This may cause access invalid memory
1465 	 * when calling snd_jack_report
1466 	 */
1467 	if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1468 		jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1469 	else if (!spec->dyn_pcm_assign) {
1470 		jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1471 		if (jack_tbl)
1472 			jack = jack_tbl->jack;
1473 	}
1474 	return jack;
1475 }
1476 
1477 /* update ELD and jack state via audio component */
sync_eld_via_acomp(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin)1478 static void sync_eld_via_acomp(struct hda_codec *codec,
1479 			       struct hdmi_spec_per_pin *per_pin)
1480 {
1481 	struct hdmi_spec *spec = codec->spec;
1482 	struct hdmi_eld *eld = &spec->temp_eld;
1483 	struct snd_jack *jack = NULL;
1484 	int size;
1485 
1486 	mutex_lock(&per_pin->lock);
1487 	eld->monitor_present = false;
1488 	size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1489 				      &eld->monitor_present, eld->eld_buffer,
1490 				      ELD_MAX_SIZE);
1491 	if (size > 0) {
1492 		size = min(size, ELD_MAX_SIZE);
1493 		if (snd_hdmi_parse_eld(codec, &eld->info,
1494 				       eld->eld_buffer, size) < 0)
1495 			size = -EINVAL;
1496 	}
1497 
1498 	if (size > 0) {
1499 		eld->eld_valid = true;
1500 		eld->eld_size = size;
1501 	} else {
1502 		eld->eld_valid = false;
1503 		eld->eld_size = 0;
1504 	}
1505 
1506 	/* pcm_idx >=0 before update_eld() means it is in monitor
1507 	 * disconnected event. Jack must be fetched before update_eld()
1508 	 */
1509 	jack = pin_idx_to_jack(codec, per_pin);
1510 	update_eld(codec, per_pin, eld);
1511 	if (jack == NULL)
1512 		jack = pin_idx_to_jack(codec, per_pin);
1513 	if (jack == NULL)
1514 		goto unlock;
1515 	snd_jack_report(jack,
1516 			eld->monitor_present ? SND_JACK_AVOUT : 0);
1517  unlock:
1518 	mutex_unlock(&per_pin->lock);
1519 }
1520 
hdmi_present_sense(struct hdmi_spec_per_pin * per_pin,int repoll)1521 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1522 {
1523 	struct hda_codec *codec = per_pin->codec;
1524 	struct hdmi_spec *spec = codec->spec;
1525 	int ret;
1526 
1527 	/* no temporary power up/down needed for component notifier */
1528 	if (!codec_has_acomp(codec))
1529 		snd_hda_power_up_pm(codec);
1530 
1531 	mutex_lock(&spec->pcm_lock);
1532 	if (codec_has_acomp(codec)) {
1533 		sync_eld_via_acomp(codec, per_pin);
1534 		ret = false; /* don't call snd_hda_jack_report_sync() */
1535 	} else {
1536 		ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1537 	}
1538 	mutex_unlock(&spec->pcm_lock);
1539 
1540 	if (!codec_has_acomp(codec))
1541 		snd_hda_power_down_pm(codec);
1542 
1543 	return ret;
1544 }
1545 
hdmi_repoll_eld(struct work_struct * work)1546 static void hdmi_repoll_eld(struct work_struct *work)
1547 {
1548 	struct hdmi_spec_per_pin *per_pin =
1549 	container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1550 
1551 	if (per_pin->repoll_count++ > 6)
1552 		per_pin->repoll_count = 0;
1553 
1554 	if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1555 		snd_hda_jack_report_sync(per_pin->codec);
1556 }
1557 
1558 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1559 					     hda_nid_t nid);
1560 
hdmi_add_pin(struct hda_codec * codec,hda_nid_t pin_nid)1561 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1562 {
1563 	struct hdmi_spec *spec = codec->spec;
1564 	unsigned int caps, config;
1565 	int pin_idx;
1566 	struct hdmi_spec_per_pin *per_pin;
1567 	int err;
1568 
1569 	caps = snd_hda_query_pin_caps(codec, pin_nid);
1570 	if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1571 		return 0;
1572 
1573 	config = snd_hda_codec_get_pincfg(codec, pin_nid);
1574 	if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1575 		return 0;
1576 
1577 	if (is_haswell_plus(codec))
1578 		intel_haswell_fixup_connect_list(codec, pin_nid);
1579 
1580 	pin_idx = spec->num_pins;
1581 	per_pin = snd_array_new(&spec->pins);
1582 	if (!per_pin)
1583 		return -ENOMEM;
1584 
1585 	per_pin->pin_nid = pin_nid;
1586 	per_pin->non_pcm = false;
1587 	if (spec->dyn_pcm_assign)
1588 		per_pin->pcm_idx = -1;
1589 	else {
1590 		per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1591 		per_pin->pcm_idx = pin_idx;
1592 	}
1593 	per_pin->pin_nid_idx = pin_idx;
1594 
1595 	err = hdmi_read_pin_conn(codec, pin_idx);
1596 	if (err < 0)
1597 		return err;
1598 
1599 	spec->num_pins++;
1600 
1601 	return 0;
1602 }
1603 
hdmi_add_cvt(struct hda_codec * codec,hda_nid_t cvt_nid)1604 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1605 {
1606 	struct hdmi_spec *spec = codec->spec;
1607 	struct hdmi_spec_per_cvt *per_cvt;
1608 	unsigned int chans;
1609 	int err;
1610 
1611 	chans = get_wcaps(codec, cvt_nid);
1612 	chans = get_wcaps_channels(chans);
1613 
1614 	per_cvt = snd_array_new(&spec->cvts);
1615 	if (!per_cvt)
1616 		return -ENOMEM;
1617 
1618 	per_cvt->cvt_nid = cvt_nid;
1619 	per_cvt->channels_min = 2;
1620 	if (chans <= 16) {
1621 		per_cvt->channels_max = chans;
1622 		if (chans > spec->chmap.channels_max)
1623 			spec->chmap.channels_max = chans;
1624 	}
1625 
1626 	err = snd_hda_query_supported_pcm(codec, cvt_nid,
1627 					  &per_cvt->rates,
1628 					  &per_cvt->formats,
1629 					  &per_cvt->maxbps);
1630 	if (err < 0)
1631 		return err;
1632 
1633 	if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1634 		spec->cvt_nids[spec->num_cvts] = cvt_nid;
1635 	spec->num_cvts++;
1636 
1637 	return 0;
1638 }
1639 
hdmi_parse_codec(struct hda_codec * codec)1640 static int hdmi_parse_codec(struct hda_codec *codec)
1641 {
1642 	hda_nid_t nid;
1643 	int i, nodes;
1644 
1645 	nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1646 	if (!nid || nodes < 0) {
1647 		codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1648 		return -EINVAL;
1649 	}
1650 
1651 	for (i = 0; i < nodes; i++, nid++) {
1652 		unsigned int caps;
1653 		unsigned int type;
1654 
1655 		caps = get_wcaps(codec, nid);
1656 		type = get_wcaps_type(caps);
1657 
1658 		if (!(caps & AC_WCAP_DIGITAL))
1659 			continue;
1660 
1661 		switch (type) {
1662 		case AC_WID_AUD_OUT:
1663 			hdmi_add_cvt(codec, nid);
1664 			break;
1665 		case AC_WID_PIN:
1666 			hdmi_add_pin(codec, nid);
1667 			break;
1668 		}
1669 	}
1670 
1671 	return 0;
1672 }
1673 
1674 /*
1675  */
check_non_pcm_per_cvt(struct hda_codec * codec,hda_nid_t cvt_nid)1676 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1677 {
1678 	struct hda_spdif_out *spdif;
1679 	bool non_pcm;
1680 
1681 	mutex_lock(&codec->spdif_mutex);
1682 	spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1683 	/* Add sanity check to pass klockwork check.
1684 	 * This should never happen.
1685 	 */
1686 	if (WARN_ON(spdif == NULL))
1687 		return true;
1688 	non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1689 	mutex_unlock(&codec->spdif_mutex);
1690 	return non_pcm;
1691 }
1692 
1693 /*
1694  * HDMI callbacks
1695  */
1696 
generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)1697 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1698 					   struct hda_codec *codec,
1699 					   unsigned int stream_tag,
1700 					   unsigned int format,
1701 					   struct snd_pcm_substream *substream)
1702 {
1703 	hda_nid_t cvt_nid = hinfo->nid;
1704 	struct hdmi_spec *spec = codec->spec;
1705 	int pin_idx;
1706 	struct hdmi_spec_per_pin *per_pin;
1707 	hda_nid_t pin_nid;
1708 	struct snd_pcm_runtime *runtime = substream->runtime;
1709 	bool non_pcm;
1710 	int pinctl;
1711 	int err;
1712 
1713 	mutex_lock(&spec->pcm_lock);
1714 	pin_idx = hinfo_to_pin_index(codec, hinfo);
1715 	if (spec->dyn_pcm_assign && pin_idx < 0) {
1716 		/* when dyn_pcm_assign and pcm is not bound to a pin
1717 		 * skip pin setup and return 0 to make audio playback
1718 		 * be ongoing
1719 		 */
1720 		pin_cvt_fixup(codec, NULL, cvt_nid);
1721 		snd_hda_codec_setup_stream(codec, cvt_nid,
1722 					stream_tag, 0, format);
1723 		mutex_unlock(&spec->pcm_lock);
1724 		return 0;
1725 	}
1726 
1727 	if (snd_BUG_ON(pin_idx < 0)) {
1728 		mutex_unlock(&spec->pcm_lock);
1729 		return -EINVAL;
1730 	}
1731 	per_pin = get_pin(spec, pin_idx);
1732 	pin_nid = per_pin->pin_nid;
1733 
1734 	/* Verify pin:cvt selections to avoid silent audio after S3.
1735 	 * After S3, the audio driver restores pin:cvt selections
1736 	 * but this can happen before gfx is ready and such selection
1737 	 * is overlooked by HW. Thus multiple pins can share a same
1738 	 * default convertor and mute control will affect each other,
1739 	 * which can cause a resumed audio playback become silent
1740 	 * after S3.
1741 	 */
1742 	pin_cvt_fixup(codec, per_pin, 0);
1743 
1744 	/* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1745 	/* Todo: add DP1.2 MST audio support later */
1746 	if (codec_has_acomp(codec))
1747 		snd_hdac_sync_audio_rate(&codec->core, pin_nid, runtime->rate);
1748 
1749 	non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1750 	mutex_lock(&per_pin->lock);
1751 	per_pin->channels = substream->runtime->channels;
1752 	per_pin->setup = true;
1753 
1754 	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1755 	mutex_unlock(&per_pin->lock);
1756 	if (spec->dyn_pin_out) {
1757 		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1758 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1759 		snd_hda_codec_write(codec, pin_nid, 0,
1760 				    AC_VERB_SET_PIN_WIDGET_CONTROL,
1761 				    pinctl | PIN_OUT);
1762 	}
1763 
1764 	err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1765 				 stream_tag, format);
1766 	mutex_unlock(&spec->pcm_lock);
1767 	return err;
1768 }
1769 
generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1770 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1771 					     struct hda_codec *codec,
1772 					     struct snd_pcm_substream *substream)
1773 {
1774 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1775 	return 0;
1776 }
1777 
hdmi_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)1778 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1779 			  struct hda_codec *codec,
1780 			  struct snd_pcm_substream *substream)
1781 {
1782 	struct hdmi_spec *spec = codec->spec;
1783 	int cvt_idx, pin_idx, pcm_idx;
1784 	struct hdmi_spec_per_cvt *per_cvt;
1785 	struct hdmi_spec_per_pin *per_pin;
1786 	int pinctl;
1787 
1788 	if (hinfo->nid) {
1789 		pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1790 		if (snd_BUG_ON(pcm_idx < 0))
1791 			return -EINVAL;
1792 		cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1793 		if (snd_BUG_ON(cvt_idx < 0))
1794 			return -EINVAL;
1795 		per_cvt = get_cvt(spec, cvt_idx);
1796 
1797 		snd_BUG_ON(!per_cvt->assigned);
1798 		per_cvt->assigned = 0;
1799 		hinfo->nid = 0;
1800 
1801 		mutex_lock(&spec->pcm_lock);
1802 		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1803 		clear_bit(pcm_idx, &spec->pcm_in_use);
1804 		pin_idx = hinfo_to_pin_index(codec, hinfo);
1805 		if (spec->dyn_pcm_assign && pin_idx < 0) {
1806 			mutex_unlock(&spec->pcm_lock);
1807 			return 0;
1808 		}
1809 
1810 		if (snd_BUG_ON(pin_idx < 0)) {
1811 			mutex_unlock(&spec->pcm_lock);
1812 			return -EINVAL;
1813 		}
1814 		per_pin = get_pin(spec, pin_idx);
1815 
1816 		if (spec->dyn_pin_out) {
1817 			pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1818 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1819 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1820 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
1821 					    pinctl & ~PIN_OUT);
1822 		}
1823 
1824 		mutex_lock(&per_pin->lock);
1825 		per_pin->chmap_set = false;
1826 		memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1827 
1828 		per_pin->setup = false;
1829 		per_pin->channels = 0;
1830 		mutex_unlock(&per_pin->lock);
1831 		mutex_unlock(&spec->pcm_lock);
1832 	}
1833 
1834 	return 0;
1835 }
1836 
1837 static const struct hda_pcm_ops generic_ops = {
1838 	.open = hdmi_pcm_open,
1839 	.close = hdmi_pcm_close,
1840 	.prepare = generic_hdmi_playback_pcm_prepare,
1841 	.cleanup = generic_hdmi_playback_pcm_cleanup,
1842 };
1843 
hdmi_get_spk_alloc(struct hdac_device * hdac,int pcm_idx)1844 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1845 {
1846 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1847 	struct hdmi_spec *spec = codec->spec;
1848 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1849 
1850 	if (!per_pin)
1851 		return 0;
1852 
1853 	return per_pin->sink_eld.info.spk_alloc;
1854 }
1855 
hdmi_get_chmap(struct hdac_device * hdac,int pcm_idx,unsigned char * chmap)1856 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1857 					unsigned char *chmap)
1858 {
1859 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1860 	struct hdmi_spec *spec = codec->spec;
1861 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1862 
1863 	/* chmap is already set to 0 in caller */
1864 	if (!per_pin)
1865 		return;
1866 
1867 	memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1868 }
1869 
hdmi_set_chmap(struct hdac_device * hdac,int pcm_idx,unsigned char * chmap,int prepared)1870 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1871 				unsigned char *chmap, int prepared)
1872 {
1873 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1874 	struct hdmi_spec *spec = codec->spec;
1875 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1876 
1877 	if (!per_pin)
1878 		return;
1879 	mutex_lock(&per_pin->lock);
1880 	per_pin->chmap_set = true;
1881 	memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1882 	if (prepared)
1883 		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1884 	mutex_unlock(&per_pin->lock);
1885 }
1886 
is_hdmi_pcm_attached(struct hdac_device * hdac,int pcm_idx)1887 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1888 {
1889 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1890 	struct hdmi_spec *spec = codec->spec;
1891 	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1892 
1893 	return per_pin ? true:false;
1894 }
1895 
generic_hdmi_build_pcms(struct hda_codec * codec)1896 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1897 {
1898 	struct hdmi_spec *spec = codec->spec;
1899 	int pin_idx;
1900 
1901 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1902 		struct hda_pcm *info;
1903 		struct hda_pcm_stream *pstr;
1904 
1905 		info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1906 		if (!info)
1907 			return -ENOMEM;
1908 
1909 		spec->pcm_rec[pin_idx].pcm = info;
1910 		spec->pcm_used++;
1911 		info->pcm_type = HDA_PCM_TYPE_HDMI;
1912 		info->own_chmap = true;
1913 
1914 		pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1915 		pstr->substreams = 1;
1916 		pstr->ops = generic_ops;
1917 		/* other pstr fields are set in open */
1918 	}
1919 
1920 	return 0;
1921 }
1922 
free_hdmi_jack_priv(struct snd_jack * jack)1923 static void free_hdmi_jack_priv(struct snd_jack *jack)
1924 {
1925 	struct hdmi_pcm *pcm = jack->private_data;
1926 
1927 	pcm->jack = NULL;
1928 }
1929 
add_hdmi_jack_kctl(struct hda_codec * codec,struct hdmi_spec * spec,int pcm_idx,const char * name)1930 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1931 			       struct hdmi_spec *spec,
1932 			       int pcm_idx,
1933 			       const char *name)
1934 {
1935 	struct snd_jack *jack;
1936 	int err;
1937 
1938 	err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1939 			   true, false);
1940 	if (err < 0)
1941 		return err;
1942 
1943 	spec->pcm_rec[pcm_idx].jack = jack;
1944 	jack->private_data = &spec->pcm_rec[pcm_idx];
1945 	jack->private_free = free_hdmi_jack_priv;
1946 	return 0;
1947 }
1948 
generic_hdmi_build_jack(struct hda_codec * codec,int pcm_idx)1949 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1950 {
1951 	char hdmi_str[32] = "HDMI/DP";
1952 	struct hdmi_spec *spec = codec->spec;
1953 	struct hdmi_spec_per_pin *per_pin;
1954 	struct hda_jack_tbl *jack;
1955 	int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1956 	bool phantom_jack;
1957 	int ret;
1958 
1959 	if (pcmdev > 0)
1960 		sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1961 
1962 	if (spec->dyn_pcm_assign)
1963 		return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1964 
1965 	/* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1966 	/* if !dyn_pcm_assign, it must be non-MST mode.
1967 	 * This means pcms and pins are statically mapped.
1968 	 * And pcm_idx is pin_idx.
1969 	 */
1970 	per_pin = get_pin(spec, pcm_idx);
1971 	phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1972 	if (phantom_jack)
1973 		strncat(hdmi_str, " Phantom",
1974 			sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1975 	ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1976 				    phantom_jack);
1977 	if (ret < 0)
1978 		return ret;
1979 	jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1980 	if (jack == NULL)
1981 		return 0;
1982 	/* assign jack->jack to pcm_rec[].jack to
1983 	 * align with dyn_pcm_assign mode
1984 	 */
1985 	spec->pcm_rec[pcm_idx].jack = jack->jack;
1986 	return 0;
1987 }
1988 
generic_hdmi_build_controls(struct hda_codec * codec)1989 static int generic_hdmi_build_controls(struct hda_codec *codec)
1990 {
1991 	struct hdmi_spec *spec = codec->spec;
1992 	int err;
1993 	int pin_idx, pcm_idx;
1994 
1995 
1996 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1997 		err = generic_hdmi_build_jack(codec, pcm_idx);
1998 		if (err < 0)
1999 			return err;
2000 
2001 		/* create the spdif for each pcm
2002 		 * pin will be bound when monitor is connected
2003 		 */
2004 		if (spec->dyn_pcm_assign)
2005 			err = snd_hda_create_dig_out_ctls(codec,
2006 					  0, spec->cvt_nids[0],
2007 					  HDA_PCM_TYPE_HDMI);
2008 		else {
2009 			struct hdmi_spec_per_pin *per_pin =
2010 				get_pin(spec, pcm_idx);
2011 			err = snd_hda_create_dig_out_ctls(codec,
2012 						  per_pin->pin_nid,
2013 						  per_pin->mux_nids[0],
2014 						  HDA_PCM_TYPE_HDMI);
2015 		}
2016 		if (err < 0)
2017 			return err;
2018 		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2019 
2020 		/* add control for ELD Bytes */
2021 		err = hdmi_create_eld_ctl(codec, pcm_idx,
2022 					get_pcm_rec(spec, pcm_idx)->device);
2023 		if (err < 0)
2024 			return err;
2025 	}
2026 
2027 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2028 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2029 
2030 		hdmi_present_sense(per_pin, 0);
2031 	}
2032 
2033 	/* add channel maps */
2034 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2035 		struct hda_pcm *pcm;
2036 
2037 		pcm = get_pcm_rec(spec, pcm_idx);
2038 		if (!pcm || !pcm->pcm)
2039 			break;
2040 		err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2041 		if (err < 0)
2042 			return err;
2043 	}
2044 
2045 	return 0;
2046 }
2047 
generic_hdmi_init_per_pins(struct hda_codec * codec)2048 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2049 {
2050 	struct hdmi_spec *spec = codec->spec;
2051 	int pin_idx;
2052 
2053 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2054 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2055 
2056 		per_pin->codec = codec;
2057 		mutex_init(&per_pin->lock);
2058 		INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2059 		eld_proc_new(per_pin, pin_idx);
2060 	}
2061 	return 0;
2062 }
2063 
generic_hdmi_init(struct hda_codec * codec)2064 static int generic_hdmi_init(struct hda_codec *codec)
2065 {
2066 	struct hdmi_spec *spec = codec->spec;
2067 	int pin_idx;
2068 
2069 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2070 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2071 		hda_nid_t pin_nid = per_pin->pin_nid;
2072 
2073 		hdmi_init_pin(codec, pin_nid);
2074 		if (!codec_has_acomp(codec))
2075 			snd_hda_jack_detect_enable_callback(codec, pin_nid,
2076 				codec->jackpoll_interval > 0 ?
2077 				jack_callback : NULL);
2078 	}
2079 	return 0;
2080 }
2081 
hdmi_array_init(struct hdmi_spec * spec,int nums)2082 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2083 {
2084 	snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2085 	snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2086 }
2087 
hdmi_array_free(struct hdmi_spec * spec)2088 static void hdmi_array_free(struct hdmi_spec *spec)
2089 {
2090 	snd_array_free(&spec->pins);
2091 	snd_array_free(&spec->cvts);
2092 }
2093 
generic_spec_free(struct hda_codec * codec)2094 static void generic_spec_free(struct hda_codec *codec)
2095 {
2096 	struct hdmi_spec *spec = codec->spec;
2097 
2098 	if (spec) {
2099 		if (spec->i915_bound)
2100 			snd_hdac_i915_exit(&codec->bus->core);
2101 		hdmi_array_free(spec);
2102 		kfree(spec);
2103 		codec->spec = NULL;
2104 	}
2105 	codec->dp_mst = false;
2106 }
2107 
generic_hdmi_free(struct hda_codec * codec)2108 static void generic_hdmi_free(struct hda_codec *codec)
2109 {
2110 	struct hdmi_spec *spec = codec->spec;
2111 	int pin_idx, pcm_idx;
2112 
2113 	if (codec_has_acomp(codec))
2114 		snd_hdac_i915_register_notifier(NULL);
2115 
2116 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2117 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2118 		cancel_delayed_work_sync(&per_pin->work);
2119 		eld_proc_free(per_pin);
2120 	}
2121 
2122 	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2123 		if (spec->pcm_rec[pcm_idx].jack == NULL)
2124 			continue;
2125 		if (spec->dyn_pcm_assign)
2126 			snd_device_free(codec->card,
2127 					spec->pcm_rec[pcm_idx].jack);
2128 		else
2129 			spec->pcm_rec[pcm_idx].jack = NULL;
2130 	}
2131 
2132 	generic_spec_free(codec);
2133 }
2134 
2135 #ifdef CONFIG_PM
generic_hdmi_resume(struct hda_codec * codec)2136 static int generic_hdmi_resume(struct hda_codec *codec)
2137 {
2138 	struct hdmi_spec *spec = codec->spec;
2139 	int pin_idx;
2140 
2141 	codec->patch_ops.init(codec);
2142 	regcache_sync(codec->core.regmap);
2143 
2144 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2145 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2146 		hdmi_present_sense(per_pin, 1);
2147 	}
2148 	return 0;
2149 }
2150 #endif
2151 
2152 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2153 	.init			= generic_hdmi_init,
2154 	.free			= generic_hdmi_free,
2155 	.build_pcms		= generic_hdmi_build_pcms,
2156 	.build_controls		= generic_hdmi_build_controls,
2157 	.unsol_event		= hdmi_unsol_event,
2158 #ifdef CONFIG_PM
2159 	.resume			= generic_hdmi_resume,
2160 #endif
2161 };
2162 
2163 static const struct hdmi_ops generic_standard_hdmi_ops = {
2164 	.pin_get_eld				= snd_hdmi_get_eld,
2165 	.pin_setup_infoframe			= hdmi_pin_setup_infoframe,
2166 	.pin_hbr_setup				= hdmi_pin_hbr_setup,
2167 	.setup_stream				= hdmi_setup_stream,
2168 };
2169 
2170 /* allocate codec->spec and assign/initialize generic parser ops */
alloc_generic_hdmi(struct hda_codec * codec)2171 static int alloc_generic_hdmi(struct hda_codec *codec)
2172 {
2173 	struct hdmi_spec *spec;
2174 
2175 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2176 	if (!spec)
2177 		return -ENOMEM;
2178 
2179 	spec->ops = generic_standard_hdmi_ops;
2180 	mutex_init(&spec->pcm_lock);
2181 	snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2182 
2183 	spec->chmap.ops.get_chmap = hdmi_get_chmap;
2184 	spec->chmap.ops.set_chmap = hdmi_set_chmap;
2185 	spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2186 	spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2187 
2188 	codec->spec = spec;
2189 	hdmi_array_init(spec, 4);
2190 
2191 	codec->patch_ops = generic_hdmi_patch_ops;
2192 
2193 	return 0;
2194 }
2195 
2196 /* generic HDMI parser */
patch_generic_hdmi(struct hda_codec * codec)2197 static int patch_generic_hdmi(struct hda_codec *codec)
2198 {
2199 	int err;
2200 
2201 	err = alloc_generic_hdmi(codec);
2202 	if (err < 0)
2203 		return err;
2204 
2205 	err = hdmi_parse_codec(codec);
2206 	if (err < 0) {
2207 		generic_spec_free(codec);
2208 		return err;
2209 	}
2210 
2211 	generic_hdmi_init_per_pins(codec);
2212 	return 0;
2213 }
2214 
2215 /*
2216  * Intel codec parsers and helpers
2217  */
2218 
intel_haswell_fixup_connect_list(struct hda_codec * codec,hda_nid_t nid)2219 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2220 					     hda_nid_t nid)
2221 {
2222 	struct hdmi_spec *spec = codec->spec;
2223 	hda_nid_t conns[4];
2224 	int nconns;
2225 
2226 	nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2227 	if (nconns == spec->num_cvts &&
2228 	    !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2229 		return;
2230 
2231 	/* override pins connection list */
2232 	codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2233 	snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2234 }
2235 
2236 #define INTEL_VENDOR_NID 0x08
2237 #define INTEL_GET_VENDOR_VERB 0xf81
2238 #define INTEL_SET_VENDOR_VERB 0x781
2239 #define INTEL_EN_DP12			0x02 /* enable DP 1.2 features */
2240 #define INTEL_EN_ALL_PIN_CVTS	0x01 /* enable 2nd & 3rd pins and convertors */
2241 
intel_haswell_enable_all_pins(struct hda_codec * codec,bool update_tree)2242 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2243 					  bool update_tree)
2244 {
2245 	unsigned int vendor_param;
2246 
2247 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2248 				INTEL_GET_VENDOR_VERB, 0);
2249 	if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2250 		return;
2251 
2252 	vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2253 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2254 				INTEL_SET_VENDOR_VERB, vendor_param);
2255 	if (vendor_param == -1)
2256 		return;
2257 
2258 	if (update_tree)
2259 		snd_hda_codec_update_widgets(codec);
2260 }
2261 
intel_haswell_fixup_enable_dp12(struct hda_codec * codec)2262 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2263 {
2264 	unsigned int vendor_param;
2265 
2266 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2267 				INTEL_GET_VENDOR_VERB, 0);
2268 	if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2269 		return;
2270 
2271 	/* enable DP1.2 mode */
2272 	vendor_param |= INTEL_EN_DP12;
2273 	snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2274 	snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2275 				INTEL_SET_VENDOR_VERB, vendor_param);
2276 }
2277 
2278 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2279  * Otherwise you may get severe h/w communication errors.
2280  */
haswell_set_power_state(struct hda_codec * codec,hda_nid_t fg,unsigned int power_state)2281 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2282 				unsigned int power_state)
2283 {
2284 	if (power_state == AC_PWRST_D0) {
2285 		intel_haswell_enable_all_pins(codec, false);
2286 		intel_haswell_fixup_enable_dp12(codec);
2287 	}
2288 
2289 	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2290 	snd_hda_codec_set_power_to_all(codec, fg, power_state);
2291 }
2292 
intel_pin_eld_notify(void * audio_ptr,int port)2293 static void intel_pin_eld_notify(void *audio_ptr, int port)
2294 {
2295 	struct hda_codec *codec = audio_ptr;
2296 	int pin_nid;
2297 
2298 	/* we assume only from port-B to port-D */
2299 	if (port < 1 || port > 3)
2300 		return;
2301 
2302 	switch (codec->core.vendor_id) {
2303 	case 0x80860054: /* ILK */
2304 	case 0x80862804: /* ILK */
2305 	case 0x80862882: /* VLV */
2306 		pin_nid = port + 0x03;
2307 		break;
2308 	default:
2309 		pin_nid = port + 0x04;
2310 		break;
2311 	}
2312 
2313 	/* skip notification during system suspend (but not in runtime PM);
2314 	 * the state will be updated at resume
2315 	 */
2316 	if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2317 		return;
2318 	/* ditto during suspend/resume process itself */
2319 	if (atomic_read(&(codec)->core.in_pm))
2320 		return;
2321 
2322 	snd_hdac_i915_set_bclk(&codec->bus->core);
2323 	check_presence_and_report(codec, pin_nid);
2324 }
2325 
2326 /* register i915 component pin_eld_notify callback */
register_i915_notifier(struct hda_codec * codec)2327 static void register_i915_notifier(struct hda_codec *codec)
2328 {
2329 	struct hdmi_spec *spec = codec->spec;
2330 
2331 	spec->use_acomp_notifier = true;
2332 	spec->i915_audio_ops.audio_ptr = codec;
2333 	/* intel_audio_codec_enable() or intel_audio_codec_disable()
2334 	 * will call pin_eld_notify with using audio_ptr pointer
2335 	 * We need make sure audio_ptr is really setup
2336 	 */
2337 	wmb();
2338 	spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2339 	snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2340 }
2341 
2342 /* setup_stream ops override for HSW+ */
i915_hsw_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,u32 stream_tag,int format)2343 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2344 				 hda_nid_t pin_nid, u32 stream_tag, int format)
2345 {
2346 	haswell_verify_D0(codec, cvt_nid, pin_nid);
2347 	return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2348 }
2349 
2350 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
i915_pin_cvt_fixup(struct hda_codec * codec,struct hdmi_spec_per_pin * per_pin,hda_nid_t cvt_nid)2351 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2352 			       struct hdmi_spec_per_pin *per_pin,
2353 			       hda_nid_t cvt_nid)
2354 {
2355 	if (per_pin) {
2356 		intel_verify_pin_cvt_connect(codec, per_pin);
2357 		intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2358 					     per_pin->mux_idx);
2359 	} else {
2360 		intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
2361 	}
2362 }
2363 
2364 /* Intel Haswell and onwards; audio component with eld notifier */
patch_i915_hsw_hdmi(struct hda_codec * codec)2365 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2366 {
2367 	struct hdmi_spec *spec;
2368 	int err;
2369 
2370 	/* HSW+ requires i915 binding */
2371 	if (!codec->bus->core.audio_component) {
2372 		codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2373 		return -ENODEV;
2374 	}
2375 
2376 	err = alloc_generic_hdmi(codec);
2377 	if (err < 0)
2378 		return err;
2379 	spec = codec->spec;
2380 
2381 	intel_haswell_enable_all_pins(codec, true);
2382 	intel_haswell_fixup_enable_dp12(codec);
2383 
2384 	/* For Haswell/Broadwell, the controller is also in the power well and
2385 	 * can cover the codec power request, and so need not set this flag.
2386 	 */
2387 	if (!is_haswell(codec) && !is_broadwell(codec))
2388 		codec->core.link_power_control = 1;
2389 
2390 	codec->patch_ops.set_power_state = haswell_set_power_state;
2391 	codec->dp_mst = true;
2392 	codec->depop_delay = 0;
2393 	codec->auto_runtime_pm = 1;
2394 
2395 	spec->ops.setup_stream = i915_hsw_setup_stream;
2396 	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2397 
2398 	err = hdmi_parse_codec(codec);
2399 	if (err < 0) {
2400 		generic_spec_free(codec);
2401 		return err;
2402 	}
2403 
2404 	generic_hdmi_init_per_pins(codec);
2405 	register_i915_notifier(codec);
2406 	return 0;
2407 }
2408 
2409 /* Intel Baytrail and Braswell; with eld notifier */
patch_i915_byt_hdmi(struct hda_codec * codec)2410 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2411 {
2412 	struct hdmi_spec *spec;
2413 	int err;
2414 
2415 	/* requires i915 binding */
2416 	if (!codec->bus->core.audio_component) {
2417 		codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2418 		return -ENODEV;
2419 	}
2420 
2421 	err = alloc_generic_hdmi(codec);
2422 	if (err < 0)
2423 		return err;
2424 	spec = codec->spec;
2425 
2426 	/* For Valleyview/Cherryview, only the display codec is in the display
2427 	 * power well and can use link_power ops to request/release the power.
2428 	 */
2429 	codec->core.link_power_control = 1;
2430 
2431 	codec->depop_delay = 0;
2432 	codec->auto_runtime_pm = 1;
2433 
2434 	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2435 
2436 	err = hdmi_parse_codec(codec);
2437 	if (err < 0) {
2438 		generic_spec_free(codec);
2439 		return err;
2440 	}
2441 
2442 	generic_hdmi_init_per_pins(codec);
2443 	register_i915_notifier(codec);
2444 	return 0;
2445 }
2446 
2447 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
patch_i915_cpt_hdmi(struct hda_codec * codec)2448 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2449 {
2450 	struct hdmi_spec *spec;
2451 	int err;
2452 
2453 	/* no i915 component should have been bound before this */
2454 	if (WARN_ON(codec->bus->core.audio_component))
2455 		return -EBUSY;
2456 
2457 	err = alloc_generic_hdmi(codec);
2458 	if (err < 0)
2459 		return err;
2460 	spec = codec->spec;
2461 
2462 	/* Try to bind with i915 now */
2463 	err = snd_hdac_i915_init(&codec->bus->core);
2464 	if (err < 0)
2465 		goto error;
2466 	spec->i915_bound = true;
2467 
2468 	err = hdmi_parse_codec(codec);
2469 	if (err < 0)
2470 		goto error;
2471 
2472 	generic_hdmi_init_per_pins(codec);
2473 	register_i915_notifier(codec);
2474 	return 0;
2475 
2476  error:
2477 	generic_spec_free(codec);
2478 	return err;
2479 }
2480 
2481 /*
2482  * Shared non-generic implementations
2483  */
2484 
simple_playback_build_pcms(struct hda_codec * codec)2485 static int simple_playback_build_pcms(struct hda_codec *codec)
2486 {
2487 	struct hdmi_spec *spec = codec->spec;
2488 	struct hda_pcm *info;
2489 	unsigned int chans;
2490 	struct hda_pcm_stream *pstr;
2491 	struct hdmi_spec_per_cvt *per_cvt;
2492 
2493 	per_cvt = get_cvt(spec, 0);
2494 	chans = get_wcaps(codec, per_cvt->cvt_nid);
2495 	chans = get_wcaps_channels(chans);
2496 
2497 	info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2498 	if (!info)
2499 		return -ENOMEM;
2500 	spec->pcm_rec[0].pcm = info;
2501 	info->pcm_type = HDA_PCM_TYPE_HDMI;
2502 	pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2503 	*pstr = spec->pcm_playback;
2504 	pstr->nid = per_cvt->cvt_nid;
2505 	if (pstr->channels_max <= 2 && chans && chans <= 16)
2506 		pstr->channels_max = chans;
2507 
2508 	return 0;
2509 }
2510 
2511 /* unsolicited event for jack sensing */
simple_hdmi_unsol_event(struct hda_codec * codec,unsigned int res)2512 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2513 				    unsigned int res)
2514 {
2515 	snd_hda_jack_set_dirty_all(codec);
2516 	snd_hda_jack_report_sync(codec);
2517 }
2518 
2519 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2520  * as long as spec->pins[] is set correctly
2521  */
2522 #define simple_hdmi_build_jack	generic_hdmi_build_jack
2523 
simple_playback_build_controls(struct hda_codec * codec)2524 static int simple_playback_build_controls(struct hda_codec *codec)
2525 {
2526 	struct hdmi_spec *spec = codec->spec;
2527 	struct hdmi_spec_per_cvt *per_cvt;
2528 	int err;
2529 
2530 	per_cvt = get_cvt(spec, 0);
2531 	err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2532 					  per_cvt->cvt_nid,
2533 					  HDA_PCM_TYPE_HDMI);
2534 	if (err < 0)
2535 		return err;
2536 	return simple_hdmi_build_jack(codec, 0);
2537 }
2538 
simple_playback_init(struct hda_codec * codec)2539 static int simple_playback_init(struct hda_codec *codec)
2540 {
2541 	struct hdmi_spec *spec = codec->spec;
2542 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2543 	hda_nid_t pin = per_pin->pin_nid;
2544 
2545 	snd_hda_codec_write(codec, pin, 0,
2546 			    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2547 	/* some codecs require to unmute the pin */
2548 	if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2549 		snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2550 				    AMP_OUT_UNMUTE);
2551 	snd_hda_jack_detect_enable(codec, pin);
2552 	return 0;
2553 }
2554 
simple_playback_free(struct hda_codec * codec)2555 static void simple_playback_free(struct hda_codec *codec)
2556 {
2557 	struct hdmi_spec *spec = codec->spec;
2558 
2559 	hdmi_array_free(spec);
2560 	kfree(spec);
2561 }
2562 
2563 /*
2564  * Nvidia specific implementations
2565  */
2566 
2567 #define Nv_VERB_SET_Channel_Allocation          0xF79
2568 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2569 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2570 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2571 
2572 #define nvhdmi_master_con_nid_7x	0x04
2573 #define nvhdmi_master_pin_nid_7x	0x05
2574 
2575 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2576 	/*front, rear, clfe, rear_surr */
2577 	0x6, 0x8, 0xa, 0xc,
2578 };
2579 
2580 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2581 	/* set audio protect on */
2582 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2583 	/* enable digital output on pin widget */
2584 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2585 	{} /* terminator */
2586 };
2587 
2588 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2589 	/* set audio protect on */
2590 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2591 	/* enable digital output on pin widget */
2592 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2593 	{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2594 	{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2595 	{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2596 	{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2597 	{} /* terminator */
2598 };
2599 
2600 #ifdef LIMITED_RATE_FMT_SUPPORT
2601 /* support only the safe format and rate */
2602 #define SUPPORTED_RATES		SNDRV_PCM_RATE_48000
2603 #define SUPPORTED_MAXBPS	16
2604 #define SUPPORTED_FORMATS	SNDRV_PCM_FMTBIT_S16_LE
2605 #else
2606 /* support all rates and formats */
2607 #define SUPPORTED_RATES \
2608 	(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2609 	SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2610 	 SNDRV_PCM_RATE_192000)
2611 #define SUPPORTED_MAXBPS	24
2612 #define SUPPORTED_FORMATS \
2613 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2614 #endif
2615 
nvhdmi_7x_init_2ch(struct hda_codec * codec)2616 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2617 {
2618 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2619 	return 0;
2620 }
2621 
nvhdmi_7x_init_8ch(struct hda_codec * codec)2622 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2623 {
2624 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2625 	return 0;
2626 }
2627 
2628 static unsigned int channels_2_6_8[] = {
2629 	2, 6, 8
2630 };
2631 
2632 static unsigned int channels_2_8[] = {
2633 	2, 8
2634 };
2635 
2636 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2637 	.count = ARRAY_SIZE(channels_2_6_8),
2638 	.list = channels_2_6_8,
2639 	.mask = 0,
2640 };
2641 
2642 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2643 	.count = ARRAY_SIZE(channels_2_8),
2644 	.list = channels_2_8,
2645 	.mask = 0,
2646 };
2647 
simple_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2648 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2649 				    struct hda_codec *codec,
2650 				    struct snd_pcm_substream *substream)
2651 {
2652 	struct hdmi_spec *spec = codec->spec;
2653 	struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2654 
2655 	switch (codec->preset->vendor_id) {
2656 	case 0x10de0002:
2657 	case 0x10de0003:
2658 	case 0x10de0005:
2659 	case 0x10de0006:
2660 		hw_constraints_channels = &hw_constraints_2_8_channels;
2661 		break;
2662 	case 0x10de0007:
2663 		hw_constraints_channels = &hw_constraints_2_6_8_channels;
2664 		break;
2665 	default:
2666 		break;
2667 	}
2668 
2669 	if (hw_constraints_channels != NULL) {
2670 		snd_pcm_hw_constraint_list(substream->runtime, 0,
2671 				SNDRV_PCM_HW_PARAM_CHANNELS,
2672 				hw_constraints_channels);
2673 	} else {
2674 		snd_pcm_hw_constraint_step(substream->runtime, 0,
2675 					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2676 	}
2677 
2678 	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2679 }
2680 
simple_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2681 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2682 				     struct hda_codec *codec,
2683 				     struct snd_pcm_substream *substream)
2684 {
2685 	struct hdmi_spec *spec = codec->spec;
2686 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2687 }
2688 
simple_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)2689 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2690 				       struct hda_codec *codec,
2691 				       unsigned int stream_tag,
2692 				       unsigned int format,
2693 				       struct snd_pcm_substream *substream)
2694 {
2695 	struct hdmi_spec *spec = codec->spec;
2696 	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2697 					     stream_tag, format, substream);
2698 }
2699 
2700 static const struct hda_pcm_stream simple_pcm_playback = {
2701 	.substreams = 1,
2702 	.channels_min = 2,
2703 	.channels_max = 2,
2704 	.ops = {
2705 		.open = simple_playback_pcm_open,
2706 		.close = simple_playback_pcm_close,
2707 		.prepare = simple_playback_pcm_prepare
2708 	},
2709 };
2710 
2711 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2712 	.build_controls = simple_playback_build_controls,
2713 	.build_pcms = simple_playback_build_pcms,
2714 	.init = simple_playback_init,
2715 	.free = simple_playback_free,
2716 	.unsol_event = simple_hdmi_unsol_event,
2717 };
2718 
patch_simple_hdmi(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid)2719 static int patch_simple_hdmi(struct hda_codec *codec,
2720 			     hda_nid_t cvt_nid, hda_nid_t pin_nid)
2721 {
2722 	struct hdmi_spec *spec;
2723 	struct hdmi_spec_per_cvt *per_cvt;
2724 	struct hdmi_spec_per_pin *per_pin;
2725 
2726 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2727 	if (!spec)
2728 		return -ENOMEM;
2729 
2730 	codec->spec = spec;
2731 	hdmi_array_init(spec, 1);
2732 
2733 	spec->multiout.num_dacs = 0;  /* no analog */
2734 	spec->multiout.max_channels = 2;
2735 	spec->multiout.dig_out_nid = cvt_nid;
2736 	spec->num_cvts = 1;
2737 	spec->num_pins = 1;
2738 	per_pin = snd_array_new(&spec->pins);
2739 	per_cvt = snd_array_new(&spec->cvts);
2740 	if (!per_pin || !per_cvt) {
2741 		simple_playback_free(codec);
2742 		return -ENOMEM;
2743 	}
2744 	per_cvt->cvt_nid = cvt_nid;
2745 	per_pin->pin_nid = pin_nid;
2746 	spec->pcm_playback = simple_pcm_playback;
2747 
2748 	codec->patch_ops = simple_hdmi_patch_ops;
2749 
2750 	return 0;
2751 }
2752 
nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec * codec,int channels)2753 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2754 						    int channels)
2755 {
2756 	unsigned int chanmask;
2757 	int chan = channels ? (channels - 1) : 1;
2758 
2759 	switch (channels) {
2760 	default:
2761 	case 0:
2762 	case 2:
2763 		chanmask = 0x00;
2764 		break;
2765 	case 4:
2766 		chanmask = 0x08;
2767 		break;
2768 	case 6:
2769 		chanmask = 0x0b;
2770 		break;
2771 	case 8:
2772 		chanmask = 0x13;
2773 		break;
2774 	}
2775 
2776 	/* Set the audio infoframe channel allocation and checksum fields.  The
2777 	 * channel count is computed implicitly by the hardware. */
2778 	snd_hda_codec_write(codec, 0x1, 0,
2779 			Nv_VERB_SET_Channel_Allocation, chanmask);
2780 
2781 	snd_hda_codec_write(codec, 0x1, 0,
2782 			Nv_VERB_SET_Info_Frame_Checksum,
2783 			(0x71 - chan - chanmask));
2784 }
2785 
nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)2786 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2787 				   struct hda_codec *codec,
2788 				   struct snd_pcm_substream *substream)
2789 {
2790 	struct hdmi_spec *spec = codec->spec;
2791 	int i;
2792 
2793 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2794 			0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2795 	for (i = 0; i < 4; i++) {
2796 		/* set the stream id */
2797 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2798 				AC_VERB_SET_CHANNEL_STREAMID, 0);
2799 		/* set the stream format */
2800 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2801 				AC_VERB_SET_STREAM_FORMAT, 0);
2802 	}
2803 
2804 	/* The audio hardware sends a channel count of 0x7 (8ch) when all the
2805 	 * streams are disabled. */
2806 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2807 
2808 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2809 }
2810 
nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)2811 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2812 				     struct hda_codec *codec,
2813 				     unsigned int stream_tag,
2814 				     unsigned int format,
2815 				     struct snd_pcm_substream *substream)
2816 {
2817 	int chs;
2818 	unsigned int dataDCC2, channel_id;
2819 	int i;
2820 	struct hdmi_spec *spec = codec->spec;
2821 	struct hda_spdif_out *spdif;
2822 	struct hdmi_spec_per_cvt *per_cvt;
2823 
2824 	mutex_lock(&codec->spdif_mutex);
2825 	per_cvt = get_cvt(spec, 0);
2826 	spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2827 
2828 	chs = substream->runtime->channels;
2829 
2830 	dataDCC2 = 0x2;
2831 
2832 	/* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2833 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2834 		snd_hda_codec_write(codec,
2835 				nvhdmi_master_con_nid_7x,
2836 				0,
2837 				AC_VERB_SET_DIGI_CONVERT_1,
2838 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2839 
2840 	/* set the stream id */
2841 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2842 			AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2843 
2844 	/* set the stream format */
2845 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2846 			AC_VERB_SET_STREAM_FORMAT, format);
2847 
2848 	/* turn on again (if needed) */
2849 	/* enable and set the channel status audio/data flag */
2850 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2851 		snd_hda_codec_write(codec,
2852 				nvhdmi_master_con_nid_7x,
2853 				0,
2854 				AC_VERB_SET_DIGI_CONVERT_1,
2855 				spdif->ctls & 0xff);
2856 		snd_hda_codec_write(codec,
2857 				nvhdmi_master_con_nid_7x,
2858 				0,
2859 				AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2860 	}
2861 
2862 	for (i = 0; i < 4; i++) {
2863 		if (chs == 2)
2864 			channel_id = 0;
2865 		else
2866 			channel_id = i * 2;
2867 
2868 		/* turn off SPDIF once;
2869 		 *otherwise the IEC958 bits won't be updated
2870 		 */
2871 		if (codec->spdif_status_reset &&
2872 		(spdif->ctls & AC_DIG1_ENABLE))
2873 			snd_hda_codec_write(codec,
2874 				nvhdmi_con_nids_7x[i],
2875 				0,
2876 				AC_VERB_SET_DIGI_CONVERT_1,
2877 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2878 		/* set the stream id */
2879 		snd_hda_codec_write(codec,
2880 				nvhdmi_con_nids_7x[i],
2881 				0,
2882 				AC_VERB_SET_CHANNEL_STREAMID,
2883 				(stream_tag << 4) | channel_id);
2884 		/* set the stream format */
2885 		snd_hda_codec_write(codec,
2886 				nvhdmi_con_nids_7x[i],
2887 				0,
2888 				AC_VERB_SET_STREAM_FORMAT,
2889 				format);
2890 		/* turn on again (if needed) */
2891 		/* enable and set the channel status audio/data flag */
2892 		if (codec->spdif_status_reset &&
2893 		(spdif->ctls & AC_DIG1_ENABLE)) {
2894 			snd_hda_codec_write(codec,
2895 					nvhdmi_con_nids_7x[i],
2896 					0,
2897 					AC_VERB_SET_DIGI_CONVERT_1,
2898 					spdif->ctls & 0xff);
2899 			snd_hda_codec_write(codec,
2900 					nvhdmi_con_nids_7x[i],
2901 					0,
2902 					AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2903 		}
2904 	}
2905 
2906 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2907 
2908 	mutex_unlock(&codec->spdif_mutex);
2909 	return 0;
2910 }
2911 
2912 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2913 	.substreams = 1,
2914 	.channels_min = 2,
2915 	.channels_max = 8,
2916 	.nid = nvhdmi_master_con_nid_7x,
2917 	.rates = SUPPORTED_RATES,
2918 	.maxbps = SUPPORTED_MAXBPS,
2919 	.formats = SUPPORTED_FORMATS,
2920 	.ops = {
2921 		.open = simple_playback_pcm_open,
2922 		.close = nvhdmi_8ch_7x_pcm_close,
2923 		.prepare = nvhdmi_8ch_7x_pcm_prepare
2924 	},
2925 };
2926 
patch_nvhdmi_2ch(struct hda_codec * codec)2927 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2928 {
2929 	struct hdmi_spec *spec;
2930 	int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2931 				    nvhdmi_master_pin_nid_7x);
2932 	if (err < 0)
2933 		return err;
2934 
2935 	codec->patch_ops.init = nvhdmi_7x_init_2ch;
2936 	/* override the PCM rates, etc, as the codec doesn't give full list */
2937 	spec = codec->spec;
2938 	spec->pcm_playback.rates = SUPPORTED_RATES;
2939 	spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2940 	spec->pcm_playback.formats = SUPPORTED_FORMATS;
2941 	return 0;
2942 }
2943 
nvhdmi_7x_8ch_build_pcms(struct hda_codec * codec)2944 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2945 {
2946 	struct hdmi_spec *spec = codec->spec;
2947 	int err = simple_playback_build_pcms(codec);
2948 	if (!err) {
2949 		struct hda_pcm *info = get_pcm_rec(spec, 0);
2950 		info->own_chmap = true;
2951 	}
2952 	return err;
2953 }
2954 
nvhdmi_7x_8ch_build_controls(struct hda_codec * codec)2955 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2956 {
2957 	struct hdmi_spec *spec = codec->spec;
2958 	struct hda_pcm *info;
2959 	struct snd_pcm_chmap *chmap;
2960 	int err;
2961 
2962 	err = simple_playback_build_controls(codec);
2963 	if (err < 0)
2964 		return err;
2965 
2966 	/* add channel maps */
2967 	info = get_pcm_rec(spec, 0);
2968 	err = snd_pcm_add_chmap_ctls(info->pcm,
2969 				     SNDRV_PCM_STREAM_PLAYBACK,
2970 				     snd_pcm_alt_chmaps, 8, 0, &chmap);
2971 	if (err < 0)
2972 		return err;
2973 	switch (codec->preset->vendor_id) {
2974 	case 0x10de0002:
2975 	case 0x10de0003:
2976 	case 0x10de0005:
2977 	case 0x10de0006:
2978 		chmap->channel_mask = (1U << 2) | (1U << 8);
2979 		break;
2980 	case 0x10de0007:
2981 		chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2982 	}
2983 	return 0;
2984 }
2985 
patch_nvhdmi_8ch_7x(struct hda_codec * codec)2986 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2987 {
2988 	struct hdmi_spec *spec;
2989 	int err = patch_nvhdmi_2ch(codec);
2990 	if (err < 0)
2991 		return err;
2992 	spec = codec->spec;
2993 	spec->multiout.max_channels = 8;
2994 	spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2995 	codec->patch_ops.init = nvhdmi_7x_init_8ch;
2996 	codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2997 	codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2998 
2999 	/* Initialize the audio infoframe channel mask and checksum to something
3000 	 * valid */
3001 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3002 
3003 	return 0;
3004 }
3005 
3006 /*
3007  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3008  * - 0x10de0015
3009  * - 0x10de0040
3010  */
nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap * chmap,struct hdac_cea_channel_speaker_allocation * cap,int channels)3011 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3012 		struct hdac_cea_channel_speaker_allocation *cap, int channels)
3013 {
3014 	if (cap->ca_index == 0x00 && channels == 2)
3015 		return SNDRV_CTL_TLVT_CHMAP_FIXED;
3016 
3017 	/* If the speaker allocation matches the channel count, it is OK. */
3018 	if (cap->channels != channels)
3019 		return -1;
3020 
3021 	/* all channels are remappable freely */
3022 	return SNDRV_CTL_TLVT_CHMAP_VAR;
3023 }
3024 
nvhdmi_chmap_validate(struct hdac_chmap * chmap,int ca,int chs,unsigned char * map)3025 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3026 		int ca, int chs, unsigned char *map)
3027 {
3028 	if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3029 		return -EINVAL;
3030 
3031 	return 0;
3032 }
3033 
patch_nvhdmi(struct hda_codec * codec)3034 static int patch_nvhdmi(struct hda_codec *codec)
3035 {
3036 	struct hdmi_spec *spec;
3037 	int err;
3038 
3039 	err = patch_generic_hdmi(codec);
3040 	if (err)
3041 		return err;
3042 
3043 	spec = codec->spec;
3044 	spec->dyn_pin_out = true;
3045 
3046 	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3047 		nvhdmi_chmap_cea_alloc_validate_get_type;
3048 	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3049 
3050 	return 0;
3051 }
3052 
3053 /*
3054  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3055  * accessed using vendor-defined verbs. These registers can be used for
3056  * interoperability between the HDA and HDMI drivers.
3057  */
3058 
3059 /* Audio Function Group node */
3060 #define NVIDIA_AFG_NID 0x01
3061 
3062 /*
3063  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3064  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3065  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3066  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3067  * additional bit (at position 30) to signal the validity of the format.
3068  *
3069  * | 31      | 30    | 29  16 | 15   0 |
3070  * +---------+-------+--------+--------+
3071  * | TRIGGER | VALID | UNUSED | FORMAT |
3072  * +-----------------------------------|
3073  *
3074  * Note that for the trigger bit to take effect it needs to change value
3075  * (i.e. it needs to be toggled).
3076  */
3077 #define NVIDIA_GET_SCRATCH0		0xfa6
3078 #define NVIDIA_SET_SCRATCH0_BYTE0	0xfa7
3079 #define NVIDIA_SET_SCRATCH0_BYTE1	0xfa8
3080 #define NVIDIA_SET_SCRATCH0_BYTE2	0xfa9
3081 #define NVIDIA_SET_SCRATCH0_BYTE3	0xfaa
3082 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3083 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3084 
3085 #define NVIDIA_GET_SCRATCH1		0xfab
3086 #define NVIDIA_SET_SCRATCH1_BYTE0	0xfac
3087 #define NVIDIA_SET_SCRATCH1_BYTE1	0xfad
3088 #define NVIDIA_SET_SCRATCH1_BYTE2	0xfae
3089 #define NVIDIA_SET_SCRATCH1_BYTE3	0xfaf
3090 
3091 /*
3092  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3093  * the format is invalidated so that the HDMI codec can be disabled.
3094  */
tegra_hdmi_set_format(struct hda_codec * codec,unsigned int format)3095 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3096 {
3097 	unsigned int value;
3098 
3099 	/* bits [31:30] contain the trigger and valid bits */
3100 	value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3101 				   NVIDIA_GET_SCRATCH0, 0);
3102 	value = (value >> 24) & 0xff;
3103 
3104 	/* bits [15:0] are used to store the HDA format */
3105 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3106 			    NVIDIA_SET_SCRATCH0_BYTE0,
3107 			    (format >> 0) & 0xff);
3108 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3109 			    NVIDIA_SET_SCRATCH0_BYTE1,
3110 			    (format >> 8) & 0xff);
3111 
3112 	/* bits [16:24] are unused */
3113 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3114 			    NVIDIA_SET_SCRATCH0_BYTE2, 0);
3115 
3116 	/*
3117 	 * Bit 30 signals that the data is valid and hence that HDMI audio can
3118 	 * be enabled.
3119 	 */
3120 	if (format == 0)
3121 		value &= ~NVIDIA_SCRATCH_VALID;
3122 	else
3123 		value |= NVIDIA_SCRATCH_VALID;
3124 
3125 	/*
3126 	 * Whenever the trigger bit is toggled, an interrupt is raised in the
3127 	 * HDMI codec. The HDMI driver will use that as trigger to update its
3128 	 * configuration.
3129 	 */
3130 	value ^= NVIDIA_SCRATCH_TRIGGER;
3131 
3132 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3133 			    NVIDIA_SET_SCRATCH0_BYTE3, value);
3134 }
3135 
tegra_hdmi_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3136 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3137 				  struct hda_codec *codec,
3138 				  unsigned int stream_tag,
3139 				  unsigned int format,
3140 				  struct snd_pcm_substream *substream)
3141 {
3142 	int err;
3143 
3144 	err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3145 						format, substream);
3146 	if (err < 0)
3147 		return err;
3148 
3149 	/* notify the HDMI codec of the format change */
3150 	tegra_hdmi_set_format(codec, format);
3151 
3152 	return 0;
3153 }
3154 
tegra_hdmi_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3155 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3156 				  struct hda_codec *codec,
3157 				  struct snd_pcm_substream *substream)
3158 {
3159 	/* invalidate the format in the HDMI codec */
3160 	tegra_hdmi_set_format(codec, 0);
3161 
3162 	return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3163 }
3164 
hda_find_pcm_by_type(struct hda_codec * codec,int type)3165 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3166 {
3167 	struct hdmi_spec *spec = codec->spec;
3168 	unsigned int i;
3169 
3170 	for (i = 0; i < spec->num_pins; i++) {
3171 		struct hda_pcm *pcm = get_pcm_rec(spec, i);
3172 
3173 		if (pcm->pcm_type == type)
3174 			return pcm;
3175 	}
3176 
3177 	return NULL;
3178 }
3179 
tegra_hdmi_build_pcms(struct hda_codec * codec)3180 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3181 {
3182 	struct hda_pcm_stream *stream;
3183 	struct hda_pcm *pcm;
3184 	int err;
3185 
3186 	err = generic_hdmi_build_pcms(codec);
3187 	if (err < 0)
3188 		return err;
3189 
3190 	pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3191 	if (!pcm)
3192 		return -ENODEV;
3193 
3194 	/*
3195 	 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3196 	 * codec about format changes.
3197 	 */
3198 	stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3199 	stream->ops.prepare = tegra_hdmi_pcm_prepare;
3200 	stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3201 
3202 	return 0;
3203 }
3204 
patch_tegra_hdmi(struct hda_codec * codec)3205 static int patch_tegra_hdmi(struct hda_codec *codec)
3206 {
3207 	int err;
3208 
3209 	err = patch_generic_hdmi(codec);
3210 	if (err)
3211 		return err;
3212 
3213 	codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3214 
3215 	return 0;
3216 }
3217 
3218 /*
3219  * ATI/AMD-specific implementations
3220  */
3221 
3222 #define is_amdhdmi_rev3_or_later(codec) \
3223 	((codec)->core.vendor_id == 0x1002aa01 && \
3224 	 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3225 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3226 
3227 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3228 #define ATI_VERB_SET_CHANNEL_ALLOCATION	0x771
3229 #define ATI_VERB_SET_DOWNMIX_INFO	0x772
3230 #define ATI_VERB_SET_MULTICHANNEL_01	0x777
3231 #define ATI_VERB_SET_MULTICHANNEL_23	0x778
3232 #define ATI_VERB_SET_MULTICHANNEL_45	0x779
3233 #define ATI_VERB_SET_MULTICHANNEL_67	0x77a
3234 #define ATI_VERB_SET_HBR_CONTROL	0x77c
3235 #define ATI_VERB_SET_MULTICHANNEL_1	0x785
3236 #define ATI_VERB_SET_MULTICHANNEL_3	0x786
3237 #define ATI_VERB_SET_MULTICHANNEL_5	0x787
3238 #define ATI_VERB_SET_MULTICHANNEL_7	0x788
3239 #define ATI_VERB_SET_MULTICHANNEL_MODE	0x789
3240 #define ATI_VERB_GET_CHANNEL_ALLOCATION	0xf71
3241 #define ATI_VERB_GET_DOWNMIX_INFO	0xf72
3242 #define ATI_VERB_GET_MULTICHANNEL_01	0xf77
3243 #define ATI_VERB_GET_MULTICHANNEL_23	0xf78
3244 #define ATI_VERB_GET_MULTICHANNEL_45	0xf79
3245 #define ATI_VERB_GET_MULTICHANNEL_67	0xf7a
3246 #define ATI_VERB_GET_HBR_CONTROL	0xf7c
3247 #define ATI_VERB_GET_MULTICHANNEL_1	0xf85
3248 #define ATI_VERB_GET_MULTICHANNEL_3	0xf86
3249 #define ATI_VERB_GET_MULTICHANNEL_5	0xf87
3250 #define ATI_VERB_GET_MULTICHANNEL_7	0xf88
3251 #define ATI_VERB_GET_MULTICHANNEL_MODE	0xf89
3252 
3253 /* AMD specific HDA cvt verbs */
3254 #define ATI_VERB_SET_RAMP_RATE		0x770
3255 #define ATI_VERB_GET_RAMP_RATE		0xf70
3256 
3257 #define ATI_OUT_ENABLE 0x1
3258 
3259 #define ATI_MULTICHANNEL_MODE_PAIRED	0
3260 #define ATI_MULTICHANNEL_MODE_SINGLE	1
3261 
3262 #define ATI_HBR_CAPABLE 0x01
3263 #define ATI_HBR_ENABLE 0x10
3264 
atihdmi_pin_get_eld(struct hda_codec * codec,hda_nid_t nid,unsigned char * buf,int * eld_size)3265 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3266 			   unsigned char *buf, int *eld_size)
3267 {
3268 	/* call hda_eld.c ATI/AMD-specific function */
3269 	return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3270 				    is_amdhdmi_rev3_or_later(codec));
3271 }
3272 
atihdmi_pin_setup_infoframe(struct hda_codec * codec,hda_nid_t pin_nid,int ca,int active_channels,int conn_type)3273 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3274 					int active_channels, int conn_type)
3275 {
3276 	snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3277 }
3278 
atihdmi_paired_swap_fc_lfe(int pos)3279 static int atihdmi_paired_swap_fc_lfe(int pos)
3280 {
3281 	/*
3282 	 * ATI/AMD have automatic FC/LFE swap built-in
3283 	 * when in pairwise mapping mode.
3284 	 */
3285 
3286 	switch (pos) {
3287 		/* see channel_allocations[].speakers[] */
3288 		case 2: return 3;
3289 		case 3: return 2;
3290 		default: break;
3291 	}
3292 
3293 	return pos;
3294 }
3295 
atihdmi_paired_chmap_validate(struct hdac_chmap * chmap,int ca,int chs,unsigned char * map)3296 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3297 			int ca, int chs, unsigned char *map)
3298 {
3299 	struct hdac_cea_channel_speaker_allocation *cap;
3300 	int i, j;
3301 
3302 	/* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3303 
3304 	cap = snd_hdac_get_ch_alloc_from_ca(ca);
3305 	for (i = 0; i < chs; ++i) {
3306 		int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3307 		bool ok = false;
3308 		bool companion_ok = false;
3309 
3310 		if (!mask)
3311 			continue;
3312 
3313 		for (j = 0 + i % 2; j < 8; j += 2) {
3314 			int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3315 			if (cap->speakers[chan_idx] == mask) {
3316 				/* channel is in a supported position */
3317 				ok = true;
3318 
3319 				if (i % 2 == 0 && i + 1 < chs) {
3320 					/* even channel, check the odd companion */
3321 					int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3322 					int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3323 					int comp_mask_act = cap->speakers[comp_chan_idx];
3324 
3325 					if (comp_mask_req == comp_mask_act)
3326 						companion_ok = true;
3327 					else
3328 						return -EINVAL;
3329 				}
3330 				break;
3331 			}
3332 		}
3333 
3334 		if (!ok)
3335 			return -EINVAL;
3336 
3337 		if (companion_ok)
3338 			i++; /* companion channel already checked */
3339 	}
3340 
3341 	return 0;
3342 }
3343 
atihdmi_pin_set_slot_channel(struct hdac_device * hdac,hda_nid_t pin_nid,int hdmi_slot,int stream_channel)3344 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3345 		hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3346 {
3347 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3348 	int verb;
3349 	int ati_channel_setup = 0;
3350 
3351 	if (hdmi_slot > 7)
3352 		return -EINVAL;
3353 
3354 	if (!has_amd_full_remap_support(codec)) {
3355 		hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3356 
3357 		/* In case this is an odd slot but without stream channel, do not
3358 		 * disable the slot since the corresponding even slot could have a
3359 		 * channel. In case neither have a channel, the slot pair will be
3360 		 * disabled when this function is called for the even slot. */
3361 		if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3362 			return 0;
3363 
3364 		hdmi_slot -= hdmi_slot % 2;
3365 
3366 		if (stream_channel != 0xf)
3367 			stream_channel -= stream_channel % 2;
3368 	}
3369 
3370 	verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3371 
3372 	/* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3373 
3374 	if (stream_channel != 0xf)
3375 		ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3376 
3377 	return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3378 }
3379 
atihdmi_pin_get_slot_channel(struct hdac_device * hdac,hda_nid_t pin_nid,int asp_slot)3380 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3381 				hda_nid_t pin_nid, int asp_slot)
3382 {
3383 	struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3384 	bool was_odd = false;
3385 	int ati_asp_slot = asp_slot;
3386 	int verb;
3387 	int ati_channel_setup;
3388 
3389 	if (asp_slot > 7)
3390 		return -EINVAL;
3391 
3392 	if (!has_amd_full_remap_support(codec)) {
3393 		ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3394 		if (ati_asp_slot % 2 != 0) {
3395 			ati_asp_slot -= 1;
3396 			was_odd = true;
3397 		}
3398 	}
3399 
3400 	verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3401 
3402 	ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3403 
3404 	if (!(ati_channel_setup & ATI_OUT_ENABLE))
3405 		return 0xf;
3406 
3407 	return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3408 }
3409 
atihdmi_paired_chmap_cea_alloc_validate_get_type(struct hdac_chmap * chmap,struct hdac_cea_channel_speaker_allocation * cap,int channels)3410 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3411 		struct hdac_chmap *chmap,
3412 		struct hdac_cea_channel_speaker_allocation *cap,
3413 		int channels)
3414 {
3415 	int c;
3416 
3417 	/*
3418 	 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3419 	 * we need to take that into account (a single channel may take 2
3420 	 * channel slots if we need to carry a silent channel next to it).
3421 	 * On Rev3+ AMD codecs this function is not used.
3422 	 */
3423 	int chanpairs = 0;
3424 
3425 	/* We only produce even-numbered channel count TLVs */
3426 	if ((channels % 2) != 0)
3427 		return -1;
3428 
3429 	for (c = 0; c < 7; c += 2) {
3430 		if (cap->speakers[c] || cap->speakers[c+1])
3431 			chanpairs++;
3432 	}
3433 
3434 	if (chanpairs * 2 != channels)
3435 		return -1;
3436 
3437 	return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3438 }
3439 
atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap * hchmap,struct hdac_cea_channel_speaker_allocation * cap,unsigned int * chmap,int channels)3440 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3441 		struct hdac_cea_channel_speaker_allocation *cap,
3442 		unsigned int *chmap, int channels)
3443 {
3444 	/* produce paired maps for pre-rev3 ATI/AMD codecs */
3445 	int count = 0;
3446 	int c;
3447 
3448 	for (c = 7; c >= 0; c--) {
3449 		int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3450 		int spk = cap->speakers[chan];
3451 		if (!spk) {
3452 			/* add N/A channel if the companion channel is occupied */
3453 			if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3454 				chmap[count++] = SNDRV_CHMAP_NA;
3455 
3456 			continue;
3457 		}
3458 
3459 		chmap[count++] = snd_hdac_spk_to_chmap(spk);
3460 	}
3461 
3462 	WARN_ON(count != channels);
3463 }
3464 
atihdmi_pin_hbr_setup(struct hda_codec * codec,hda_nid_t pin_nid,bool hbr)3465 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3466 				 bool hbr)
3467 {
3468 	int hbr_ctl, hbr_ctl_new;
3469 
3470 	hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3471 	if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3472 		if (hbr)
3473 			hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3474 		else
3475 			hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3476 
3477 		codec_dbg(codec,
3478 			  "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3479 				pin_nid,
3480 				hbr_ctl == hbr_ctl_new ? "" : "new-",
3481 				hbr_ctl_new);
3482 
3483 		if (hbr_ctl != hbr_ctl_new)
3484 			snd_hda_codec_write(codec, pin_nid, 0,
3485 						ATI_VERB_SET_HBR_CONTROL,
3486 						hbr_ctl_new);
3487 
3488 	} else if (hbr)
3489 		return -EINVAL;
3490 
3491 	return 0;
3492 }
3493 
atihdmi_setup_stream(struct hda_codec * codec,hda_nid_t cvt_nid,hda_nid_t pin_nid,u32 stream_tag,int format)3494 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3495 				hda_nid_t pin_nid, u32 stream_tag, int format)
3496 {
3497 
3498 	if (is_amdhdmi_rev3_or_later(codec)) {
3499 		int ramp_rate = 180; /* default as per AMD spec */
3500 		/* disable ramp-up/down for non-pcm as per AMD spec */
3501 		if (format & AC_FMT_TYPE_NON_PCM)
3502 			ramp_rate = 0;
3503 
3504 		snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3505 	}
3506 
3507 	return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3508 }
3509 
3510 
atihdmi_init(struct hda_codec * codec)3511 static int atihdmi_init(struct hda_codec *codec)
3512 {
3513 	struct hdmi_spec *spec = codec->spec;
3514 	int pin_idx, err;
3515 
3516 	err = generic_hdmi_init(codec);
3517 
3518 	if (err)
3519 		return err;
3520 
3521 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3522 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3523 
3524 		/* make sure downmix information in infoframe is zero */
3525 		snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3526 
3527 		/* enable channel-wise remap mode if supported */
3528 		if (has_amd_full_remap_support(codec))
3529 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3530 					    ATI_VERB_SET_MULTICHANNEL_MODE,
3531 					    ATI_MULTICHANNEL_MODE_SINGLE);
3532 	}
3533 
3534 	return 0;
3535 }
3536 
patch_atihdmi(struct hda_codec * codec)3537 static int patch_atihdmi(struct hda_codec *codec)
3538 {
3539 	struct hdmi_spec *spec;
3540 	struct hdmi_spec_per_cvt *per_cvt;
3541 	int err, cvt_idx;
3542 
3543 	err = patch_generic_hdmi(codec);
3544 
3545 	if (err)
3546 		return err;
3547 
3548 	codec->patch_ops.init = atihdmi_init;
3549 
3550 	spec = codec->spec;
3551 
3552 	spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3553 	spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3554 	spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3555 	spec->ops.setup_stream = atihdmi_setup_stream;
3556 
3557 	spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3558 	spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3559 
3560 	if (!has_amd_full_remap_support(codec)) {
3561 		/* override to ATI/AMD-specific versions with pairwise mapping */
3562 		spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3563 			atihdmi_paired_chmap_cea_alloc_validate_get_type;
3564 		spec->chmap.ops.cea_alloc_to_tlv_chmap =
3565 				atihdmi_paired_cea_alloc_to_tlv_chmap;
3566 		spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3567 	}
3568 
3569 	/* ATI/AMD converters do not advertise all of their capabilities */
3570 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3571 		per_cvt = get_cvt(spec, cvt_idx);
3572 		per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3573 		per_cvt->rates |= SUPPORTED_RATES;
3574 		per_cvt->formats |= SUPPORTED_FORMATS;
3575 		per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3576 	}
3577 
3578 	spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3579 
3580 	return 0;
3581 }
3582 
3583 /* VIA HDMI Implementation */
3584 #define VIAHDMI_CVT_NID	0x02	/* audio converter1 */
3585 #define VIAHDMI_PIN_NID	0x03	/* HDMI output pin1 */
3586 
patch_via_hdmi(struct hda_codec * codec)3587 static int patch_via_hdmi(struct hda_codec *codec)
3588 {
3589 	return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3590 }
3591 
3592 /*
3593  * patch entries
3594  */
3595 static const struct hda_device_id snd_hda_id_hdmi[] = {
3596 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",	patch_atihdmi),
3597 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",	patch_atihdmi),
3598 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",	patch_atihdmi),
3599 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",	patch_atihdmi),
3600 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",	patch_generic_hdmi),
3601 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",	patch_generic_hdmi),
3602 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",	patch_generic_hdmi),
3603 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",	patch_nvhdmi_2ch),
3604 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
3605 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
3606 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",	patch_nvhdmi_8ch_7x),
3607 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
3608 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
3609 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",	patch_nvhdmi_8ch_7x),
3610 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",	patch_nvhdmi),
3611 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",	patch_nvhdmi),
3612 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",	patch_nvhdmi),
3613 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",	patch_nvhdmi),
3614 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",	patch_nvhdmi),
3615 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",	patch_nvhdmi),
3616 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",	patch_nvhdmi),
3617 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",	patch_nvhdmi),
3618 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",	patch_nvhdmi),
3619 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",	patch_nvhdmi),
3620 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",	patch_nvhdmi),
3621 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",	patch_nvhdmi),
3622 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",	patch_nvhdmi),
3623 /* 17 is known to be absent */
3624 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",	patch_nvhdmi),
3625 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",	patch_nvhdmi),
3626 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",	patch_nvhdmi),
3627 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",	patch_nvhdmi),
3628 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",	patch_nvhdmi),
3629 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",	patch_tegra_hdmi),
3630 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",	patch_tegra_hdmi),
3631 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",	patch_tegra_hdmi),
3632 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP",	patch_tegra_hdmi),
3633 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",	patch_nvhdmi),
3634 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",	patch_nvhdmi),
3635 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",	patch_nvhdmi),
3636 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",	patch_nvhdmi),
3637 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",	patch_nvhdmi),
3638 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",	patch_nvhdmi),
3639 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",	patch_nvhdmi),
3640 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",	patch_nvhdmi),
3641 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",	patch_nvhdmi),
3642 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",	patch_nvhdmi),
3643 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",	patch_nvhdmi),
3644 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",	patch_nvhdmi),
3645 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",	patch_nvhdmi_2ch),
3646 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",	patch_nvhdmi),
3647 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",	patch_nvhdmi),
3648 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",	patch_nvhdmi),
3649 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",	patch_nvhdmi),
3650 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",	patch_nvhdmi),
3651 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",	patch_nvhdmi),
3652 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",	patch_nvhdmi),
3653 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",	patch_nvhdmi),
3654 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",	patch_nvhdmi),
3655 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",	patch_nvhdmi),
3656 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",	patch_nvhdmi),
3657 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",	patch_nvhdmi),
3658 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",	patch_nvhdmi),
3659 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",	patch_nvhdmi),
3660 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",	patch_nvhdmi),
3661 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",	patch_nvhdmi),
3662 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",	patch_nvhdmi),
3663 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",	patch_nvhdmi),
3664 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",	patch_nvhdmi),
3665 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",	patch_nvhdmi),
3666 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",	patch_nvhdmi),
3667 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",	patch_nvhdmi),
3668 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",	patch_nvhdmi),
3669 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",	patch_nvhdmi),
3670 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",	patch_nvhdmi_2ch),
3671 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",	patch_nvhdmi_2ch),
3672 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",	patch_via_hdmi),
3673 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",	patch_via_hdmi),
3674 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",	patch_generic_hdmi),
3675 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",	patch_generic_hdmi),
3676 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
3677 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",	patch_generic_hdmi),
3678 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",	patch_generic_hdmi),
3679 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",	patch_generic_hdmi),
3680 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
3681 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI",	patch_i915_cpt_hdmi),
3682 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3683 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",	patch_i915_hsw_hdmi),
3684 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",	patch_i915_hsw_hdmi),
3685 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",	patch_i915_hsw_hdmi),
3686 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",	patch_i915_hsw_hdmi),
3687 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",	patch_i915_hsw_hdmi),
3688 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",	patch_i915_hsw_hdmi),
3689 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",	patch_generic_hdmi),
3690 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI",	patch_i915_byt_hdmi),
3691 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",	patch_i915_byt_hdmi),
3692 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",	patch_generic_hdmi),
3693 /* special ID for generic HDMI */
3694 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3695 {} /* terminator */
3696 };
3697 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3698 
3699 MODULE_LICENSE("GPL");
3700 MODULE_DESCRIPTION("HDMI HD-audio codec");
3701 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3702 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3703 MODULE_ALIAS("snd-hda-codec-atihdmi");
3704 
3705 static struct hda_codec_driver hdmi_driver = {
3706 	.id = snd_hda_id_hdmi,
3707 };
3708 
3709 module_hda_codec_driver(hdmi_driver);
3710