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1 /*
2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3  *
4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
5  *      code based on hdsp.c   Paul Davis
6  *                             Marcus Andersson
7  *                             Thomas Charbonnel
8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
9  *                                               <remy.bruno@trinnov.com>
10  *
11  *      Modified 2009-04-13 for proper metering by Florian Faber
12  *                                               <faber@faberman.de>
13  *
14  *      Modified 2009-04-14 for native float support by Florian Faber
15  *                                               <faber@faberman.de>
16  *
17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18  *                                               <faber@faberman.de>
19  *
20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
21  *
22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23  *
24  *	Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25  *
26  *   This program is free software; you can redistribute it and/or modify
27  *   it under the terms of the GNU General Public License as published by
28  *   the Free Software Foundation; either version 2 of the License, or
29  *   (at your option) any later version.
30  *
31  *   This program is distributed in the hope that it will be useful,
32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  *   GNU General Public License for more details.
35  *
36  *   You should have received a copy of the GNU General Public License
37  *   along with this program; if not, write to the Free Software
38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
39  *
40  */
41 
42 /* *************    Register Documentation   *******************************************************
43  *
44  * Work in progress! Documentation is based on the code in this file.
45  *
46  * --------- HDSPM_controlRegister ---------
47  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
48  * :||||.||||:||||.||||:||||.||||:||||.||||:
49  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
50  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
51  * :||||.||||:||||.||||:||||.||||:||||.||||:
52  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
53  * :    .    :    .    :    .    :  x .    :  HDSPM_AudioInterruptEnable \_ setting both bits
54  * :    .    :    .    :    .    :    .   x:  HDSPM_Start                /  enables audio IO
55  * :    .    :    .    :    .    :   x.    :  HDSPM_ClockModeMaster - 1: Master, 0: Slave
56  * :    .    :    .    :    .    :    .210 :  HDSPM_LatencyMask - 3 Bit value for latency
57  * :    .    :    .    :    .    :    .    :      0:64, 1:128, 2:256, 3:512,
58  * :    .    :    .    :    .    :    .    :      4:1024, 5:2048, 6:4096, 7:8192
59  * :x   .    :    .    :    .   x:xx  .    :  HDSPM_FrequencyMask
60  * :    .    :    .    :    .    :10  .    :  HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
61  * :    .    :    .    :    .   x:    .    :  <MADI> HDSPM_DoubleSpeed
62  * :x   .    :    .    :    .    :    .    :  <MADI> HDSPM_QuadSpeed
63  * :    .  3 :    .  10:  2 .    :    .    :  HDSPM_SyncRefMask :
64  * :    .    :    .   x:    .    :    .    :  HDSPM_SyncRef0
65  * :    .    :    .  x :    .    :    .    :  HDSPM_SyncRef1
66  * :    .    :    .    :  x .    :    .    :  <AES32> HDSPM_SyncRef2
67  * :    .  x :    .    :    .    :    .    :  <AES32> HDSPM_SyncRef3
68  * :    .    :    .  10:    .    :    .    :  <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
69  * :    .  3 :    .  10:  2 .    :    .    :  <AES32>  0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
70  * :    .  x :    .    :    .    :    .    :  <MADIe> HDSPe_FLOAT_FORMAT
71  * :    .    :    .    : x  .    :    .    :  <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
72  * :    .    :    .    :x   .    :    .    :  <MADI> HDSPM_InputSelect1
73  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
74  * :    .    :    .    :    . x  :    .    :  <MADI> HDSPM_TX_64ch
75  * :    .    :    .    :    . x  :    .    :  <AES32> HDSPM_Emphasis
76  * :    .    :    .    :    .x   :    .    :  <MADI> HDSPM_AutoInp
77  * :    .    :    . x  :    .    :    .    :  <MADI> HDSPM_SMUX
78  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
79  * :    .    :   x.    :    .    :    .    :  <MADI> HDSPM_taxi_reset
80  * :    .   x:    .    :    .    :    .    :  <MADI> HDSPM_LineOut
81  * :    .   x:    .    :    .    :    .    :  <AES32> ??????????????????
82  * :    .    :   x.    :    .    :    .    :  <AES32> HDSPM_WCK48
83  * :    .    :    .    :    .x   :    .    :  <AES32> HDSPM_Dolby
84  * :    .    : x  .    :    .    :    .    :  HDSPM_Midi0InterruptEnable
85  * :    .    :x   .    :    .    :    .    :  HDSPM_Midi1InterruptEnable
86  * :    .    :  x .    :    .    :    .    :  HDSPM_Midi2InterruptEnable
87  * :    . x  :    .    :    .    :    .    :  <MADI> HDSPM_Midi3InterruptEnable
88  * :    . x  :    .    :    .    :    .    :  <AES32> HDSPM_DS_DoubleWire
89  * :    .x   :    .    :    .    :    .    :  <AES32> HDSPM_QS_DoubleWire
90  * :   x.    :    .    :    .    :    .    :  <AES32> HDSPM_QS_QuadWire
91  * :    .    :    .    :    .  x :    .    :  <AES32> HDSPM_Professional
92  * : x  .    :    .    :    .    :    .    :  HDSPM_wclk_sel
93  * :    .    :    .    :    .    :    .    :
94  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
95  * :||||.||||:||||.||||:||||.||||:||||.||||:
96  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
97  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
98  * :||||.||||:||||.||||:||||.||||:||||.||||:
99  * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
100  *
101  *
102  *
103  * AIO / RayDAT only
104  *
105  * ------------ HDSPM_WR_SETTINGS ----------
106  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107  * :1098.7654:3210.9876:5432.1098:7654.3210:
108  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110  * :||||.||||:||||.||||:||||.||||:||||.||||:
111  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112  * :    .    :    .    :    .    :    .   x: HDSPM_c0Master 1: Master, 0: Slave
113  * :    .    :    .    :    .    :    .  x : HDSPM_c0_SyncRef0
114  * :    .    :    .    :    .    :    . x  : HDSPM_c0_SyncRef1
115  * :    .    :    .    :    .    :    .x   : HDSPM_c0_SyncRef2
116  * :    .    :    .    :    .    :   x.    : HDSPM_c0_SyncRef3
117  * :    .    :    .    :    .    :   3.210 : HDSPM_c0_SyncRefMask:
118  * :    .    :    .    :    .    :    .    :  RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
120  * :    .    :    .    :    .    :    .    :  AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
122  * :    .    :    .    :    .    :    .    :
123  * :    .    :    .    :    .    :    .    :
124  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125  * :1098.7654:3210.9876:5432.1098:7654.3210:
126  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128  * :||||.||||:||||.||||:||||.||||:||||.||||:
129  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
130  *
131  */
132 #include <linux/init.h>
133 #include <linux/delay.h>
134 #include <linux/interrupt.h>
135 #include <linux/module.h>
136 #include <linux/slab.h>
137 #include <linux/pci.h>
138 #include <linux/math64.h>
139 #include <linux/io.h>
140 
141 #include <sound/core.h>
142 #include <sound/control.h>
143 #include <sound/pcm.h>
144 #include <sound/pcm_params.h>
145 #include <sound/info.h>
146 #include <sound/asoundef.h>
147 #include <sound/rawmidi.h>
148 #include <sound/hwdep.h>
149 #include <sound/initval.h>
150 
151 #include <sound/hdspm.h>
152 
153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	  /* Index 0-MAX */
154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	  /* ID for this card */
155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
156 
157 module_param_array(index, int, NULL, 0444);
158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
159 
160 module_param_array(id, charp, NULL, 0444);
161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
162 
163 module_param_array(enable, bool, NULL, 0444);
164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
165 
166 
167 MODULE_AUTHOR
168 (
169 	"Winfried Ritsch <ritsch_AT_iem.at>, "
170 	"Paul Davis <paul@linuxaudiosystems.com>, "
171 	"Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
172 	"Remy Bruno <remy.bruno@trinnov.com>, "
173 	"Florian Faber <faberman@linuxproaudio.org>, "
174 	"Adrian Knoth <adi@drcomp.erfurt.thur.de>"
175 );
176 MODULE_DESCRIPTION("RME HDSPM");
177 MODULE_LICENSE("GPL");
178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
179 
180 /* --- Write registers. ---
181   These are defined as byte-offsets from the iobase value.  */
182 
183 #define HDSPM_WR_SETTINGS             0
184 #define HDSPM_outputBufferAddress    32
185 #define HDSPM_inputBufferAddress     36
186 #define HDSPM_controlRegister	     64
187 #define HDSPM_interruptConfirmation  96
188 #define HDSPM_control2Reg	     256  /* not in specs ???????? */
189 #define HDSPM_freqReg                256  /* for setting arbitrary clock values (DDS feature) */
190 #define HDSPM_midiDataOut0	     352  /* just believe in old code */
191 #define HDSPM_midiDataOut1	     356
192 #define HDSPM_eeprom_wr		     384  /* for AES32 */
193 
194 /* DMA enable for 64 channels, only Bit 0 is relevant */
195 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
196 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
197 
198 /* 16 page addresses for each of the 64 channels DMA buffer in and out
199    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
200 #define HDSPM_pageAddressBufferOut       8192
201 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
202 
203 #define HDSPM_MADI_mixerBase    32768	/* 32768-65535 for 2x64x64 Fader */
204 
205 #define HDSPM_MATRIX_MIXER_SIZE  8192	/* = 2*64*64 * 4 Byte => 32kB */
206 
207 /* --- Read registers. ---
208    These are defined as byte-offsets from the iobase value */
209 #define HDSPM_statusRegister    0
210 /*#define HDSPM_statusRegister2  96 */
211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
212  * offset 192, for AES32 *and* MADI
213  * => need to check that offset 192 is working on MADI */
214 #define HDSPM_statusRegister2  192
215 #define HDSPM_timecodeRegister 128
216 
217 /* AIO, RayDAT */
218 #define HDSPM_RD_STATUS_0 0
219 #define HDSPM_RD_STATUS_1 64
220 #define HDSPM_RD_STATUS_2 128
221 #define HDSPM_RD_STATUS_3 192
222 
223 #define HDSPM_RD_TCO           256
224 #define HDSPM_RD_PLL_FREQ      512
225 #define HDSPM_WR_TCO           128
226 
227 #define HDSPM_TCO1_TCO_lock			0x00000001
228 #define HDSPM_TCO1_WCK_Input_Range_LSB		0x00000002
229 #define HDSPM_TCO1_WCK_Input_Range_MSB		0x00000004
230 #define HDSPM_TCO1_LTC_Input_valid		0x00000008
231 #define HDSPM_TCO1_WCK_Input_valid		0x00000010
232 #define HDSPM_TCO1_Video_Input_Format_NTSC	0x00000020
233 #define HDSPM_TCO1_Video_Input_Format_PAL	0x00000040
234 
235 #define HDSPM_TCO1_set_TC			0x00000100
236 #define HDSPM_TCO1_set_drop_frame_flag		0x00000200
237 #define HDSPM_TCO1_LTC_Format_LSB		0x00000400
238 #define HDSPM_TCO1_LTC_Format_MSB		0x00000800
239 
240 #define HDSPM_TCO2_TC_run			0x00010000
241 #define HDSPM_TCO2_WCK_IO_ratio_LSB		0x00020000
242 #define HDSPM_TCO2_WCK_IO_ratio_MSB		0x00040000
243 #define HDSPM_TCO2_set_num_drop_frames_LSB	0x00080000
244 #define HDSPM_TCO2_set_num_drop_frames_MSB	0x00100000
245 #define HDSPM_TCO2_set_jam_sync			0x00200000
246 #define HDSPM_TCO2_set_flywheel			0x00400000
247 
248 #define HDSPM_TCO2_set_01_4			0x01000000
249 #define HDSPM_TCO2_set_pull_down		0x02000000
250 #define HDSPM_TCO2_set_pull_up			0x04000000
251 #define HDSPM_TCO2_set_freq			0x08000000
252 #define HDSPM_TCO2_set_term_75R			0x10000000
253 #define HDSPM_TCO2_set_input_LSB		0x20000000
254 #define HDSPM_TCO2_set_input_MSB		0x40000000
255 #define HDSPM_TCO2_set_freq_from_app		0x80000000
256 
257 
258 #define HDSPM_midiDataOut0    352
259 #define HDSPM_midiDataOut1    356
260 #define HDSPM_midiDataOut2    368
261 
262 #define HDSPM_midiDataIn0     360
263 #define HDSPM_midiDataIn1     364
264 #define HDSPM_midiDataIn2     372
265 #define HDSPM_midiDataIn3     376
266 
267 /* status is data bytes in MIDI-FIFO (0-128) */
268 #define HDSPM_midiStatusOut0  384
269 #define HDSPM_midiStatusOut1  388
270 #define HDSPM_midiStatusOut2  400
271 
272 #define HDSPM_midiStatusIn0   392
273 #define HDSPM_midiStatusIn1   396
274 #define HDSPM_midiStatusIn2   404
275 #define HDSPM_midiStatusIn3   408
276 
277 
278 /* the meters are regular i/o-mapped registers, but offset
279    considerably from the rest. the peak registers are reset
280    when read; the least-significant 4 bits are full-scale counters;
281    the actual peak value is in the most-significant 24 bits.
282 */
283 
284 #define HDSPM_MADI_INPUT_PEAK		4096
285 #define HDSPM_MADI_PLAYBACK_PEAK	4352
286 #define HDSPM_MADI_OUTPUT_PEAK		4608
287 
288 #define HDSPM_MADI_INPUT_RMS_L		6144
289 #define HDSPM_MADI_PLAYBACK_RMS_L	6400
290 #define HDSPM_MADI_OUTPUT_RMS_L		6656
291 
292 #define HDSPM_MADI_INPUT_RMS_H		7168
293 #define HDSPM_MADI_PLAYBACK_RMS_H	7424
294 #define HDSPM_MADI_OUTPUT_RMS_H		7680
295 
296 /* --- Control Register bits --------- */
297 #define HDSPM_Start                (1<<0) /* start engine */
298 
299 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
300 #define HDSPM_Latency1             (1<<2) /* where n is defined */
301 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
302 
303 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
304 #define HDSPM_c0Master		0x1    /* Master clock bit in settings
305 					  register [RayDAT, AIO] */
306 
307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
308 
309 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
310 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
311 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
312 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
313 
314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
315 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
316 				     56channelMODE=0 */ /* MADI ONLY*/
317 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
318 
319 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
320                                      0=off, 1=on  */ /* MADI ONLY */
321 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
322 
323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
324 				    * -- MADI ONLY
325 				    */
326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
327 
328 #define HDSPM_SyncRef2     (1<<13)
329 #define HDSPM_SyncRef3     (1<<25)
330 
331 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
332 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
333                                       AES additional bits in
334 				      lower 5 Audiodatabits ??? */
335 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
336 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
337 
338 #define HDSPM_Midi0InterruptEnable 0x0400000
339 #define HDSPM_Midi1InterruptEnable 0x0800000
340 #define HDSPM_Midi2InterruptEnable 0x0200000
341 #define HDSPM_Midi3InterruptEnable 0x4000000
342 
343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
344 #define HDSPe_FLOAT_FORMAT         0x2000000
345 
346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
348 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
349 
350 #define HDSPM_wclk_sel (1<<30)
351 
352 /* additional control register bits for AIO*/
353 #define HDSPM_c0_Wck48				0x20 /* also RayDAT */
354 #define HDSPM_c0_Input0				0x1000
355 #define HDSPM_c0_Input1				0x2000
356 #define HDSPM_c0_Spdif_Opt			0x4000
357 #define HDSPM_c0_Pro				0x8000
358 #define HDSPM_c0_clr_tms			0x10000
359 #define HDSPM_c0_AEB1				0x20000
360 #define HDSPM_c0_AEB2				0x40000
361 #define HDSPM_c0_LineOut			0x80000
362 #define HDSPM_c0_AD_GAIN0			0x100000
363 #define HDSPM_c0_AD_GAIN1			0x200000
364 #define HDSPM_c0_DA_GAIN0			0x400000
365 #define HDSPM_c0_DA_GAIN1			0x800000
366 #define HDSPM_c0_PH_GAIN0			0x1000000
367 #define HDSPM_c0_PH_GAIN1			0x2000000
368 #define HDSPM_c0_Sym6db				0x4000000
369 
370 
371 /* --- bit helper defines */
372 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
373 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
374 			      HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
375 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
376 #define HDSPM_InputOptical   0
377 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
378 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
379 			      HDSPM_SyncRef2|HDSPM_SyncRef3)
380 
381 #define HDSPM_c0_SyncRef0      0x2
382 #define HDSPM_c0_SyncRef1      0x4
383 #define HDSPM_c0_SyncRef2      0x8
384 #define HDSPM_c0_SyncRef3      0x10
385 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
386 				HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
387 
388 #define HDSPM_SYNC_FROM_WORD    0	/* Preferred sync reference */
389 #define HDSPM_SYNC_FROM_MADI    1	/* choices - used by "pref_sync_ref" */
390 #define HDSPM_SYNC_FROM_TCO     2
391 #define HDSPM_SYNC_FROM_SYNC_IN 3
392 
393 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
394 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
395 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
396 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
398 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
399 				HDSPM_Frequency0)
400 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
401 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
402 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
403 				 HDSPM_Frequency0)
404 
405 
406 /* Synccheck Status */
407 #define HDSPM_SYNC_CHECK_NO_LOCK 0
408 #define HDSPM_SYNC_CHECK_LOCK    1
409 #define HDSPM_SYNC_CHECK_SYNC	 2
410 
411 /* AutoSync References - used by "autosync_ref" control switch */
412 #define HDSPM_AUTOSYNC_FROM_WORD      0
413 #define HDSPM_AUTOSYNC_FROM_MADI      1
414 #define HDSPM_AUTOSYNC_FROM_TCO       2
415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
416 #define HDSPM_AUTOSYNC_FROM_NONE      4
417 
418 /* Possible sources of MADI input */
419 #define HDSPM_OPTICAL 0		/* optical   */
420 #define HDSPM_COAXIAL 1		/* BNC */
421 
422 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
423 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
424 
425 #define hdspm_encode_in(x) (((x)&0x3)<<14)
426 #define hdspm_decode_in(x) (((x)>>14)&0x3)
427 
428 /* --- control2 register bits --- */
429 #define HDSPM_TMS             (1<<0)
430 #define HDSPM_TCK             (1<<1)
431 #define HDSPM_TDI             (1<<2)
432 #define HDSPM_JTAG            (1<<3)
433 #define HDSPM_PWDN            (1<<4)
434 #define HDSPM_PROGRAM	      (1<<5)
435 #define HDSPM_CONFIG_MODE_0   (1<<6)
436 #define HDSPM_CONFIG_MODE_1   (1<<7)
437 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
438 #define HDSPM_BIGENDIAN_MODE  (1<<9)
439 #define HDSPM_RD_MULTIPLE     (1<<10)
440 
441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
442      that do not conflict with specific bits for AES32 seem to be valid also
443      for the AES32
444  */
445 #define HDSPM_audioIRQPending    (1<<0)	/* IRQ is high and pending */
446 #define HDSPM_RX_64ch            (1<<1)	/* Input 64chan. MODE=1, 56chn MODE=0 */
447 #define HDSPM_AB_int             (1<<2)	/* InputChannel Opt=0, Coax=1
448 					 * (like inp0)
449 					 */
450 
451 #define HDSPM_madiLock           (1<<3)	/* MADI Locked =1, no=0 */
452 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
453 
454 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
455 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
456 
457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
459 
460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
461 			/* since 64byte accurate, last 6 bits are not used */
462 
463 
464 
465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
466 
467 #define HDSPM_madiFreq0         (1<<22)	/* system freq 0=error */
468 #define HDSPM_madiFreq1         (1<<23)	/* 1=32, 2=44.1 3=48 */
469 #define HDSPM_madiFreq2         (1<<24)	/* 4=64, 5=88.2 6=96 */
470 #define HDSPM_madiFreq3         (1<<25)	/* 7=128, 8=176.4 9=192 */
471 
472 #define HDSPM_BufferID          (1<<26)	/* (Double)Buffer ID toggles with
473 					 * Interrupt
474 					 */
475 #define HDSPM_tco_detect         0x08000000
476 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
477 
478 #define HDSPM_s2_tco_detect      0x00000040
479 #define HDSPM_s2_AEBO_D          0x00000080
480 #define HDSPM_s2_AEBI_D          0x00000100
481 
482 
483 #define HDSPM_midi0IRQPending    0x40000000
484 #define HDSPM_midi1IRQPending    0x80000000
485 #define HDSPM_midi2IRQPending    0x20000000
486 #define HDSPM_midi2IRQPendingAES 0x00000020
487 #define HDSPM_midi3IRQPending    0x00200000
488 
489 /* --- status bit helpers */
490 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
491 			     HDSPM_madiFreq2|HDSPM_madiFreq3)
492 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
493 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
494 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
495 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
496 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
497 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
498 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
500 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
501 
502 /* Status2 Register bits */ /* MADI ONLY */
503 
504 #define HDSPM_version0 (1<<0)	/* not really defined but I guess */
505 #define HDSPM_version1 (1<<1)	/* in former cards it was ??? */
506 #define HDSPM_version2 (1<<2)
507 
508 #define HDSPM_wcLock (1<<3)	/* Wordclock is detected and locked */
509 #define HDSPM_wcSync (1<<4)	/* Wordclock is in sync with systemclock */
510 
511 #define HDSPM_wc_freq0 (1<<5)	/* input freq detected via autosync  */
512 #define HDSPM_wc_freq1 (1<<6)	/* 001=32, 010==44.1, 011=48, */
513 #define HDSPM_wc_freq2 (1<<7)	/* 100=64, 101=88.2, 110=96, 111=128 */
514 #define HDSPM_wc_freq3 0x800	/* 1000=176.4, 1001=192 */
515 
516 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
517 #define HDSPM_SyncRef1 0x20000
518 
519 #define HDSPM_SelSyncRef0 (1<<8)	/* AutoSync Source */
520 #define HDSPM_SelSyncRef1 (1<<9)	/* 000=word, 001=MADI, */
521 #define HDSPM_SelSyncRef2 (1<<10)	/* 111=no valid signal */
522 
523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
524 
525 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
526 			    HDSPM_wc_freq3)
527 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
528 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
529 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
530 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
531 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
532 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
533 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
535 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
536 
537 #define HDSPM_status1_F_0 0x0400000
538 #define HDSPM_status1_F_1 0x0800000
539 #define HDSPM_status1_F_2 0x1000000
540 #define HDSPM_status1_F_3 0x2000000
541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
542 
543 
544 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
545 				    HDSPM_SelSyncRef2)
546 #define HDSPM_SelSyncRef_WORD      0
547 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
548 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
549 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
550 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
551 				    HDSPM_SelSyncRef2)
552 
553 /*
554    For AES32, bits for status, status2 and timecode are different
555 */
556 /* status */
557 #define HDSPM_AES32_wcLock	0x0200000
558 #define HDSPM_AES32_wcSync	0x0100000
559 #define HDSPM_AES32_wcFreq_bit  22
560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
561   HDSPM_bit2freq */
562 #define HDSPM_AES32_syncref_bit  16
563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
564 
565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
577 
578 /*  status2 */
579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
580 #define HDSPM_LockAES   0x80
581 #define HDSPM_LockAES1  0x80
582 #define HDSPM_LockAES2  0x40
583 #define HDSPM_LockAES3  0x20
584 #define HDSPM_LockAES4  0x10
585 #define HDSPM_LockAES5  0x8
586 #define HDSPM_LockAES6  0x4
587 #define HDSPM_LockAES7  0x2
588 #define HDSPM_LockAES8  0x1
589 /*
590    Timecode
591    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
592    AES i+1
593  bits 3210
594       0001  32kHz
595       0010  44.1kHz
596       0011  48kHz
597       0100  64kHz
598       0101  88.2kHz
599       0110  96kHz
600       0111  128kHz
601       1000  176.4kHz
602       1001  192kHz
603   NB: Timecode register doesn't seem to work on AES32 card revision 230
604 */
605 
606 /* Mixer Values */
607 #define UNITY_GAIN          32768	/* = 65536/2 */
608 #define MINUS_INFINITY_GAIN 0
609 
610 /* Number of channels for different Speed Modes */
611 #define MADI_SS_CHANNELS       64
612 #define MADI_DS_CHANNELS       32
613 #define MADI_QS_CHANNELS       16
614 
615 #define RAYDAT_SS_CHANNELS     36
616 #define RAYDAT_DS_CHANNELS     20
617 #define RAYDAT_QS_CHANNELS     12
618 
619 #define AIO_IN_SS_CHANNELS        14
620 #define AIO_IN_DS_CHANNELS        10
621 #define AIO_IN_QS_CHANNELS        8
622 #define AIO_OUT_SS_CHANNELS        16
623 #define AIO_OUT_DS_CHANNELS        12
624 #define AIO_OUT_QS_CHANNELS        10
625 
626 #define AES32_CHANNELS		16
627 
628 /* the size of a substream (1 mono data stream) */
629 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
630 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
631 
632 /* the size of the area we need to allocate for DMA transfers. the
633    size is the same regardless of the number of channels, and
634    also the latency to use.
635    for one direction !!!
636 */
637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
639 
640 #define HDSPM_RAYDAT_REV	211
641 #define HDSPM_AIO_REV		212
642 #define HDSPM_MADIFACE_REV	213
643 
644 /* speed factor modes */
645 #define HDSPM_SPEED_SINGLE 0
646 #define HDSPM_SPEED_DOUBLE 1
647 #define HDSPM_SPEED_QUAD   2
648 
649 /* names for speed modes */
650 static char *hdspm_speed_names[] = { "single", "double", "quad" };
651 
652 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
653 					  "AES1", "AES2", "AES3", "AES4",
654 					  "AES5", "AES6", "AES7", "AES8",
655 					  "TCO", "Sync In"
656 };
657 static const char *const texts_autosync_aes[] = { "Word Clock",
658 				      "AES1", "AES2", "AES3", "AES4",
659 				      "AES5", "AES6", "AES7", "AES8",
660 				      "Sync In"
661 };
662 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
663 					   "MADI", "TCO", "Sync In" };
664 static const char *const texts_autosync_madi[] = { "Word Clock",
665 				       "MADI", "Sync In" };
666 
667 static const char *const texts_autosync_raydat_tco[] = {
668 	"Word Clock",
669 	"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
670 	"AES", "SPDIF", "TCO", "Sync In"
671 };
672 static const char *const texts_autosync_raydat[] = {
673 	"Word Clock",
674 	"ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
675 	"AES", "SPDIF", "Sync In"
676 };
677 static const char *const texts_autosync_aio_tco[] = {
678 	"Word Clock",
679 	"ADAT", "AES", "SPDIF", "TCO", "Sync In"
680 };
681 static const char *const texts_autosync_aio[] = { "Word Clock",
682 				      "ADAT", "AES", "SPDIF", "Sync In" };
683 
684 static const char *const texts_freq[] = {
685 	"No Lock",
686 	"32 kHz",
687 	"44.1 kHz",
688 	"48 kHz",
689 	"64 kHz",
690 	"88.2 kHz",
691 	"96 kHz",
692 	"128 kHz",
693 	"176.4 kHz",
694 	"192 kHz"
695 };
696 
697 static char *texts_ports_madi[] = {
698 	"MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
699 	"MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
700 	"MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
701 	"MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
702 	"MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
703 	"MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
704 	"MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
705 	"MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
706 	"MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
707 	"MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
708 	"MADI.61", "MADI.62", "MADI.63", "MADI.64",
709 };
710 
711 
712 static char *texts_ports_raydat_ss[] = {
713 	"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
714 	"ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715 	"ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
716 	"ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
717 	"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
718 	"ADAT4.7", "ADAT4.8",
719 	"AES.L", "AES.R",
720 	"SPDIF.L", "SPDIF.R"
721 };
722 
723 static char *texts_ports_raydat_ds[] = {
724 	"ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
725 	"ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
726 	"ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
727 	"ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
728 	"AES.L", "AES.R",
729 	"SPDIF.L", "SPDIF.R"
730 };
731 
732 static char *texts_ports_raydat_qs[] = {
733 	"ADAT1.1", "ADAT1.2",
734 	"ADAT2.1", "ADAT2.2",
735 	"ADAT3.1", "ADAT3.2",
736 	"ADAT4.1", "ADAT4.2",
737 	"AES.L", "AES.R",
738 	"SPDIF.L", "SPDIF.R"
739 };
740 
741 
742 static char *texts_ports_aio_in_ss[] = {
743 	"Analogue.L", "Analogue.R",
744 	"AES.L", "AES.R",
745 	"SPDIF.L", "SPDIF.R",
746 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
747 	"ADAT.7", "ADAT.8",
748 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
749 };
750 
751 static char *texts_ports_aio_out_ss[] = {
752 	"Analogue.L", "Analogue.R",
753 	"AES.L", "AES.R",
754 	"SPDIF.L", "SPDIF.R",
755 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
756 	"ADAT.7", "ADAT.8",
757 	"Phone.L", "Phone.R",
758 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
759 };
760 
761 static char *texts_ports_aio_in_ds[] = {
762 	"Analogue.L", "Analogue.R",
763 	"AES.L", "AES.R",
764 	"SPDIF.L", "SPDIF.R",
765 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
766 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
767 };
768 
769 static char *texts_ports_aio_out_ds[] = {
770 	"Analogue.L", "Analogue.R",
771 	"AES.L", "AES.R",
772 	"SPDIF.L", "SPDIF.R",
773 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
774 	"Phone.L", "Phone.R",
775 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
776 };
777 
778 static char *texts_ports_aio_in_qs[] = {
779 	"Analogue.L", "Analogue.R",
780 	"AES.L", "AES.R",
781 	"SPDIF.L", "SPDIF.R",
782 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
783 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
784 };
785 
786 static char *texts_ports_aio_out_qs[] = {
787 	"Analogue.L", "Analogue.R",
788 	"AES.L", "AES.R",
789 	"SPDIF.L", "SPDIF.R",
790 	"ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
791 	"Phone.L", "Phone.R",
792 	"AEB.1", "AEB.2", "AEB.3", "AEB.4"
793 };
794 
795 static char *texts_ports_aes32[] = {
796 	"AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
797 	"AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
798 	"AES.15", "AES.16"
799 };
800 
801 /* These tables map the ALSA channels 1..N to the channels that we
802    need to use in order to find the relevant channel buffer. RME
803    refers to this kind of mapping as between "the ADAT channel and
804    the DMA channel." We index it using the logical audio channel,
805    and the value is the DMA channel (i.e. channel buffer number)
806    where the data for that channel can be read/written from/to.
807 */
808 
809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
810 	0, 1, 2, 3, 4, 5, 6, 7,
811 	8, 9, 10, 11, 12, 13, 14, 15,
812 	16, 17, 18, 19, 20, 21, 22, 23,
813 	24, 25, 26, 27, 28, 29, 30, 31,
814 	32, 33, 34, 35, 36, 37, 38, 39,
815 	40, 41, 42, 43, 44, 45, 46, 47,
816 	48, 49, 50, 51, 52, 53, 54, 55,
817 	56, 57, 58, 59, 60, 61, 62, 63
818 };
819 
820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
821 	4, 5, 6, 7, 8, 9, 10, 11,	/* ADAT 1 */
822 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT 2 */
823 	20, 21, 22, 23, 24, 25, 26, 27,	/* ADAT 3 */
824 	28, 29, 30, 31, 32, 33, 34, 35,	/* ADAT 4 */
825 	0, 1,			/* AES */
826 	2, 3,			/* SPDIF */
827 	-1, -1, -1, -1,
828 	-1, -1, -1, -1, -1, -1, -1, -1,
829 	-1, -1, -1, -1, -1, -1, -1, -1,
830 	-1, -1, -1, -1, -1, -1, -1, -1,
831 };
832 
833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
834 	4, 5, 6, 7,		/* ADAT 1 */
835 	8, 9, 10, 11,		/* ADAT 2 */
836 	12, 13, 14, 15,		/* ADAT 3 */
837 	16, 17, 18, 19,		/* ADAT 4 */
838 	0, 1,			/* AES */
839 	2, 3,			/* SPDIF */
840 	-1, -1, -1, -1,
841 	-1, -1, -1, -1, -1, -1, -1, -1,
842 	-1, -1, -1, -1, -1, -1, -1, -1,
843 	-1, -1, -1, -1, -1, -1, -1, -1,
844 	-1, -1, -1, -1, -1, -1, -1, -1,
845 	-1, -1, -1, -1, -1, -1, -1, -1,
846 };
847 
848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
849 	4, 5,			/* ADAT 1 */
850 	6, 7,			/* ADAT 2 */
851 	8, 9,			/* ADAT 3 */
852 	10, 11,			/* ADAT 4 */
853 	0, 1,			/* AES */
854 	2, 3,			/* SPDIF */
855 	-1, -1, -1, -1,
856 	-1, -1, -1, -1, -1, -1, -1, -1,
857 	-1, -1, -1, -1, -1, -1, -1, -1,
858 	-1, -1, -1, -1, -1, -1, -1, -1,
859 	-1, -1, -1, -1, -1, -1, -1, -1,
860 	-1, -1, -1, -1, -1, -1, -1, -1,
861 	-1, -1, -1, -1, -1, -1, -1, -1,
862 };
863 
864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
865 	0, 1,			/* line in */
866 	8, 9,			/* aes in, */
867 	10, 11,			/* spdif in */
868 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT in */
869 	2, 3, 4, 5,		/* AEB */
870 	-1, -1, -1, -1, -1, -1,
871 	-1, -1, -1, -1, -1, -1, -1, -1,
872 	-1, -1, -1, -1, -1, -1, -1, -1,
873 	-1, -1, -1, -1, -1, -1, -1, -1,
874 	-1, -1, -1, -1, -1, -1, -1, -1,
875 	-1, -1, -1, -1, -1, -1, -1, -1,
876 };
877 
878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
879 	0, 1,			/* line out */
880 	8, 9,			/* aes out */
881 	10, 11,			/* spdif out */
882 	12, 13, 14, 15, 16, 17, 18, 19,	/* ADAT out */
883 	6, 7,			/* phone out */
884 	2, 3, 4, 5,		/* AEB */
885 	-1, -1, -1, -1,
886 	-1, -1, -1, -1, -1, -1, -1, -1,
887 	-1, -1, -1, -1, -1, -1, -1, -1,
888 	-1, -1, -1, -1, -1, -1, -1, -1,
889 	-1, -1, -1, -1, -1, -1, -1, -1,
890 	-1, -1, -1, -1, -1, -1, -1, -1,
891 };
892 
893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
894 	0, 1,			/* line in */
895 	8, 9,			/* aes in */
896 	10, 11,			/* spdif in */
897 	12, 14, 16, 18,		/* adat in */
898 	2, 3, 4, 5,		/* AEB */
899 	-1, -1,
900 	-1, -1, -1, -1, -1, -1, -1, -1,
901 	-1, -1, -1, -1, -1, -1, -1, -1,
902 	-1, -1, -1, -1, -1, -1, -1, -1,
903 	-1, -1, -1, -1, -1, -1, -1, -1,
904 	-1, -1, -1, -1, -1, -1, -1, -1,
905 	-1, -1, -1, -1, -1, -1, -1, -1
906 };
907 
908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
909 	0, 1,			/* line out */
910 	8, 9,			/* aes out */
911 	10, 11,			/* spdif out */
912 	12, 14, 16, 18,		/* adat out */
913 	6, 7,			/* phone out */
914 	2, 3, 4, 5,		/* AEB */
915 	-1, -1, -1, -1, -1, -1, -1, -1,
916 	-1, -1, -1, -1, -1, -1, -1, -1,
917 	-1, -1, -1, -1, -1, -1, -1, -1,
918 	-1, -1, -1, -1, -1, -1, -1, -1,
919 	-1, -1, -1, -1, -1, -1, -1, -1,
920 	-1, -1, -1, -1, -1, -1, -1, -1
921 };
922 
923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
924 	0, 1,			/* line in */
925 	8, 9,			/* aes in */
926 	10, 11,			/* spdif in */
927 	12, 16,			/* adat in */
928 	2, 3, 4, 5,		/* AEB */
929 	-1, -1, -1, -1,
930 	-1, -1, -1, -1, -1, -1, -1, -1,
931 	-1, -1, -1, -1, -1, -1, -1, -1,
932 	-1, -1, -1, -1, -1, -1, -1, -1,
933 	-1, -1, -1, -1, -1, -1, -1, -1,
934 	-1, -1, -1, -1, -1, -1, -1, -1,
935 	-1, -1, -1, -1, -1, -1, -1, -1
936 };
937 
938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
939 	0, 1,			/* line out */
940 	8, 9,			/* aes out */
941 	10, 11,			/* spdif out */
942 	12, 16,			/* adat out */
943 	6, 7,			/* phone out */
944 	2, 3, 4, 5,		/* AEB */
945 	-1, -1,
946 	-1, -1, -1, -1, -1, -1, -1, -1,
947 	-1, -1, -1, -1, -1, -1, -1, -1,
948 	-1, -1, -1, -1, -1, -1, -1, -1,
949 	-1, -1, -1, -1, -1, -1, -1, -1,
950 	-1, -1, -1, -1, -1, -1, -1, -1,
951 	-1, -1, -1, -1, -1, -1, -1, -1
952 };
953 
954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
955 	0, 1, 2, 3, 4, 5, 6, 7,
956 	8, 9, 10, 11, 12, 13, 14, 15,
957 	-1, -1, -1, -1, -1, -1, -1, -1,
958 	-1, -1, -1, -1, -1, -1, -1, -1,
959 	-1, -1, -1, -1, -1, -1, -1, -1,
960 	-1, -1, -1, -1, -1, -1, -1, -1,
961 	-1, -1, -1, -1, -1, -1, -1, -1,
962 	-1, -1, -1, -1, -1, -1, -1, -1
963 };
964 
965 struct hdspm_midi {
966 	struct hdspm *hdspm;
967 	int id;
968 	struct snd_rawmidi *rmidi;
969 	struct snd_rawmidi_substream *input;
970 	struct snd_rawmidi_substream *output;
971 	char istimer;		/* timer in use */
972 	struct timer_list timer;
973 	spinlock_t lock;
974 	int pending;
975 	int dataIn;
976 	int statusIn;
977 	int dataOut;
978 	int statusOut;
979 	int ie;
980 	int irq;
981 };
982 
983 struct hdspm_tco {
984 	int input; /* 0: LTC, 1:Video, 2: WC*/
985 	int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
986 	int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
987 	int samplerate; /* 0=44.1, 1=48, 2= freq from app */
988 	int pull; /*   0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
989 	int term; /* 0 = off, 1 = on */
990 };
991 
992 struct hdspm {
993         spinlock_t lock;
994 	/* only one playback and/or capture stream */
995         struct snd_pcm_substream *capture_substream;
996         struct snd_pcm_substream *playback_substream;
997 
998 	char *card_name;	     /* for procinfo */
999 	unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1000 
1001 	uint8_t io_type;
1002 
1003 	int monitor_outs;	/* set up monitoring outs init flag */
1004 
1005 	u32 control_register;	/* cached value */
1006 	u32 control2_register;	/* cached value */
1007 	u32 settings_register;  /* cached value for AIO / RayDat (sync reference, master/slave) */
1008 
1009 	struct hdspm_midi midi[4];
1010 	struct tasklet_struct midi_tasklet;
1011 
1012 	size_t period_bytes;
1013 	unsigned char ss_in_channels;
1014 	unsigned char ds_in_channels;
1015 	unsigned char qs_in_channels;
1016 	unsigned char ss_out_channels;
1017 	unsigned char ds_out_channels;
1018 	unsigned char qs_out_channels;
1019 
1020 	unsigned char max_channels_in;
1021 	unsigned char max_channels_out;
1022 
1023 	signed char *channel_map_in;
1024 	signed char *channel_map_out;
1025 
1026 	signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027 	signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1028 
1029 	char **port_names_in;
1030 	char **port_names_out;
1031 
1032 	char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033 	char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1034 
1035 	unsigned char *playback_buffer;	/* suitably aligned address */
1036 	unsigned char *capture_buffer;	/* suitably aligned address */
1037 
1038 	pid_t capture_pid;	/* process id which uses capture */
1039 	pid_t playback_pid;	/* process id which uses capture */
1040 	int running;		/* running status */
1041 
1042 	int last_external_sample_rate;	/* samplerate mystic ... */
1043 	int last_internal_sample_rate;
1044 	int system_sample_rate;
1045 
1046 	int dev;		/* Hardware vars... */
1047 	int irq;
1048 	unsigned long port;
1049 	void __iomem *iobase;
1050 
1051 	int irq_count;		/* for debug */
1052 	int midiPorts;
1053 
1054 	struct snd_card *card;	/* one card */
1055 	struct snd_pcm *pcm;		/* has one pcm */
1056 	struct snd_hwdep *hwdep;	/* and a hwdep for additional ioctl */
1057 	struct pci_dev *pci;	/* and an pci info */
1058 
1059 	/* Mixer vars */
1060 	/* fast alsa mixer */
1061 	struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062 	/* but input to much, so not used */
1063 	struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1064 	/* full mixer accessible over mixer ioctl or hwdep-device */
1065 	struct hdspm_mixer *mixer;
1066 
1067 	struct hdspm_tco *tco;  /* NULL if no TCO detected */
1068 
1069 	const char *const *texts_autosync;
1070 	int texts_autosync_items;
1071 
1072 	cycles_t last_interrupt;
1073 
1074 	unsigned int serial;
1075 
1076 	struct hdspm_peak_rms peak_rms;
1077 };
1078 
1079 
1080 static const struct pci_device_id snd_hdspm_ids[] = {
1081 	{
1082 	 .vendor = PCI_VENDOR_ID_XILINX,
1083 	 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084 	 .subvendor = PCI_ANY_ID,
1085 	 .subdevice = PCI_ANY_ID,
1086 	 .class = 0,
1087 	 .class_mask = 0,
1088 	 .driver_data = 0},
1089 	{0,}
1090 };
1091 
1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1093 
1094 /* prototypes */
1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096 					 struct hdspm *hdspm);
1097 static int snd_hdspm_create_pcm(struct snd_card *card,
1098 				struct hdspm *hdspm);
1099 
1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103 static int hdspm_autosync_ref(struct hdspm *hdspm);
1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1106 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1107 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1108 			    struct snd_pcm_substream *substream,
1109 			     unsigned int reg, int channels);
1110 
1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1115 
1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1119 
1120 
1121 
HDSPM_bit2freq(int n)1122 static inline int HDSPM_bit2freq(int n)
1123 {
1124 	static const int bit2freq_tab[] = {
1125 		0, 32000, 44100, 48000, 64000, 88200,
1126 		96000, 128000, 176400, 192000 };
1127 	if (n < 1 || n > 9)
1128 		return 0;
1129 	return bit2freq_tab[n];
1130 }
1131 
hdspm_is_raydat_or_aio(struct hdspm * hdspm)1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1133 {
1134 	return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1135 }
1136 
1137 
1138 /* Write/read to/from HDSPM with Adresses in Bytes
1139    not words but only 32Bit writes are allowed */
1140 
hdspm_write(struct hdspm * hdspm,unsigned int reg,unsigned int val)1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1142 			       unsigned int val)
1143 {
1144 	writel(val, hdspm->iobase + reg);
1145 }
1146 
hdspm_read(struct hdspm * hdspm,unsigned int reg)1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1148 {
1149 	return readl(hdspm->iobase + reg);
1150 }
1151 
1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153    mixer is write only on hardware so we have to cache him for read
1154    each fader is a u32, but uses only the first 16 bit */
1155 
hdspm_read_in_gain(struct hdspm * hdspm,unsigned int chan,unsigned int in)1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1157 				     unsigned int in)
1158 {
1159 	if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1160 		return 0;
1161 
1162 	return hdspm->mixer->ch[chan].in[in];
1163 }
1164 
hdspm_read_pb_gain(struct hdspm * hdspm,unsigned int chan,unsigned int pb)1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1166 				     unsigned int pb)
1167 {
1168 	if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1169 		return 0;
1170 	return hdspm->mixer->ch[chan].pb[pb];
1171 }
1172 
hdspm_write_in_gain(struct hdspm * hdspm,unsigned int chan,unsigned int in,unsigned short data)1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1174 				      unsigned int in, unsigned short data)
1175 {
1176 	if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1177 		return -1;
1178 
1179 	hdspm_write(hdspm,
1180 		    HDSPM_MADI_mixerBase +
1181 		    ((in + 128 * chan) * sizeof(u32)),
1182 		    (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183 	return 0;
1184 }
1185 
hdspm_write_pb_gain(struct hdspm * hdspm,unsigned int chan,unsigned int pb,unsigned short data)1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1187 				      unsigned int pb, unsigned short data)
1188 {
1189 	if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1190 		return -1;
1191 
1192 	hdspm_write(hdspm,
1193 		    HDSPM_MADI_mixerBase +
1194 		    ((64 + pb + 128 * chan) * sizeof(u32)),
1195 		    (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1196 	return 0;
1197 }
1198 
1199 
1200 /* enable DMA for specific channels, now available for DSP-MADI */
snd_hdspm_enable_in(struct hdspm * hdspm,int i,int v)1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1202 {
1203 	hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1204 }
1205 
snd_hdspm_enable_out(struct hdspm * hdspm,int i,int v)1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1207 {
1208 	hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1209 }
1210 
1211 /* check if same process is writing and reading */
snd_hdspm_use_is_exclusive(struct hdspm * hdspm)1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1213 {
1214 	unsigned long flags;
1215 	int ret = 1;
1216 
1217 	spin_lock_irqsave(&hdspm->lock, flags);
1218 	if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219 	    (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1220 		ret = 0;
1221 	}
1222 	spin_unlock_irqrestore(&hdspm->lock, flags);
1223 	return ret;
1224 }
1225 
1226 /* round arbitary sample rates to commonly known rates */
hdspm_round_frequency(int rate)1227 static int hdspm_round_frequency(int rate)
1228 {
1229 	if (rate < 38050)
1230 		return 32000;
1231 	if (rate < 46008)
1232 		return 44100;
1233 	else
1234 		return 48000;
1235 }
1236 
1237 /* QS and DS rates normally can not be detected
1238  * automatically by the card. Only exception is MADI
1239  * in 96k frame mode.
1240  *
1241  * So if we read SS values (32 .. 48k), check for
1242  * user-provided DS/QS bits in the control register
1243  * and multiply the base frequency accordingly.
1244  */
hdspm_rate_multiplier(struct hdspm * hdspm,int rate)1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1246 {
1247 	if (rate <= 48000) {
1248 		if (hdspm->control_register & HDSPM_QuadSpeed)
1249 			return rate * 4;
1250 		else if (hdspm->control_register &
1251 				HDSPM_DoubleSpeed)
1252 			return rate * 2;
1253 	}
1254 	return rate;
1255 }
1256 
1257 /* check for external sample rate, returns the sample rate in Hz*/
hdspm_external_sample_rate(struct hdspm * hdspm)1258 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1259 {
1260 	unsigned int status, status2;
1261 	int syncref, rate = 0, rate_bits;
1262 
1263 	switch (hdspm->io_type) {
1264 	case AES32:
1265 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1267 
1268 		syncref = hdspm_autosync_ref(hdspm);
1269 		switch (syncref) {
1270 		case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1271 		/* Check WC sync and get sample rate */
1272 			if (hdspm_wc_sync_check(hdspm))
1273 				return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1274 			break;
1275 
1276 		case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1277 		case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1278 		case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1279 		case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1280 		case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1281 		case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1282 		case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1283 		case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1284 		/* Check AES sync and get sample rate */
1285 			if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1286 				return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1287 							syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1288 			break;
1289 
1290 
1291 		case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1292 		/* Check TCO sync and get sample rate */
1293 			if (hdspm_tco_sync_check(hdspm))
1294 				return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1295 			break;
1296 		default:
1297 			return 0;
1298 		} /* end switch(syncref) */
1299 		break;
1300 
1301 	case MADIface:
1302 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1303 
1304 		if (!(status & HDSPM_madiLock)) {
1305 			rate = 0;  /* no lock */
1306 		} else {
1307 			switch (status & (HDSPM_status1_freqMask)) {
1308 			case HDSPM_status1_F_0*1:
1309 				rate = 32000; break;
1310 			case HDSPM_status1_F_0*2:
1311 				rate = 44100; break;
1312 			case HDSPM_status1_F_0*3:
1313 				rate = 48000; break;
1314 			case HDSPM_status1_F_0*4:
1315 				rate = 64000; break;
1316 			case HDSPM_status1_F_0*5:
1317 				rate = 88200; break;
1318 			case HDSPM_status1_F_0*6:
1319 				rate = 96000; break;
1320 			case HDSPM_status1_F_0*7:
1321 				rate = 128000; break;
1322 			case HDSPM_status1_F_0*8:
1323 				rate = 176400; break;
1324 			case HDSPM_status1_F_0*9:
1325 				rate = 192000; break;
1326 			default:
1327 				rate = 0; break;
1328 			}
1329 		}
1330 
1331 		break;
1332 
1333 	case MADI:
1334 	case AIO:
1335 	case RayDAT:
1336 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1337 		status = hdspm_read(hdspm, HDSPM_statusRegister);
1338 		rate = 0;
1339 
1340 		/* if wordclock has synced freq and wordclock is valid */
1341 		if ((status2 & HDSPM_wcLock) != 0 &&
1342 				(status2 & HDSPM_SelSyncRef0) == 0) {
1343 
1344 			rate_bits = status2 & HDSPM_wcFreqMask;
1345 
1346 
1347 			switch (rate_bits) {
1348 			case HDSPM_wcFreq32:
1349 				rate = 32000;
1350 				break;
1351 			case HDSPM_wcFreq44_1:
1352 				rate = 44100;
1353 				break;
1354 			case HDSPM_wcFreq48:
1355 				rate = 48000;
1356 				break;
1357 			case HDSPM_wcFreq64:
1358 				rate = 64000;
1359 				break;
1360 			case HDSPM_wcFreq88_2:
1361 				rate = 88200;
1362 				break;
1363 			case HDSPM_wcFreq96:
1364 				rate = 96000;
1365 				break;
1366 			case HDSPM_wcFreq128:
1367 				rate = 128000;
1368 				break;
1369 			case HDSPM_wcFreq176_4:
1370 				rate = 176400;
1371 				break;
1372 			case HDSPM_wcFreq192:
1373 				rate = 192000;
1374 				break;
1375 			default:
1376 				rate = 0;
1377 				break;
1378 			}
1379 		}
1380 
1381 		/* if rate detected and Syncref is Word than have it,
1382 		 * word has priority to MADI
1383 		 */
1384 		if (rate != 0 &&
1385 		(status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1386 			return hdspm_rate_multiplier(hdspm, rate);
1387 
1388 		/* maybe a madi input (which is taken if sel sync is madi) */
1389 		if (status & HDSPM_madiLock) {
1390 			rate_bits = status & HDSPM_madiFreqMask;
1391 
1392 			switch (rate_bits) {
1393 			case HDSPM_madiFreq32:
1394 				rate = 32000;
1395 				break;
1396 			case HDSPM_madiFreq44_1:
1397 				rate = 44100;
1398 				break;
1399 			case HDSPM_madiFreq48:
1400 				rate = 48000;
1401 				break;
1402 			case HDSPM_madiFreq64:
1403 				rate = 64000;
1404 				break;
1405 			case HDSPM_madiFreq88_2:
1406 				rate = 88200;
1407 				break;
1408 			case HDSPM_madiFreq96:
1409 				rate = 96000;
1410 				break;
1411 			case HDSPM_madiFreq128:
1412 				rate = 128000;
1413 				break;
1414 			case HDSPM_madiFreq176_4:
1415 				rate = 176400;
1416 				break;
1417 			case HDSPM_madiFreq192:
1418 				rate = 192000;
1419 				break;
1420 			default:
1421 				rate = 0;
1422 				break;
1423 			}
1424 
1425 		} /* endif HDSPM_madiLock */
1426 
1427 		/* check sample rate from TCO or SYNC_IN */
1428 		{
1429 			bool is_valid_input = 0;
1430 			bool has_sync = 0;
1431 
1432 			syncref = hdspm_autosync_ref(hdspm);
1433 			if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1434 				is_valid_input = 1;
1435 				has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1436 					hdspm_tco_sync_check(hdspm));
1437 			} else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1438 				is_valid_input = 1;
1439 				has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1440 					hdspm_sync_in_sync_check(hdspm));
1441 			}
1442 
1443 			if (is_valid_input && has_sync) {
1444 				rate = hdspm_round_frequency(
1445 					hdspm_get_pll_freq(hdspm));
1446 			}
1447 		}
1448 
1449 		rate = hdspm_rate_multiplier(hdspm, rate);
1450 
1451 		break;
1452 	}
1453 
1454 	return rate;
1455 }
1456 
1457 /* return latency in samples per period */
hdspm_get_latency(struct hdspm * hdspm)1458 static int hdspm_get_latency(struct hdspm *hdspm)
1459 {
1460 	int n;
1461 
1462 	n = hdspm_decode_latency(hdspm->control_register);
1463 
1464 	/* Special case for new RME cards with 32 samples period size.
1465 	 * The three latency bits in the control register
1466 	 * (HDSP_LatencyMask) encode latency values of 64 samples as
1467 	 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1468 	 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1469 	 * it corresponds to 32 samples.
1470 	 */
1471 	if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1472 		n = -1;
1473 
1474 	return 1 << (n + 6);
1475 }
1476 
1477 /* Latency function */
hdspm_compute_period_size(struct hdspm * hdspm)1478 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1479 {
1480 	hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1481 }
1482 
1483 
hdspm_hw_pointer(struct hdspm * hdspm)1484 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1485 {
1486 	int position;
1487 
1488 	position = hdspm_read(hdspm, HDSPM_statusRegister);
1489 
1490 	switch (hdspm->io_type) {
1491 	case RayDAT:
1492 	case AIO:
1493 		position &= HDSPM_BufferPositionMask;
1494 		position /= 4; /* Bytes per sample */
1495 		break;
1496 	default:
1497 		position = (position & HDSPM_BufferID) ?
1498 			(hdspm->period_bytes / 4) : 0;
1499 	}
1500 
1501 	return position;
1502 }
1503 
1504 
hdspm_start_audio(struct hdspm * s)1505 static inline void hdspm_start_audio(struct hdspm * s)
1506 {
1507 	s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1508 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1509 }
1510 
hdspm_stop_audio(struct hdspm * s)1511 static inline void hdspm_stop_audio(struct hdspm * s)
1512 {
1513 	s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1514 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1515 }
1516 
1517 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
hdspm_silence_playback(struct hdspm * hdspm)1518 static void hdspm_silence_playback(struct hdspm *hdspm)
1519 {
1520 	int i;
1521 	int n = hdspm->period_bytes;
1522 	void *buf = hdspm->playback_buffer;
1523 
1524 	if (buf == NULL)
1525 		return;
1526 
1527 	for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1528 		memset(buf, 0, n);
1529 		buf += HDSPM_CHANNEL_BUFFER_BYTES;
1530 	}
1531 }
1532 
hdspm_set_interrupt_interval(struct hdspm * s,unsigned int frames)1533 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1534 {
1535 	int n;
1536 
1537 	spin_lock_irq(&s->lock);
1538 
1539 	if (32 == frames) {
1540 		/* Special case for new RME cards like RayDAT/AIO which
1541 		 * support period sizes of 32 samples. Since latency is
1542 		 * encoded in the three bits of HDSP_LatencyMask, we can only
1543 		 * have values from 0 .. 7. While 0 still means 64 samples and
1544 		 * 6 represents 4096 samples on all cards, 7 represents 8192
1545 		 * on older cards and 32 samples on new cards.
1546 		 *
1547 		 * In other words, period size in samples is calculated by
1548 		 * 2^(n+6) with n ranging from 0 .. 7.
1549 		 */
1550 		n = 7;
1551 	} else {
1552 		frames >>= 7;
1553 		n = 0;
1554 		while (frames) {
1555 			n++;
1556 			frames >>= 1;
1557 		}
1558 	}
1559 
1560 	s->control_register &= ~HDSPM_LatencyMask;
1561 	s->control_register |= hdspm_encode_latency(n);
1562 
1563 	hdspm_write(s, HDSPM_controlRegister, s->control_register);
1564 
1565 	hdspm_compute_period_size(s);
1566 
1567 	spin_unlock_irq(&s->lock);
1568 
1569 	return 0;
1570 }
1571 
hdspm_calc_dds_value(struct hdspm * hdspm,u64 period)1572 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1573 {
1574 	u64 freq_const;
1575 
1576 	if (period == 0)
1577 		return 0;
1578 
1579 	switch (hdspm->io_type) {
1580 	case MADI:
1581 	case AES32:
1582 		freq_const = 110069313433624ULL;
1583 		break;
1584 	case RayDAT:
1585 	case AIO:
1586 		freq_const = 104857600000000ULL;
1587 		break;
1588 	case MADIface:
1589 		freq_const = 131072000000000ULL;
1590 		break;
1591 	default:
1592 		snd_BUG();
1593 		return 0;
1594 	}
1595 
1596 	return div_u64(freq_const, period);
1597 }
1598 
1599 
hdspm_set_dds_value(struct hdspm * hdspm,int rate)1600 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1601 {
1602 	u64 n;
1603 
1604 	if (snd_BUG_ON(rate <= 0))
1605 		return;
1606 
1607 	if (rate >= 112000)
1608 		rate /= 4;
1609 	else if (rate >= 56000)
1610 		rate /= 2;
1611 
1612 	switch (hdspm->io_type) {
1613 	case MADIface:
1614 		n = 131072000000000ULL;  /* 125 MHz */
1615 		break;
1616 	case MADI:
1617 	case AES32:
1618 		n = 110069313433624ULL;  /* 105 MHz */
1619 		break;
1620 	case RayDAT:
1621 	case AIO:
1622 		n = 104857600000000ULL;  /* 100 MHz */
1623 		break;
1624 	default:
1625 		snd_BUG();
1626 		return;
1627 	}
1628 
1629 	n = div_u64(n, rate);
1630 	/* n should be less than 2^32 for being written to FREQ register */
1631 	snd_BUG_ON(n >> 32);
1632 	hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1633 }
1634 
1635 /* dummy set rate lets see what happens */
hdspm_set_rate(struct hdspm * hdspm,int rate,int called_internally)1636 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1637 {
1638 	int current_rate;
1639 	int rate_bits;
1640 	int not_set = 0;
1641 	int current_speed, target_speed;
1642 
1643 	/* ASSUMPTION: hdspm->lock is either set, or there is no need for
1644 	   it (e.g. during module initialization).
1645 	 */
1646 
1647 	if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1648 
1649 		/* SLAVE --- */
1650 		if (called_internally) {
1651 
1652 			/* request from ctl or card initialization
1653 			   just make a warning an remember setting
1654 			   for future master mode switching */
1655 
1656 			dev_warn(hdspm->card->dev,
1657 				 "Warning: device is not running as a clock master.\n");
1658 			not_set = 1;
1659 		} else {
1660 
1661 			/* hw_param request while in AutoSync mode */
1662 			int external_freq =
1663 			    hdspm_external_sample_rate(hdspm);
1664 
1665 			if (hdspm_autosync_ref(hdspm) ==
1666 			    HDSPM_AUTOSYNC_FROM_NONE) {
1667 
1668 				dev_warn(hdspm->card->dev,
1669 					 "Detected no External Sync\n");
1670 				not_set = 1;
1671 
1672 			} else if (rate != external_freq) {
1673 
1674 				dev_warn(hdspm->card->dev,
1675 					 "Warning: No AutoSync source for requested rate\n");
1676 				not_set = 1;
1677 			}
1678 		}
1679 	}
1680 
1681 	current_rate = hdspm->system_sample_rate;
1682 
1683 	/* Changing between Singe, Double and Quad speed is not
1684 	   allowed if any substreams are open. This is because such a change
1685 	   causes a shift in the location of the DMA buffers and a reduction
1686 	   in the number of available buffers.
1687 
1688 	   Note that a similar but essentially insoluble problem exists for
1689 	   externally-driven rate changes. All we can do is to flag rate
1690 	   changes in the read/write routines.
1691 	 */
1692 
1693 	if (current_rate <= 48000)
1694 		current_speed = HDSPM_SPEED_SINGLE;
1695 	else if (current_rate <= 96000)
1696 		current_speed = HDSPM_SPEED_DOUBLE;
1697 	else
1698 		current_speed = HDSPM_SPEED_QUAD;
1699 
1700 	if (rate <= 48000)
1701 		target_speed = HDSPM_SPEED_SINGLE;
1702 	else if (rate <= 96000)
1703 		target_speed = HDSPM_SPEED_DOUBLE;
1704 	else
1705 		target_speed = HDSPM_SPEED_QUAD;
1706 
1707 	switch (rate) {
1708 	case 32000:
1709 		rate_bits = HDSPM_Frequency32KHz;
1710 		break;
1711 	case 44100:
1712 		rate_bits = HDSPM_Frequency44_1KHz;
1713 		break;
1714 	case 48000:
1715 		rate_bits = HDSPM_Frequency48KHz;
1716 		break;
1717 	case 64000:
1718 		rate_bits = HDSPM_Frequency64KHz;
1719 		break;
1720 	case 88200:
1721 		rate_bits = HDSPM_Frequency88_2KHz;
1722 		break;
1723 	case 96000:
1724 		rate_bits = HDSPM_Frequency96KHz;
1725 		break;
1726 	case 128000:
1727 		rate_bits = HDSPM_Frequency128KHz;
1728 		break;
1729 	case 176400:
1730 		rate_bits = HDSPM_Frequency176_4KHz;
1731 		break;
1732 	case 192000:
1733 		rate_bits = HDSPM_Frequency192KHz;
1734 		break;
1735 	default:
1736 		return -EINVAL;
1737 	}
1738 
1739 	if (current_speed != target_speed
1740 	    && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1741 		dev_err(hdspm->card->dev,
1742 			"cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1743 			hdspm_speed_names[current_speed],
1744 			hdspm_speed_names[target_speed],
1745 			hdspm->capture_pid, hdspm->playback_pid);
1746 		return -EBUSY;
1747 	}
1748 
1749 	hdspm->control_register &= ~HDSPM_FrequencyMask;
1750 	hdspm->control_register |= rate_bits;
1751 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1752 
1753 	/* For AES32, need to set DDS value in FREQ register
1754 	   For MADI, also apparently */
1755 	hdspm_set_dds_value(hdspm, rate);
1756 
1757 	if (AES32 == hdspm->io_type && rate != current_rate)
1758 		hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1759 
1760 	hdspm->system_sample_rate = rate;
1761 
1762 	if (rate <= 48000) {
1763 		hdspm->channel_map_in = hdspm->channel_map_in_ss;
1764 		hdspm->channel_map_out = hdspm->channel_map_out_ss;
1765 		hdspm->max_channels_in = hdspm->ss_in_channels;
1766 		hdspm->max_channels_out = hdspm->ss_out_channels;
1767 		hdspm->port_names_in = hdspm->port_names_in_ss;
1768 		hdspm->port_names_out = hdspm->port_names_out_ss;
1769 	} else if (rate <= 96000) {
1770 		hdspm->channel_map_in = hdspm->channel_map_in_ds;
1771 		hdspm->channel_map_out = hdspm->channel_map_out_ds;
1772 		hdspm->max_channels_in = hdspm->ds_in_channels;
1773 		hdspm->max_channels_out = hdspm->ds_out_channels;
1774 		hdspm->port_names_in = hdspm->port_names_in_ds;
1775 		hdspm->port_names_out = hdspm->port_names_out_ds;
1776 	} else {
1777 		hdspm->channel_map_in = hdspm->channel_map_in_qs;
1778 		hdspm->channel_map_out = hdspm->channel_map_out_qs;
1779 		hdspm->max_channels_in = hdspm->qs_in_channels;
1780 		hdspm->max_channels_out = hdspm->qs_out_channels;
1781 		hdspm->port_names_in = hdspm->port_names_in_qs;
1782 		hdspm->port_names_out = hdspm->port_names_out_qs;
1783 	}
1784 
1785 	if (not_set != 0)
1786 		return -1;
1787 
1788 	return 0;
1789 }
1790 
1791 /* mainly for init to 0 on load */
all_in_all_mixer(struct hdspm * hdspm,int sgain)1792 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1793 {
1794 	int i, j;
1795 	unsigned int gain;
1796 
1797 	if (sgain > UNITY_GAIN)
1798 		gain = UNITY_GAIN;
1799 	else if (sgain < 0)
1800 		gain = 0;
1801 	else
1802 		gain = sgain;
1803 
1804 	for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1805 		for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1806 			hdspm_write_in_gain(hdspm, i, j, gain);
1807 			hdspm_write_pb_gain(hdspm, i, j, gain);
1808 		}
1809 }
1810 
1811 /*----------------------------------------------------------------------------
1812    MIDI
1813   ----------------------------------------------------------------------------*/
1814 
snd_hdspm_midi_read_byte(struct hdspm * hdspm,int id)1815 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1816 						      int id)
1817 {
1818 	/* the hardware already does the relevant bit-mask with 0xff */
1819 	return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1820 }
1821 
snd_hdspm_midi_write_byte(struct hdspm * hdspm,int id,int val)1822 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1823 					      int val)
1824 {
1825 	/* the hardware already does the relevant bit-mask with 0xff */
1826 	return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1827 }
1828 
snd_hdspm_midi_input_available(struct hdspm * hdspm,int id)1829 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1830 {
1831 	return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1832 }
1833 
snd_hdspm_midi_output_possible(struct hdspm * hdspm,int id)1834 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1835 {
1836 	int fifo_bytes_used;
1837 
1838 	fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1839 
1840 	if (fifo_bytes_used < 128)
1841 		return  128 - fifo_bytes_used;
1842 	else
1843 		return 0;
1844 }
1845 
snd_hdspm_flush_midi_input(struct hdspm * hdspm,int id)1846 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1847 {
1848 	while (snd_hdspm_midi_input_available (hdspm, id))
1849 		snd_hdspm_midi_read_byte (hdspm, id);
1850 }
1851 
snd_hdspm_midi_output_write(struct hdspm_midi * hmidi)1852 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1853 {
1854 	unsigned long flags;
1855 	int n_pending;
1856 	int to_write;
1857 	int i;
1858 	unsigned char buf[128];
1859 
1860 	/* Output is not interrupt driven */
1861 
1862 	spin_lock_irqsave (&hmidi->lock, flags);
1863 	if (hmidi->output &&
1864 	    !snd_rawmidi_transmit_empty (hmidi->output)) {
1865 		n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1866 							    hmidi->id);
1867 		if (n_pending > 0) {
1868 			if (n_pending > (int)sizeof (buf))
1869 				n_pending = sizeof (buf);
1870 
1871 			to_write = snd_rawmidi_transmit (hmidi->output, buf,
1872 							 n_pending);
1873 			if (to_write > 0) {
1874 				for (i = 0; i < to_write; ++i)
1875 					snd_hdspm_midi_write_byte (hmidi->hdspm,
1876 								   hmidi->id,
1877 								   buf[i]);
1878 			}
1879 		}
1880 	}
1881 	spin_unlock_irqrestore (&hmidi->lock, flags);
1882 	return 0;
1883 }
1884 
snd_hdspm_midi_input_read(struct hdspm_midi * hmidi)1885 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1886 {
1887 	unsigned char buf[128]; /* this buffer is designed to match the MIDI
1888 				 * input FIFO size
1889 				 */
1890 	unsigned long flags;
1891 	int n_pending;
1892 	int i;
1893 
1894 	spin_lock_irqsave (&hmidi->lock, flags);
1895 	n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1896 	if (n_pending > 0) {
1897 		if (hmidi->input) {
1898 			if (n_pending > (int)sizeof (buf))
1899 				n_pending = sizeof (buf);
1900 			for (i = 0; i < n_pending; ++i)
1901 				buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1902 								   hmidi->id);
1903 			if (n_pending)
1904 				snd_rawmidi_receive (hmidi->input, buf,
1905 						     n_pending);
1906 		} else {
1907 			/* flush the MIDI input FIFO */
1908 			while (n_pending--)
1909 				snd_hdspm_midi_read_byte (hmidi->hdspm,
1910 							  hmidi->id);
1911 		}
1912 	}
1913 	hmidi->pending = 0;
1914 	spin_unlock_irqrestore(&hmidi->lock, flags);
1915 
1916 	spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1917 	hmidi->hdspm->control_register |= hmidi->ie;
1918 	hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1919 		    hmidi->hdspm->control_register);
1920 	spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1921 
1922 	return snd_hdspm_midi_output_write (hmidi);
1923 }
1924 
1925 static void
snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream * substream,int up)1926 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1927 {
1928 	struct hdspm *hdspm;
1929 	struct hdspm_midi *hmidi;
1930 	unsigned long flags;
1931 
1932 	hmidi = substream->rmidi->private_data;
1933 	hdspm = hmidi->hdspm;
1934 
1935 	spin_lock_irqsave (&hdspm->lock, flags);
1936 	if (up) {
1937 		if (!(hdspm->control_register & hmidi->ie)) {
1938 			snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1939 			hdspm->control_register |= hmidi->ie;
1940 		}
1941 	} else {
1942 		hdspm->control_register &= ~hmidi->ie;
1943 	}
1944 
1945 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1946 	spin_unlock_irqrestore (&hdspm->lock, flags);
1947 }
1948 
snd_hdspm_midi_output_timer(unsigned long data)1949 static void snd_hdspm_midi_output_timer(unsigned long data)
1950 {
1951 	struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1952 	unsigned long flags;
1953 
1954 	snd_hdspm_midi_output_write(hmidi);
1955 	spin_lock_irqsave (&hmidi->lock, flags);
1956 
1957 	/* this does not bump hmidi->istimer, because the
1958 	   kernel automatically removed the timer when it
1959 	   expired, and we are now adding it back, thus
1960 	   leaving istimer wherever it was set before.
1961 	*/
1962 
1963 	if (hmidi->istimer)
1964 		mod_timer(&hmidi->timer, 1 + jiffies);
1965 
1966 	spin_unlock_irqrestore (&hmidi->lock, flags);
1967 }
1968 
1969 static void
snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream * substream,int up)1970 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1971 {
1972 	struct hdspm_midi *hmidi;
1973 	unsigned long flags;
1974 
1975 	hmidi = substream->rmidi->private_data;
1976 	spin_lock_irqsave (&hmidi->lock, flags);
1977 	if (up) {
1978 		if (!hmidi->istimer) {
1979 			setup_timer(&hmidi->timer, snd_hdspm_midi_output_timer,
1980 				    (unsigned long) hmidi);
1981 			mod_timer(&hmidi->timer, 1 + jiffies);
1982 			hmidi->istimer++;
1983 		}
1984 	} else {
1985 		if (hmidi->istimer && --hmidi->istimer <= 0)
1986 			del_timer (&hmidi->timer);
1987 	}
1988 	spin_unlock_irqrestore (&hmidi->lock, flags);
1989 	if (up)
1990 		snd_hdspm_midi_output_write(hmidi);
1991 }
1992 
snd_hdspm_midi_input_open(struct snd_rawmidi_substream * substream)1993 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1994 {
1995 	struct hdspm_midi *hmidi;
1996 
1997 	hmidi = substream->rmidi->private_data;
1998 	spin_lock_irq (&hmidi->lock);
1999 	snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2000 	hmidi->input = substream;
2001 	spin_unlock_irq (&hmidi->lock);
2002 
2003 	return 0;
2004 }
2005 
snd_hdspm_midi_output_open(struct snd_rawmidi_substream * substream)2006 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2007 {
2008 	struct hdspm_midi *hmidi;
2009 
2010 	hmidi = substream->rmidi->private_data;
2011 	spin_lock_irq (&hmidi->lock);
2012 	hmidi->output = substream;
2013 	spin_unlock_irq (&hmidi->lock);
2014 
2015 	return 0;
2016 }
2017 
snd_hdspm_midi_input_close(struct snd_rawmidi_substream * substream)2018 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2019 {
2020 	struct hdspm_midi *hmidi;
2021 
2022 	snd_hdspm_midi_input_trigger (substream, 0);
2023 
2024 	hmidi = substream->rmidi->private_data;
2025 	spin_lock_irq (&hmidi->lock);
2026 	hmidi->input = NULL;
2027 	spin_unlock_irq (&hmidi->lock);
2028 
2029 	return 0;
2030 }
2031 
snd_hdspm_midi_output_close(struct snd_rawmidi_substream * substream)2032 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2033 {
2034 	struct hdspm_midi *hmidi;
2035 
2036 	snd_hdspm_midi_output_trigger (substream, 0);
2037 
2038 	hmidi = substream->rmidi->private_data;
2039 	spin_lock_irq (&hmidi->lock);
2040 	hmidi->output = NULL;
2041 	spin_unlock_irq (&hmidi->lock);
2042 
2043 	return 0;
2044 }
2045 
2046 static struct snd_rawmidi_ops snd_hdspm_midi_output =
2047 {
2048 	.open =		snd_hdspm_midi_output_open,
2049 	.close =	snd_hdspm_midi_output_close,
2050 	.trigger =	snd_hdspm_midi_output_trigger,
2051 };
2052 
2053 static struct snd_rawmidi_ops snd_hdspm_midi_input =
2054 {
2055 	.open =		snd_hdspm_midi_input_open,
2056 	.close =	snd_hdspm_midi_input_close,
2057 	.trigger =	snd_hdspm_midi_input_trigger,
2058 };
2059 
snd_hdspm_create_midi(struct snd_card * card,struct hdspm * hdspm,int id)2060 static int snd_hdspm_create_midi(struct snd_card *card,
2061 				 struct hdspm *hdspm, int id)
2062 {
2063 	int err;
2064 	char buf[32];
2065 
2066 	hdspm->midi[id].id = id;
2067 	hdspm->midi[id].hdspm = hdspm;
2068 	spin_lock_init (&hdspm->midi[id].lock);
2069 
2070 	if (0 == id) {
2071 		if (MADIface == hdspm->io_type) {
2072 			/* MIDI-over-MADI on HDSPe MADIface */
2073 			hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2074 			hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2075 			hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2076 			hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2077 			hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2078 			hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2079 		} else {
2080 			hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2081 			hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2082 			hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2083 			hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2084 			hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2085 			hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2086 		}
2087 	} else if (1 == id) {
2088 		hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2089 		hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2090 		hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2091 		hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2092 		hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2093 		hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2094 	} else if ((2 == id) && (MADI == hdspm->io_type)) {
2095 		/* MIDI-over-MADI on HDSPe MADI */
2096 		hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2097 		hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2098 		hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2099 		hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2100 		hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2101 		hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2102 	} else if (2 == id) {
2103 		/* TCO MTC, read only */
2104 		hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2105 		hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2106 		hdspm->midi[2].dataOut = -1;
2107 		hdspm->midi[2].statusOut = -1;
2108 		hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2109 		hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2110 	} else if (3 == id) {
2111 		/* TCO MTC on HDSPe MADI */
2112 		hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2113 		hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2114 		hdspm->midi[3].dataOut = -1;
2115 		hdspm->midi[3].statusOut = -1;
2116 		hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2117 		hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2118 	}
2119 
2120 	if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2121 					(MADIface == hdspm->io_type)))) {
2122 		if ((id == 0) && (MADIface == hdspm->io_type)) {
2123 			sprintf(buf, "%s MIDIoverMADI", card->shortname);
2124 		} else if ((id == 2) && (MADI == hdspm->io_type)) {
2125 			sprintf(buf, "%s MIDIoverMADI", card->shortname);
2126 		} else {
2127 			sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2128 		}
2129 		err = snd_rawmidi_new(card, buf, id, 1, 1,
2130 				&hdspm->midi[id].rmidi);
2131 		if (err < 0)
2132 			return err;
2133 
2134 		sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2135 				card->id, id+1);
2136 		hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2137 
2138 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2139 				SNDRV_RAWMIDI_STREAM_OUTPUT,
2140 				&snd_hdspm_midi_output);
2141 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2142 				SNDRV_RAWMIDI_STREAM_INPUT,
2143 				&snd_hdspm_midi_input);
2144 
2145 		hdspm->midi[id].rmidi->info_flags |=
2146 			SNDRV_RAWMIDI_INFO_OUTPUT |
2147 			SNDRV_RAWMIDI_INFO_INPUT |
2148 			SNDRV_RAWMIDI_INFO_DUPLEX;
2149 	} else {
2150 		/* TCO MTC, read only */
2151 		sprintf(buf, "%s MTC %d", card->shortname, id+1);
2152 		err = snd_rawmidi_new(card, buf, id, 1, 1,
2153 				&hdspm->midi[id].rmidi);
2154 		if (err < 0)
2155 			return err;
2156 
2157 		sprintf(hdspm->midi[id].rmidi->name,
2158 				"%s MTC %d", card->id, id+1);
2159 		hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2160 
2161 		snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2162 				SNDRV_RAWMIDI_STREAM_INPUT,
2163 				&snd_hdspm_midi_input);
2164 
2165 		hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2166 	}
2167 
2168 	return 0;
2169 }
2170 
2171 
hdspm_midi_tasklet(unsigned long arg)2172 static void hdspm_midi_tasklet(unsigned long arg)
2173 {
2174 	struct hdspm *hdspm = (struct hdspm *)arg;
2175 	int i = 0;
2176 
2177 	while (i < hdspm->midiPorts) {
2178 		if (hdspm->midi[i].pending)
2179 			snd_hdspm_midi_input_read(&hdspm->midi[i]);
2180 
2181 		i++;
2182 	}
2183 }
2184 
2185 
2186 /*-----------------------------------------------------------------------------
2187   Status Interface
2188   ----------------------------------------------------------------------------*/
2189 
2190 /* get the system sample rate which is set */
2191 
2192 
hdspm_get_pll_freq(struct hdspm * hdspm)2193 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2194 {
2195 	unsigned int period, rate;
2196 
2197 	period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2198 	rate = hdspm_calc_dds_value(hdspm, period);
2199 
2200 	return rate;
2201 }
2202 
2203 /*
2204  * Calculate the real sample rate from the
2205  * current DDS value.
2206  */
hdspm_get_system_sample_rate(struct hdspm * hdspm)2207 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2208 {
2209 	unsigned int rate;
2210 
2211 	rate = hdspm_get_pll_freq(hdspm);
2212 
2213 	if (rate > 207000) {
2214 		/* Unreasonable high sample rate as seen on PCI MADI cards. */
2215 		if (0 == hdspm_system_clock_mode(hdspm)) {
2216 			/* master mode, return internal sample rate */
2217 			rate = hdspm->system_sample_rate;
2218 		} else {
2219 			/* slave mode, return external sample rate */
2220 			rate = hdspm_external_sample_rate(hdspm);
2221 			if (!rate)
2222 				rate = hdspm->system_sample_rate;
2223 		}
2224 	}
2225 
2226 	return rate;
2227 }
2228 
2229 
2230 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2231 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2232 	.name = xname, \
2233 	.index = xindex, \
2234 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2235 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2236 	.info = snd_hdspm_info_system_sample_rate, \
2237 	.put = snd_hdspm_put_system_sample_rate, \
2238 	.get = snd_hdspm_get_system_sample_rate \
2239 }
2240 
snd_hdspm_info_system_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2241 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2242 					     struct snd_ctl_elem_info *uinfo)
2243 {
2244 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2245 	uinfo->count = 1;
2246 	uinfo->value.integer.min = 27000;
2247 	uinfo->value.integer.max = 207000;
2248 	uinfo->value.integer.step = 1;
2249 	return 0;
2250 }
2251 
2252 
snd_hdspm_get_system_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2253 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2254 					    struct snd_ctl_elem_value *
2255 					    ucontrol)
2256 {
2257 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2258 
2259 	ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2260 	return 0;
2261 }
2262 
snd_hdspm_put_system_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2263 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2264 					    struct snd_ctl_elem_value *
2265 					    ucontrol)
2266 {
2267 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2268 	int rate = ucontrol->value.integer.value[0];
2269 
2270 	if (rate < 27000 || rate > 207000)
2271 		return -EINVAL;
2272 	hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2273 	return 0;
2274 }
2275 
2276 
2277 /*
2278  * Returns the WordClock sample rate class for the given card.
2279  */
hdspm_get_wc_sample_rate(struct hdspm * hdspm)2280 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2281 {
2282 	int status;
2283 
2284 	switch (hdspm->io_type) {
2285 	case RayDAT:
2286 	case AIO:
2287 		status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2288 		return (status >> 16) & 0xF;
2289 		break;
2290 	case AES32:
2291 		status = hdspm_read(hdspm, HDSPM_statusRegister);
2292 		return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2293 	default:
2294 		break;
2295 	}
2296 
2297 
2298 	return 0;
2299 }
2300 
2301 
2302 /*
2303  * Returns the TCO sample rate class for the given card.
2304  */
hdspm_get_tco_sample_rate(struct hdspm * hdspm)2305 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2306 {
2307 	int status;
2308 
2309 	if (hdspm->tco) {
2310 		switch (hdspm->io_type) {
2311 		case RayDAT:
2312 		case AIO:
2313 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2314 			return (status >> 20) & 0xF;
2315 			break;
2316 		case AES32:
2317 			status = hdspm_read(hdspm, HDSPM_statusRegister);
2318 			return (status >> 1) & 0xF;
2319 		default:
2320 			break;
2321 		}
2322 	}
2323 
2324 	return 0;
2325 }
2326 
2327 
2328 /*
2329  * Returns the SYNC_IN sample rate class for the given card.
2330  */
hdspm_get_sync_in_sample_rate(struct hdspm * hdspm)2331 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2332 {
2333 	int status;
2334 
2335 	if (hdspm->tco) {
2336 		switch (hdspm->io_type) {
2337 		case RayDAT:
2338 		case AIO:
2339 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2340 			return (status >> 12) & 0xF;
2341 			break;
2342 		default:
2343 			break;
2344 		}
2345 	}
2346 
2347 	return 0;
2348 }
2349 
2350 /*
2351  * Returns the AES sample rate class for the given card.
2352  */
hdspm_get_aes_sample_rate(struct hdspm * hdspm,int index)2353 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2354 {
2355 	int timecode;
2356 
2357 	switch (hdspm->io_type) {
2358 	case AES32:
2359 		timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2360 		return (timecode >> (4*index)) & 0xF;
2361 		break;
2362 	default:
2363 		break;
2364 	}
2365 	return 0;
2366 }
2367 
2368 /*
2369  * Returns the sample rate class for input source <idx> for
2370  * 'new style' cards like the AIO and RayDAT.
2371  */
hdspm_get_s1_sample_rate(struct hdspm * hdspm,unsigned int idx)2372 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2373 {
2374 	int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2375 
2376 	return (status >> (idx*4)) & 0xF;
2377 }
2378 
2379 #define ENUMERATED_CTL_INFO(info, texts) \
2380 	snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2381 
2382 
2383 /* Helper function to query the external sample rate and return the
2384  * corresponding enum to be returned to userspace.
2385  */
hdspm_external_rate_to_enum(struct hdspm * hdspm)2386 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2387 {
2388 	int rate = hdspm_external_sample_rate(hdspm);
2389 	int i, selected_rate = 0;
2390 	for (i = 1; i < 10; i++)
2391 		if (HDSPM_bit2freq(i) == rate) {
2392 			selected_rate = i;
2393 			break;
2394 		}
2395 	return selected_rate;
2396 }
2397 
2398 
2399 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2400 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2401 	.name = xname, \
2402 	.private_value = xindex, \
2403 	.access = SNDRV_CTL_ELEM_ACCESS_READ, \
2404 	.info = snd_hdspm_info_autosync_sample_rate, \
2405 	.get = snd_hdspm_get_autosync_sample_rate \
2406 }
2407 
2408 
snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2409 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2410 					       struct snd_ctl_elem_info *uinfo)
2411 {
2412 	ENUMERATED_CTL_INFO(uinfo, texts_freq);
2413 	return 0;
2414 }
2415 
2416 
snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2417 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2418 					      struct snd_ctl_elem_value *
2419 					      ucontrol)
2420 {
2421 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2422 
2423 	switch (hdspm->io_type) {
2424 	case RayDAT:
2425 		switch (kcontrol->private_value) {
2426 		case 0:
2427 			ucontrol->value.enumerated.item[0] =
2428 				hdspm_get_wc_sample_rate(hdspm);
2429 			break;
2430 		case 7:
2431 			ucontrol->value.enumerated.item[0] =
2432 				hdspm_get_tco_sample_rate(hdspm);
2433 			break;
2434 		case 8:
2435 			ucontrol->value.enumerated.item[0] =
2436 				hdspm_get_sync_in_sample_rate(hdspm);
2437 			break;
2438 		default:
2439 			ucontrol->value.enumerated.item[0] =
2440 				hdspm_get_s1_sample_rate(hdspm,
2441 						kcontrol->private_value-1);
2442 		}
2443 		break;
2444 
2445 	case AIO:
2446 		switch (kcontrol->private_value) {
2447 		case 0: /* WC */
2448 			ucontrol->value.enumerated.item[0] =
2449 				hdspm_get_wc_sample_rate(hdspm);
2450 			break;
2451 		case 4: /* TCO */
2452 			ucontrol->value.enumerated.item[0] =
2453 				hdspm_get_tco_sample_rate(hdspm);
2454 			break;
2455 		case 5: /* SYNC_IN */
2456 			ucontrol->value.enumerated.item[0] =
2457 				hdspm_get_sync_in_sample_rate(hdspm);
2458 			break;
2459 		default:
2460 			ucontrol->value.enumerated.item[0] =
2461 				hdspm_get_s1_sample_rate(hdspm,
2462 						kcontrol->private_value-1);
2463 		}
2464 		break;
2465 
2466 	case AES32:
2467 
2468 		switch (kcontrol->private_value) {
2469 		case 0: /* WC */
2470 			ucontrol->value.enumerated.item[0] =
2471 				hdspm_get_wc_sample_rate(hdspm);
2472 			break;
2473 		case 9: /* TCO */
2474 			ucontrol->value.enumerated.item[0] =
2475 				hdspm_get_tco_sample_rate(hdspm);
2476 			break;
2477 		case 10: /* SYNC_IN */
2478 			ucontrol->value.enumerated.item[0] =
2479 				hdspm_get_sync_in_sample_rate(hdspm);
2480 			break;
2481 		case 11: /* External Rate */
2482 			ucontrol->value.enumerated.item[0] =
2483 				hdspm_external_rate_to_enum(hdspm);
2484 			break;
2485 		default: /* AES1 to AES8 */
2486 			ucontrol->value.enumerated.item[0] =
2487 				hdspm_get_aes_sample_rate(hdspm,
2488 						kcontrol->private_value -
2489 						HDSPM_AES32_AUTOSYNC_FROM_AES1);
2490 			break;
2491 		}
2492 		break;
2493 
2494 	case MADI:
2495 	case MADIface:
2496 		ucontrol->value.enumerated.item[0] =
2497 			hdspm_external_rate_to_enum(hdspm);
2498 		break;
2499 	default:
2500 		break;
2501 	}
2502 
2503 	return 0;
2504 }
2505 
2506 
2507 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2508 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2509 	.name = xname, \
2510 	.index = xindex, \
2511 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2512 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2513 	.info = snd_hdspm_info_system_clock_mode, \
2514 	.get = snd_hdspm_get_system_clock_mode, \
2515 	.put = snd_hdspm_put_system_clock_mode, \
2516 }
2517 
2518 
2519 /*
2520  * Returns the system clock mode for the given card.
2521  * @returns 0 - master, 1 - slave
2522  */
hdspm_system_clock_mode(struct hdspm * hdspm)2523 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2524 {
2525 	switch (hdspm->io_type) {
2526 	case AIO:
2527 	case RayDAT:
2528 		if (hdspm->settings_register & HDSPM_c0Master)
2529 			return 0;
2530 		break;
2531 
2532 	default:
2533 		if (hdspm->control_register & HDSPM_ClockModeMaster)
2534 			return 0;
2535 	}
2536 
2537 	return 1;
2538 }
2539 
2540 
2541 /*
2542  * Sets the system clock mode.
2543  * @param mode 0 - master, 1 - slave
2544  */
hdspm_set_system_clock_mode(struct hdspm * hdspm,int mode)2545 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2546 {
2547 	hdspm_set_toggle_setting(hdspm,
2548 			(hdspm_is_raydat_or_aio(hdspm)) ?
2549 			HDSPM_c0Master : HDSPM_ClockModeMaster,
2550 			(0 == mode));
2551 }
2552 
2553 
snd_hdspm_info_system_clock_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2554 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2555 					    struct snd_ctl_elem_info *uinfo)
2556 {
2557 	static const char *const texts[] = { "Master", "AutoSync" };
2558 	ENUMERATED_CTL_INFO(uinfo, texts);
2559 	return 0;
2560 }
2561 
snd_hdspm_get_system_clock_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2562 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2563 					   struct snd_ctl_elem_value *ucontrol)
2564 {
2565 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2566 
2567 	ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2568 	return 0;
2569 }
2570 
snd_hdspm_put_system_clock_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2571 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2572 					   struct snd_ctl_elem_value *ucontrol)
2573 {
2574 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2575 	int val;
2576 
2577 	if (!snd_hdspm_use_is_exclusive(hdspm))
2578 		return -EBUSY;
2579 
2580 	val = ucontrol->value.enumerated.item[0];
2581 	if (val < 0)
2582 		val = 0;
2583 	else if (val > 1)
2584 		val = 1;
2585 
2586 	hdspm_set_system_clock_mode(hdspm, val);
2587 
2588 	return 0;
2589 }
2590 
2591 
2592 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2593 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2594 	.name = xname, \
2595 	.index = xindex, \
2596 	.info = snd_hdspm_info_clock_source, \
2597 	.get = snd_hdspm_get_clock_source, \
2598 	.put = snd_hdspm_put_clock_source \
2599 }
2600 
2601 
hdspm_clock_source(struct hdspm * hdspm)2602 static int hdspm_clock_source(struct hdspm * hdspm)
2603 {
2604 	switch (hdspm->system_sample_rate) {
2605 	case 32000: return 0;
2606 	case 44100: return 1;
2607 	case 48000: return 2;
2608 	case 64000: return 3;
2609 	case 88200: return 4;
2610 	case 96000: return 5;
2611 	case 128000: return 6;
2612 	case 176400: return 7;
2613 	case 192000: return 8;
2614 	}
2615 
2616 	return -1;
2617 }
2618 
hdspm_set_clock_source(struct hdspm * hdspm,int mode)2619 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2620 {
2621 	int rate;
2622 	switch (mode) {
2623 	case 0:
2624 		rate = 32000; break;
2625 	case 1:
2626 		rate = 44100; break;
2627 	case 2:
2628 		rate = 48000; break;
2629 	case 3:
2630 		rate = 64000; break;
2631 	case 4:
2632 		rate = 88200; break;
2633 	case 5:
2634 		rate = 96000; break;
2635 	case 6:
2636 		rate = 128000; break;
2637 	case 7:
2638 		rate = 176400; break;
2639 	case 8:
2640 		rate = 192000; break;
2641 	default:
2642 		rate = 48000;
2643 	}
2644 	hdspm_set_rate(hdspm, rate, 1);
2645 	return 0;
2646 }
2647 
snd_hdspm_info_clock_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2648 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2649 				       struct snd_ctl_elem_info *uinfo)
2650 {
2651 	return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2652 }
2653 
snd_hdspm_get_clock_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2654 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2655 				      struct snd_ctl_elem_value *ucontrol)
2656 {
2657 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2658 
2659 	ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2660 	return 0;
2661 }
2662 
snd_hdspm_put_clock_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2663 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2664 				      struct snd_ctl_elem_value *ucontrol)
2665 {
2666 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2667 	int change;
2668 	int val;
2669 
2670 	if (!snd_hdspm_use_is_exclusive(hdspm))
2671 		return -EBUSY;
2672 	val = ucontrol->value.enumerated.item[0];
2673 	if (val < 0)
2674 		val = 0;
2675 	if (val > 9)
2676 		val = 9;
2677 	spin_lock_irq(&hdspm->lock);
2678 	if (val != hdspm_clock_source(hdspm))
2679 		change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2680 	else
2681 		change = 0;
2682 	spin_unlock_irq(&hdspm->lock);
2683 	return change;
2684 }
2685 
2686 
2687 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2688 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2689 	.name = xname, \
2690 	.index = xindex, \
2691 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2692 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2693 	.info = snd_hdspm_info_pref_sync_ref, \
2694 	.get = snd_hdspm_get_pref_sync_ref, \
2695 	.put = snd_hdspm_put_pref_sync_ref \
2696 }
2697 
2698 
2699 /*
2700  * Returns the current preferred sync reference setting.
2701  * The semantics of the return value are depending on the
2702  * card, please see the comments for clarification.
2703  */
hdspm_pref_sync_ref(struct hdspm * hdspm)2704 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2705 {
2706 	switch (hdspm->io_type) {
2707 	case AES32:
2708 		switch (hdspm->control_register & HDSPM_SyncRefMask) {
2709 		case 0: return 0;  /* WC */
2710 		case HDSPM_SyncRef0: return 1; /* AES 1 */
2711 		case HDSPM_SyncRef1: return 2; /* AES 2 */
2712 		case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2713 		case HDSPM_SyncRef2: return 4; /* AES 4 */
2714 		case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2715 		case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2716 		case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2717 						    return 7; /* AES 7 */
2718 		case HDSPM_SyncRef3: return 8; /* AES 8 */
2719 		case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2720 		}
2721 		break;
2722 
2723 	case MADI:
2724 	case MADIface:
2725 		if (hdspm->tco) {
2726 			switch (hdspm->control_register & HDSPM_SyncRefMask) {
2727 			case 0: return 0;  /* WC */
2728 			case HDSPM_SyncRef0: return 1;  /* MADI */
2729 			case HDSPM_SyncRef1: return 2;  /* TCO */
2730 			case HDSPM_SyncRef1+HDSPM_SyncRef0:
2731 					     return 3;  /* SYNC_IN */
2732 			}
2733 		} else {
2734 			switch (hdspm->control_register & HDSPM_SyncRefMask) {
2735 			case 0: return 0;  /* WC */
2736 			case HDSPM_SyncRef0: return 1;  /* MADI */
2737 			case HDSPM_SyncRef1+HDSPM_SyncRef0:
2738 					     return 2;  /* SYNC_IN */
2739 			}
2740 		}
2741 		break;
2742 
2743 	case RayDAT:
2744 		if (hdspm->tco) {
2745 			switch ((hdspm->settings_register &
2746 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2747 			case 0: return 0;  /* WC */
2748 			case 3: return 1;  /* ADAT 1 */
2749 			case 4: return 2;  /* ADAT 2 */
2750 			case 5: return 3;  /* ADAT 3 */
2751 			case 6: return 4;  /* ADAT 4 */
2752 			case 1: return 5;  /* AES */
2753 			case 2: return 6;  /* SPDIF */
2754 			case 9: return 7;  /* TCO */
2755 			case 10: return 8; /* SYNC_IN */
2756 			}
2757 		} else {
2758 			switch ((hdspm->settings_register &
2759 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2760 			case 0: return 0;  /* WC */
2761 			case 3: return 1;  /* ADAT 1 */
2762 			case 4: return 2;  /* ADAT 2 */
2763 			case 5: return 3;  /* ADAT 3 */
2764 			case 6: return 4;  /* ADAT 4 */
2765 			case 1: return 5;  /* AES */
2766 			case 2: return 6;  /* SPDIF */
2767 			case 10: return 7; /* SYNC_IN */
2768 			}
2769 		}
2770 
2771 		break;
2772 
2773 	case AIO:
2774 		if (hdspm->tco) {
2775 			switch ((hdspm->settings_register &
2776 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2777 			case 0: return 0;  /* WC */
2778 			case 3: return 1;  /* ADAT */
2779 			case 1: return 2;  /* AES */
2780 			case 2: return 3;  /* SPDIF */
2781 			case 9: return 4;  /* TCO */
2782 			case 10: return 5; /* SYNC_IN */
2783 			}
2784 		} else {
2785 			switch ((hdspm->settings_register &
2786 				HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2787 			case 0: return 0;  /* WC */
2788 			case 3: return 1;  /* ADAT */
2789 			case 1: return 2;  /* AES */
2790 			case 2: return 3;  /* SPDIF */
2791 			case 10: return 4; /* SYNC_IN */
2792 			}
2793 		}
2794 
2795 		break;
2796 	}
2797 
2798 	return -1;
2799 }
2800 
2801 
2802 /*
2803  * Set the preferred sync reference to <pref>. The semantics
2804  * of <pref> are depending on the card type, see the comments
2805  * for clarification.
2806  */
hdspm_set_pref_sync_ref(struct hdspm * hdspm,int pref)2807 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2808 {
2809 	int p = 0;
2810 
2811 	switch (hdspm->io_type) {
2812 	case AES32:
2813 		hdspm->control_register &= ~HDSPM_SyncRefMask;
2814 		switch (pref) {
2815 		case 0: /* WC  */
2816 			break;
2817 		case 1: /* AES 1 */
2818 			hdspm->control_register |= HDSPM_SyncRef0;
2819 			break;
2820 		case 2: /* AES 2 */
2821 			hdspm->control_register |= HDSPM_SyncRef1;
2822 			break;
2823 		case 3: /* AES 3 */
2824 			hdspm->control_register |=
2825 				HDSPM_SyncRef1+HDSPM_SyncRef0;
2826 			break;
2827 		case 4: /* AES 4 */
2828 			hdspm->control_register |= HDSPM_SyncRef2;
2829 			break;
2830 		case 5: /* AES 5 */
2831 			hdspm->control_register |=
2832 				HDSPM_SyncRef2+HDSPM_SyncRef0;
2833 			break;
2834 		case 6: /* AES 6 */
2835 			hdspm->control_register |=
2836 				HDSPM_SyncRef2+HDSPM_SyncRef1;
2837 			break;
2838 		case 7: /* AES 7 */
2839 			hdspm->control_register |=
2840 				HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2841 			break;
2842 		case 8: /* AES 8 */
2843 			hdspm->control_register |= HDSPM_SyncRef3;
2844 			break;
2845 		case 9: /* TCO */
2846 			hdspm->control_register |=
2847 				HDSPM_SyncRef3+HDSPM_SyncRef0;
2848 			break;
2849 		default:
2850 			return -1;
2851 		}
2852 
2853 		break;
2854 
2855 	case MADI:
2856 	case MADIface:
2857 		hdspm->control_register &= ~HDSPM_SyncRefMask;
2858 		if (hdspm->tco) {
2859 			switch (pref) {
2860 			case 0: /* WC */
2861 				break;
2862 			case 1: /* MADI */
2863 				hdspm->control_register |= HDSPM_SyncRef0;
2864 				break;
2865 			case 2: /* TCO */
2866 				hdspm->control_register |= HDSPM_SyncRef1;
2867 				break;
2868 			case 3: /* SYNC_IN */
2869 				hdspm->control_register |=
2870 					HDSPM_SyncRef0+HDSPM_SyncRef1;
2871 				break;
2872 			default:
2873 				return -1;
2874 			}
2875 		} else {
2876 			switch (pref) {
2877 			case 0: /* WC */
2878 				break;
2879 			case 1: /* MADI */
2880 				hdspm->control_register |= HDSPM_SyncRef0;
2881 				break;
2882 			case 2: /* SYNC_IN */
2883 				hdspm->control_register |=
2884 					HDSPM_SyncRef0+HDSPM_SyncRef1;
2885 				break;
2886 			default:
2887 				return -1;
2888 			}
2889 		}
2890 
2891 		break;
2892 
2893 	case RayDAT:
2894 		if (hdspm->tco) {
2895 			switch (pref) {
2896 			case 0: p = 0; break;  /* WC */
2897 			case 1: p = 3; break;  /* ADAT 1 */
2898 			case 2: p = 4; break;  /* ADAT 2 */
2899 			case 3: p = 5; break;  /* ADAT 3 */
2900 			case 4: p = 6; break;  /* ADAT 4 */
2901 			case 5: p = 1; break;  /* AES */
2902 			case 6: p = 2; break;  /* SPDIF */
2903 			case 7: p = 9; break;  /* TCO */
2904 			case 8: p = 10; break; /* SYNC_IN */
2905 			default: return -1;
2906 			}
2907 		} else {
2908 			switch (pref) {
2909 			case 0: p = 0; break;  /* WC */
2910 			case 1: p = 3; break;  /* ADAT 1 */
2911 			case 2: p = 4; break;  /* ADAT 2 */
2912 			case 3: p = 5; break;  /* ADAT 3 */
2913 			case 4: p = 6; break;  /* ADAT 4 */
2914 			case 5: p = 1; break;  /* AES */
2915 			case 6: p = 2; break;  /* SPDIF */
2916 			case 7: p = 10; break; /* SYNC_IN */
2917 			default: return -1;
2918 			}
2919 		}
2920 		break;
2921 
2922 	case AIO:
2923 		if (hdspm->tco) {
2924 			switch (pref) {
2925 			case 0: p = 0; break;  /* WC */
2926 			case 1: p = 3; break;  /* ADAT */
2927 			case 2: p = 1; break;  /* AES */
2928 			case 3: p = 2; break;  /* SPDIF */
2929 			case 4: p = 9; break;  /* TCO */
2930 			case 5: p = 10; break; /* SYNC_IN */
2931 			default: return -1;
2932 			}
2933 		} else {
2934 			switch (pref) {
2935 			case 0: p = 0; break;  /* WC */
2936 			case 1: p = 3; break;  /* ADAT */
2937 			case 2: p = 1; break;  /* AES */
2938 			case 3: p = 2; break;  /* SPDIF */
2939 			case 4: p = 10; break; /* SYNC_IN */
2940 			default: return -1;
2941 			}
2942 		}
2943 		break;
2944 	}
2945 
2946 	switch (hdspm->io_type) {
2947 	case RayDAT:
2948 	case AIO:
2949 		hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2950 		hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2951 		hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2952 		break;
2953 
2954 	case MADI:
2955 	case MADIface:
2956 	case AES32:
2957 		hdspm_write(hdspm, HDSPM_controlRegister,
2958 				hdspm->control_register);
2959 	}
2960 
2961 	return 0;
2962 }
2963 
2964 
snd_hdspm_info_pref_sync_ref(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2965 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2966 					struct snd_ctl_elem_info *uinfo)
2967 {
2968 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2969 
2970 	snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2971 
2972 	return 0;
2973 }
2974 
snd_hdspm_get_pref_sync_ref(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2975 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2976 				       struct snd_ctl_elem_value *ucontrol)
2977 {
2978 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2979 	int psf = hdspm_pref_sync_ref(hdspm);
2980 
2981 	if (psf >= 0) {
2982 		ucontrol->value.enumerated.item[0] = psf;
2983 		return 0;
2984 	}
2985 
2986 	return -1;
2987 }
2988 
snd_hdspm_put_pref_sync_ref(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2989 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2990 				       struct snd_ctl_elem_value *ucontrol)
2991 {
2992 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2993 	int val, change = 0;
2994 
2995 	if (!snd_hdspm_use_is_exclusive(hdspm))
2996 		return -EBUSY;
2997 
2998 	val = ucontrol->value.enumerated.item[0];
2999 
3000 	if (val < 0)
3001 		val = 0;
3002 	else if (val >= hdspm->texts_autosync_items)
3003 		val = hdspm->texts_autosync_items-1;
3004 
3005 	spin_lock_irq(&hdspm->lock);
3006 	if (val != hdspm_pref_sync_ref(hdspm))
3007 		change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3008 
3009 	spin_unlock_irq(&hdspm->lock);
3010 	return change;
3011 }
3012 
3013 
3014 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3015 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3016 	.name = xname, \
3017 	.index = xindex, \
3018 	.access = SNDRV_CTL_ELEM_ACCESS_READ, \
3019 	.info = snd_hdspm_info_autosync_ref, \
3020 	.get = snd_hdspm_get_autosync_ref, \
3021 }
3022 
hdspm_autosync_ref(struct hdspm * hdspm)3023 static int hdspm_autosync_ref(struct hdspm *hdspm)
3024 {
3025 	/* This looks at the autosync selected sync reference */
3026 	if (AES32 == hdspm->io_type) {
3027 
3028 		unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3029 		unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3030 		if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3031 				(syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3032 			return syncref;
3033 		}
3034 		return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3035 
3036 	} else if (MADI == hdspm->io_type) {
3037 
3038 		unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3039 		switch (status2 & HDSPM_SelSyncRefMask) {
3040 		case HDSPM_SelSyncRef_WORD:
3041 			return HDSPM_AUTOSYNC_FROM_WORD;
3042 		case HDSPM_SelSyncRef_MADI:
3043 			return HDSPM_AUTOSYNC_FROM_MADI;
3044 		case HDSPM_SelSyncRef_TCO:
3045 			return HDSPM_AUTOSYNC_FROM_TCO;
3046 		case HDSPM_SelSyncRef_SyncIn:
3047 			return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3048 		case HDSPM_SelSyncRef_NVALID:
3049 			return HDSPM_AUTOSYNC_FROM_NONE;
3050 		default:
3051 			return HDSPM_AUTOSYNC_FROM_NONE;
3052 		}
3053 
3054 	}
3055 	return 0;
3056 }
3057 
3058 
snd_hdspm_info_autosync_ref(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3059 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3060 				       struct snd_ctl_elem_info *uinfo)
3061 {
3062 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3063 
3064 	if (AES32 == hdspm->io_type) {
3065 		static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3066 			"AES4",	"AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3067 
3068 		ENUMERATED_CTL_INFO(uinfo, texts);
3069 	} else if (MADI == hdspm->io_type) {
3070 		static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3071 			"Sync In", "None" };
3072 
3073 		ENUMERATED_CTL_INFO(uinfo, texts);
3074 	}
3075 	return 0;
3076 }
3077 
snd_hdspm_get_autosync_ref(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3078 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3079 				      struct snd_ctl_elem_value *ucontrol)
3080 {
3081 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3082 
3083 	ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3084 	return 0;
3085 }
3086 
3087 
3088 
3089 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3090 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3091 	.name = xname, \
3092 	.access = SNDRV_CTL_ELEM_ACCESS_READ |\
3093 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3094 	.info = snd_hdspm_info_tco_video_input_format, \
3095 	.get = snd_hdspm_get_tco_video_input_format, \
3096 }
3097 
snd_hdspm_info_tco_video_input_format(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3098 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3099 				       struct snd_ctl_elem_info *uinfo)
3100 {
3101 	static const char *const texts[] = {"No video", "NTSC", "PAL"};
3102 	ENUMERATED_CTL_INFO(uinfo, texts);
3103 	return 0;
3104 }
3105 
snd_hdspm_get_tco_video_input_format(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3106 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3107 				      struct snd_ctl_elem_value *ucontrol)
3108 {
3109 	u32 status;
3110 	int ret = 0;
3111 
3112 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3113 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3114 	switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3115 			HDSPM_TCO1_Video_Input_Format_PAL)) {
3116 	case HDSPM_TCO1_Video_Input_Format_NTSC:
3117 		/* ntsc */
3118 		ret = 1;
3119 		break;
3120 	case HDSPM_TCO1_Video_Input_Format_PAL:
3121 		/* pal */
3122 		ret = 2;
3123 		break;
3124 	default:
3125 		/* no video */
3126 		ret = 0;
3127 		break;
3128 	}
3129 	ucontrol->value.enumerated.item[0] = ret;
3130 	return 0;
3131 }
3132 
3133 
3134 
3135 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3136 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3137 	.name = xname, \
3138 	.access = SNDRV_CTL_ELEM_ACCESS_READ |\
3139 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3140 	.info = snd_hdspm_info_tco_ltc_frames, \
3141 	.get = snd_hdspm_get_tco_ltc_frames, \
3142 }
3143 
snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3144 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3145 				       struct snd_ctl_elem_info *uinfo)
3146 {
3147 	static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3148 				"30 fps"};
3149 	ENUMERATED_CTL_INFO(uinfo, texts);
3150 	return 0;
3151 }
3152 
hdspm_tco_ltc_frames(struct hdspm * hdspm)3153 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3154 {
3155 	u32 status;
3156 	int ret = 0;
3157 
3158 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3159 	if (status & HDSPM_TCO1_LTC_Input_valid) {
3160 		switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3161 					HDSPM_TCO1_LTC_Format_MSB)) {
3162 		case 0:
3163 			/* 24 fps */
3164 			ret = fps_24;
3165 			break;
3166 		case HDSPM_TCO1_LTC_Format_LSB:
3167 			/* 25 fps */
3168 			ret = fps_25;
3169 			break;
3170 		case HDSPM_TCO1_LTC_Format_MSB:
3171 			/* 29.97 fps */
3172 			ret = fps_2997;
3173 			break;
3174 		default:
3175 			/* 30 fps */
3176 			ret = fps_30;
3177 			break;
3178 		}
3179 	}
3180 
3181 	return ret;
3182 }
3183 
snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3184 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3185 				      struct snd_ctl_elem_value *ucontrol)
3186 {
3187 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3188 
3189 	ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3190 	return 0;
3191 }
3192 
3193 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3194 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3195 	.name = xname, \
3196 	.private_value = xindex, \
3197 	.info = snd_hdspm_info_toggle_setting, \
3198 	.get = snd_hdspm_get_toggle_setting, \
3199 	.put = snd_hdspm_put_toggle_setting \
3200 }
3201 
hdspm_toggle_setting(struct hdspm * hdspm,u32 regmask)3202 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3203 {
3204 	u32 reg;
3205 
3206 	if (hdspm_is_raydat_or_aio(hdspm))
3207 		reg = hdspm->settings_register;
3208 	else
3209 		reg = hdspm->control_register;
3210 
3211 	return (reg & regmask) ? 1 : 0;
3212 }
3213 
hdspm_set_toggle_setting(struct hdspm * hdspm,u32 regmask,int out)3214 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3215 {
3216 	u32 *reg;
3217 	u32 target_reg;
3218 
3219 	if (hdspm_is_raydat_or_aio(hdspm)) {
3220 		reg = &(hdspm->settings_register);
3221 		target_reg = HDSPM_WR_SETTINGS;
3222 	} else {
3223 		reg = &(hdspm->control_register);
3224 		target_reg = HDSPM_controlRegister;
3225 	}
3226 
3227 	if (out)
3228 		*reg |= regmask;
3229 	else
3230 		*reg &= ~regmask;
3231 
3232 	hdspm_write(hdspm, target_reg, *reg);
3233 
3234 	return 0;
3235 }
3236 
3237 #define snd_hdspm_info_toggle_setting		snd_ctl_boolean_mono_info
3238 
snd_hdspm_get_toggle_setting(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3239 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3240 			       struct snd_ctl_elem_value *ucontrol)
3241 {
3242 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3243 	u32 regmask = kcontrol->private_value;
3244 
3245 	spin_lock_irq(&hdspm->lock);
3246 	ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3247 	spin_unlock_irq(&hdspm->lock);
3248 	return 0;
3249 }
3250 
snd_hdspm_put_toggle_setting(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3251 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3252 			       struct snd_ctl_elem_value *ucontrol)
3253 {
3254 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3255 	u32 regmask = kcontrol->private_value;
3256 	int change;
3257 	unsigned int val;
3258 
3259 	if (!snd_hdspm_use_is_exclusive(hdspm))
3260 		return -EBUSY;
3261 	val = ucontrol->value.integer.value[0] & 1;
3262 	spin_lock_irq(&hdspm->lock);
3263 	change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3264 	hdspm_set_toggle_setting(hdspm, regmask, val);
3265 	spin_unlock_irq(&hdspm->lock);
3266 	return change;
3267 }
3268 
3269 #define HDSPM_INPUT_SELECT(xname, xindex) \
3270 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3271 	.name = xname, \
3272 	.index = xindex, \
3273 	.info = snd_hdspm_info_input_select, \
3274 	.get = snd_hdspm_get_input_select, \
3275 	.put = snd_hdspm_put_input_select \
3276 }
3277 
hdspm_input_select(struct hdspm * hdspm)3278 static int hdspm_input_select(struct hdspm * hdspm)
3279 {
3280 	return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3281 }
3282 
hdspm_set_input_select(struct hdspm * hdspm,int out)3283 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3284 {
3285 	if (out)
3286 		hdspm->control_register |= HDSPM_InputSelect0;
3287 	else
3288 		hdspm->control_register &= ~HDSPM_InputSelect0;
3289 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3290 
3291 	return 0;
3292 }
3293 
snd_hdspm_info_input_select(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3294 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3295 				       struct snd_ctl_elem_info *uinfo)
3296 {
3297 	static const char *const texts[] = { "optical", "coaxial" };
3298 	ENUMERATED_CTL_INFO(uinfo, texts);
3299 	return 0;
3300 }
3301 
snd_hdspm_get_input_select(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3302 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3303 				      struct snd_ctl_elem_value *ucontrol)
3304 {
3305 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3306 
3307 	spin_lock_irq(&hdspm->lock);
3308 	ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3309 	spin_unlock_irq(&hdspm->lock);
3310 	return 0;
3311 }
3312 
snd_hdspm_put_input_select(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3313 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3314 				      struct snd_ctl_elem_value *ucontrol)
3315 {
3316 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3317 	int change;
3318 	unsigned int val;
3319 
3320 	if (!snd_hdspm_use_is_exclusive(hdspm))
3321 		return -EBUSY;
3322 	val = ucontrol->value.integer.value[0] & 1;
3323 	spin_lock_irq(&hdspm->lock);
3324 	change = (int) val != hdspm_input_select(hdspm);
3325 	hdspm_set_input_select(hdspm, val);
3326 	spin_unlock_irq(&hdspm->lock);
3327 	return change;
3328 }
3329 
3330 
3331 #define HDSPM_DS_WIRE(xname, xindex) \
3332 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3333 	.name = xname, \
3334 	.index = xindex, \
3335 	.info = snd_hdspm_info_ds_wire, \
3336 	.get = snd_hdspm_get_ds_wire, \
3337 	.put = snd_hdspm_put_ds_wire \
3338 }
3339 
hdspm_ds_wire(struct hdspm * hdspm)3340 static int hdspm_ds_wire(struct hdspm * hdspm)
3341 {
3342 	return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3343 }
3344 
hdspm_set_ds_wire(struct hdspm * hdspm,int ds)3345 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3346 {
3347 	if (ds)
3348 		hdspm->control_register |= HDSPM_DS_DoubleWire;
3349 	else
3350 		hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3351 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3352 
3353 	return 0;
3354 }
3355 
snd_hdspm_info_ds_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3356 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3357 				  struct snd_ctl_elem_info *uinfo)
3358 {
3359 	static const char *const texts[] = { "Single", "Double" };
3360 	ENUMERATED_CTL_INFO(uinfo, texts);
3361 	return 0;
3362 }
3363 
snd_hdspm_get_ds_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3364 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3365 				 struct snd_ctl_elem_value *ucontrol)
3366 {
3367 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3368 
3369 	spin_lock_irq(&hdspm->lock);
3370 	ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3371 	spin_unlock_irq(&hdspm->lock);
3372 	return 0;
3373 }
3374 
snd_hdspm_put_ds_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3375 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3376 				 struct snd_ctl_elem_value *ucontrol)
3377 {
3378 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3379 	int change;
3380 	unsigned int val;
3381 
3382 	if (!snd_hdspm_use_is_exclusive(hdspm))
3383 		return -EBUSY;
3384 	val = ucontrol->value.integer.value[0] & 1;
3385 	spin_lock_irq(&hdspm->lock);
3386 	change = (int) val != hdspm_ds_wire(hdspm);
3387 	hdspm_set_ds_wire(hdspm, val);
3388 	spin_unlock_irq(&hdspm->lock);
3389 	return change;
3390 }
3391 
3392 
3393 #define HDSPM_QS_WIRE(xname, xindex) \
3394 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3395 	.name = xname, \
3396 	.index = xindex, \
3397 	.info = snd_hdspm_info_qs_wire, \
3398 	.get = snd_hdspm_get_qs_wire, \
3399 	.put = snd_hdspm_put_qs_wire \
3400 }
3401 
hdspm_qs_wire(struct hdspm * hdspm)3402 static int hdspm_qs_wire(struct hdspm * hdspm)
3403 {
3404 	if (hdspm->control_register & HDSPM_QS_DoubleWire)
3405 		return 1;
3406 	if (hdspm->control_register & HDSPM_QS_QuadWire)
3407 		return 2;
3408 	return 0;
3409 }
3410 
hdspm_set_qs_wire(struct hdspm * hdspm,int mode)3411 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3412 {
3413 	hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3414 	switch (mode) {
3415 	case 0:
3416 		break;
3417 	case 1:
3418 		hdspm->control_register |= HDSPM_QS_DoubleWire;
3419 		break;
3420 	case 2:
3421 		hdspm->control_register |= HDSPM_QS_QuadWire;
3422 		break;
3423 	}
3424 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3425 
3426 	return 0;
3427 }
3428 
snd_hdspm_info_qs_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3429 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3430 				       struct snd_ctl_elem_info *uinfo)
3431 {
3432 	static const char *const texts[] = { "Single", "Double", "Quad" };
3433 	ENUMERATED_CTL_INFO(uinfo, texts);
3434 	return 0;
3435 }
3436 
snd_hdspm_get_qs_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3437 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3438 				      struct snd_ctl_elem_value *ucontrol)
3439 {
3440 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3441 
3442 	spin_lock_irq(&hdspm->lock);
3443 	ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3444 	spin_unlock_irq(&hdspm->lock);
3445 	return 0;
3446 }
3447 
snd_hdspm_put_qs_wire(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3448 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3449 				      struct snd_ctl_elem_value *ucontrol)
3450 {
3451 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3452 	int change;
3453 	int val;
3454 
3455 	if (!snd_hdspm_use_is_exclusive(hdspm))
3456 		return -EBUSY;
3457 	val = ucontrol->value.integer.value[0];
3458 	if (val < 0)
3459 		val = 0;
3460 	if (val > 2)
3461 		val = 2;
3462 	spin_lock_irq(&hdspm->lock);
3463 	change = val != hdspm_qs_wire(hdspm);
3464 	hdspm_set_qs_wire(hdspm, val);
3465 	spin_unlock_irq(&hdspm->lock);
3466 	return change;
3467 }
3468 
3469 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3470 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3471 	.name = xname, \
3472 	.private_value = xindex, \
3473 	.info = snd_hdspm_info_tristate, \
3474 	.get = snd_hdspm_get_tristate, \
3475 	.put = snd_hdspm_put_tristate \
3476 }
3477 
hdspm_tristate(struct hdspm * hdspm,u32 regmask)3478 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3479 {
3480 	u32 reg = hdspm->settings_register & (regmask * 3);
3481 	return reg / regmask;
3482 }
3483 
hdspm_set_tristate(struct hdspm * hdspm,int mode,u32 regmask)3484 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3485 {
3486 	hdspm->settings_register &= ~(regmask * 3);
3487 	hdspm->settings_register |= (regmask * mode);
3488 	hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3489 
3490 	return 0;
3491 }
3492 
snd_hdspm_info_tristate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3493 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3494 				       struct snd_ctl_elem_info *uinfo)
3495 {
3496 	u32 regmask = kcontrol->private_value;
3497 
3498 	static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3499 	static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3500 
3501 	switch (regmask) {
3502 	case HDSPM_c0_Input0:
3503 		ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3504 		break;
3505 	default:
3506 		ENUMERATED_CTL_INFO(uinfo, texts_levels);
3507 		break;
3508 	}
3509 	return 0;
3510 }
3511 
snd_hdspm_get_tristate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3512 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3513 				      struct snd_ctl_elem_value *ucontrol)
3514 {
3515 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3516 	u32 regmask = kcontrol->private_value;
3517 
3518 	spin_lock_irq(&hdspm->lock);
3519 	ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3520 	spin_unlock_irq(&hdspm->lock);
3521 	return 0;
3522 }
3523 
snd_hdspm_put_tristate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3524 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3525 				      struct snd_ctl_elem_value *ucontrol)
3526 {
3527 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3528 	u32 regmask = kcontrol->private_value;
3529 	int change;
3530 	int val;
3531 
3532 	if (!snd_hdspm_use_is_exclusive(hdspm))
3533 		return -EBUSY;
3534 	val = ucontrol->value.integer.value[0];
3535 	if (val < 0)
3536 		val = 0;
3537 	if (val > 2)
3538 		val = 2;
3539 
3540 	spin_lock_irq(&hdspm->lock);
3541 	change = val != hdspm_tristate(hdspm, regmask);
3542 	hdspm_set_tristate(hdspm, val, regmask);
3543 	spin_unlock_irq(&hdspm->lock);
3544 	return change;
3545 }
3546 
3547 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3548 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3549 	.name = xname, \
3550 	.index = xindex, \
3551 	.info = snd_hdspm_info_madi_speedmode, \
3552 	.get = snd_hdspm_get_madi_speedmode, \
3553 	.put = snd_hdspm_put_madi_speedmode \
3554 }
3555 
hdspm_madi_speedmode(struct hdspm * hdspm)3556 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3557 {
3558 	if (hdspm->control_register & HDSPM_QuadSpeed)
3559 		return 2;
3560 	if (hdspm->control_register & HDSPM_DoubleSpeed)
3561 		return 1;
3562 	return 0;
3563 }
3564 
hdspm_set_madi_speedmode(struct hdspm * hdspm,int mode)3565 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3566 {
3567 	hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3568 	switch (mode) {
3569 	case 0:
3570 		break;
3571 	case 1:
3572 		hdspm->control_register |= HDSPM_DoubleSpeed;
3573 		break;
3574 	case 2:
3575 		hdspm->control_register |= HDSPM_QuadSpeed;
3576 		break;
3577 	}
3578 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3579 
3580 	return 0;
3581 }
3582 
snd_hdspm_info_madi_speedmode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3583 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3584 				       struct snd_ctl_elem_info *uinfo)
3585 {
3586 	static const char *const texts[] = { "Single", "Double", "Quad" };
3587 	ENUMERATED_CTL_INFO(uinfo, texts);
3588 	return 0;
3589 }
3590 
snd_hdspm_get_madi_speedmode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3591 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3592 				      struct snd_ctl_elem_value *ucontrol)
3593 {
3594 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3595 
3596 	spin_lock_irq(&hdspm->lock);
3597 	ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3598 	spin_unlock_irq(&hdspm->lock);
3599 	return 0;
3600 }
3601 
snd_hdspm_put_madi_speedmode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3602 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3603 				      struct snd_ctl_elem_value *ucontrol)
3604 {
3605 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3606 	int change;
3607 	int val;
3608 
3609 	if (!snd_hdspm_use_is_exclusive(hdspm))
3610 		return -EBUSY;
3611 	val = ucontrol->value.integer.value[0];
3612 	if (val < 0)
3613 		val = 0;
3614 	if (val > 2)
3615 		val = 2;
3616 	spin_lock_irq(&hdspm->lock);
3617 	change = val != hdspm_madi_speedmode(hdspm);
3618 	hdspm_set_madi_speedmode(hdspm, val);
3619 	spin_unlock_irq(&hdspm->lock);
3620 	return change;
3621 }
3622 
3623 #define HDSPM_MIXER(xname, xindex) \
3624 {	.iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3625 	.name = xname, \
3626 	.index = xindex, \
3627 	.device = 0, \
3628 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3629 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3630 	.info = snd_hdspm_info_mixer, \
3631 	.get = snd_hdspm_get_mixer, \
3632 	.put = snd_hdspm_put_mixer \
3633 }
3634 
snd_hdspm_info_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3635 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3636 				struct snd_ctl_elem_info *uinfo)
3637 {
3638 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3639 	uinfo->count = 3;
3640 	uinfo->value.integer.min = 0;
3641 	uinfo->value.integer.max = 65535;
3642 	uinfo->value.integer.step = 1;
3643 	return 0;
3644 }
3645 
snd_hdspm_get_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3646 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3647 			       struct snd_ctl_elem_value *ucontrol)
3648 {
3649 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3650 	int source;
3651 	int destination;
3652 
3653 	source = ucontrol->value.integer.value[0];
3654 	if (source < 0)
3655 		source = 0;
3656 	else if (source >= 2 * HDSPM_MAX_CHANNELS)
3657 		source = 2 * HDSPM_MAX_CHANNELS - 1;
3658 
3659 	destination = ucontrol->value.integer.value[1];
3660 	if (destination < 0)
3661 		destination = 0;
3662 	else if (destination >= HDSPM_MAX_CHANNELS)
3663 		destination = HDSPM_MAX_CHANNELS - 1;
3664 
3665 	spin_lock_irq(&hdspm->lock);
3666 	if (source >= HDSPM_MAX_CHANNELS)
3667 		ucontrol->value.integer.value[2] =
3668 		    hdspm_read_pb_gain(hdspm, destination,
3669 				       source - HDSPM_MAX_CHANNELS);
3670 	else
3671 		ucontrol->value.integer.value[2] =
3672 		    hdspm_read_in_gain(hdspm, destination, source);
3673 
3674 	spin_unlock_irq(&hdspm->lock);
3675 
3676 	return 0;
3677 }
3678 
snd_hdspm_put_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3679 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3680 			       struct snd_ctl_elem_value *ucontrol)
3681 {
3682 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3683 	int change;
3684 	int source;
3685 	int destination;
3686 	int gain;
3687 
3688 	if (!snd_hdspm_use_is_exclusive(hdspm))
3689 		return -EBUSY;
3690 
3691 	source = ucontrol->value.integer.value[0];
3692 	destination = ucontrol->value.integer.value[1];
3693 
3694 	if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3695 		return -1;
3696 	if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3697 		return -1;
3698 
3699 	gain = ucontrol->value.integer.value[2];
3700 
3701 	spin_lock_irq(&hdspm->lock);
3702 
3703 	if (source >= HDSPM_MAX_CHANNELS)
3704 		change = gain != hdspm_read_pb_gain(hdspm, destination,
3705 						    source -
3706 						    HDSPM_MAX_CHANNELS);
3707 	else
3708 		change = gain != hdspm_read_in_gain(hdspm, destination,
3709 						    source);
3710 
3711 	if (change) {
3712 		if (source >= HDSPM_MAX_CHANNELS)
3713 			hdspm_write_pb_gain(hdspm, destination,
3714 					    source - HDSPM_MAX_CHANNELS,
3715 					    gain);
3716 		else
3717 			hdspm_write_in_gain(hdspm, destination, source,
3718 					    gain);
3719 	}
3720 	spin_unlock_irq(&hdspm->lock);
3721 
3722 	return change;
3723 }
3724 
3725 /* The simple mixer control(s) provide gain control for the
3726    basic 1:1 mappings of playback streams to output
3727    streams.
3728 */
3729 
3730 #define HDSPM_PLAYBACK_MIXER \
3731 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3732 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3733 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3734 	.info = snd_hdspm_info_playback_mixer, \
3735 	.get = snd_hdspm_get_playback_mixer, \
3736 	.put = snd_hdspm_put_playback_mixer \
3737 }
3738 
snd_hdspm_info_playback_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3739 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3740 					 struct snd_ctl_elem_info *uinfo)
3741 {
3742 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3743 	uinfo->count = 1;
3744 	uinfo->value.integer.min = 0;
3745 	uinfo->value.integer.max = 64;
3746 	uinfo->value.integer.step = 1;
3747 	return 0;
3748 }
3749 
snd_hdspm_get_playback_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3750 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3751 					struct snd_ctl_elem_value *ucontrol)
3752 {
3753 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3754 	int channel;
3755 
3756 	channel = ucontrol->id.index - 1;
3757 
3758 	if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3759 		return -EINVAL;
3760 
3761 	spin_lock_irq(&hdspm->lock);
3762 	ucontrol->value.integer.value[0] =
3763 	  (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3764 	spin_unlock_irq(&hdspm->lock);
3765 
3766 	return 0;
3767 }
3768 
snd_hdspm_put_playback_mixer(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3769 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3770 					struct snd_ctl_elem_value *ucontrol)
3771 {
3772 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3773 	int change;
3774 	int channel;
3775 	int gain;
3776 
3777 	if (!snd_hdspm_use_is_exclusive(hdspm))
3778 		return -EBUSY;
3779 
3780 	channel = ucontrol->id.index - 1;
3781 
3782 	if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3783 		return -EINVAL;
3784 
3785 	gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3786 
3787 	spin_lock_irq(&hdspm->lock);
3788 	change =
3789 	    gain != hdspm_read_pb_gain(hdspm, channel,
3790 				       channel);
3791 	if (change)
3792 		hdspm_write_pb_gain(hdspm, channel, channel,
3793 				    gain);
3794 	spin_unlock_irq(&hdspm->lock);
3795 	return change;
3796 }
3797 
3798 #define HDSPM_SYNC_CHECK(xname, xindex) \
3799 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3800 	.name = xname, \
3801 	.private_value = xindex, \
3802 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3803 	.info = snd_hdspm_info_sync_check, \
3804 	.get = snd_hdspm_get_sync_check \
3805 }
3806 
3807 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3808 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3809 	.name = xname, \
3810 	.private_value = xindex, \
3811 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3812 	.info = snd_hdspm_tco_info_lock_check, \
3813 	.get = snd_hdspm_get_sync_check \
3814 }
3815 
3816 
3817 
snd_hdspm_info_sync_check(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3818 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3819 				     struct snd_ctl_elem_info *uinfo)
3820 {
3821 	static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3822 	ENUMERATED_CTL_INFO(uinfo, texts);
3823 	return 0;
3824 }
3825 
snd_hdspm_tco_info_lock_check(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)3826 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3827 				     struct snd_ctl_elem_info *uinfo)
3828 {
3829 	static const char *const texts[] = { "No Lock", "Lock" };
3830 	ENUMERATED_CTL_INFO(uinfo, texts);
3831 	return 0;
3832 }
3833 
hdspm_wc_sync_check(struct hdspm * hdspm)3834 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3835 {
3836 	int status, status2;
3837 
3838 	switch (hdspm->io_type) {
3839 	case AES32:
3840 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3841 		if (status & HDSPM_AES32_wcLock) {
3842 			if (status & HDSPM_AES32_wcSync)
3843 				return 2;
3844 			else
3845 				return 1;
3846 		}
3847 		return 0;
3848 		break;
3849 
3850 	case MADI:
3851 		status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3852 		if (status2 & HDSPM_wcLock) {
3853 			if (status2 & HDSPM_wcSync)
3854 				return 2;
3855 			else
3856 				return 1;
3857 		}
3858 		return 0;
3859 		break;
3860 
3861 	case RayDAT:
3862 	case AIO:
3863 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3864 
3865 		if (status & 0x2000000)
3866 			return 2;
3867 		else if (status & 0x1000000)
3868 			return 1;
3869 		return 0;
3870 
3871 		break;
3872 
3873 	case MADIface:
3874 		break;
3875 	}
3876 
3877 
3878 	return 3;
3879 }
3880 
3881 
hdspm_madi_sync_check(struct hdspm * hdspm)3882 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3883 {
3884 	int status = hdspm_read(hdspm, HDSPM_statusRegister);
3885 	if (status & HDSPM_madiLock) {
3886 		if (status & HDSPM_madiSync)
3887 			return 2;
3888 		else
3889 			return 1;
3890 	}
3891 	return 0;
3892 }
3893 
3894 
hdspm_s1_sync_check(struct hdspm * hdspm,int idx)3895 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3896 {
3897 	int status, lock, sync;
3898 
3899 	status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3900 
3901 	lock = (status & (0x1<<idx)) ? 1 : 0;
3902 	sync = (status & (0x100<<idx)) ? 1 : 0;
3903 
3904 	if (lock && sync)
3905 		return 2;
3906 	else if (lock)
3907 		return 1;
3908 	return 0;
3909 }
3910 
3911 
hdspm_sync_in_sync_check(struct hdspm * hdspm)3912 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3913 {
3914 	int status, lock = 0, sync = 0;
3915 
3916 	switch (hdspm->io_type) {
3917 	case RayDAT:
3918 	case AIO:
3919 		status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3920 		lock = (status & 0x400) ? 1 : 0;
3921 		sync = (status & 0x800) ? 1 : 0;
3922 		break;
3923 
3924 	case MADI:
3925 		status = hdspm_read(hdspm, HDSPM_statusRegister);
3926 		lock = (status & HDSPM_syncInLock) ? 1 : 0;
3927 		sync = (status & HDSPM_syncInSync) ? 1 : 0;
3928 		break;
3929 
3930 	case AES32:
3931 		status = hdspm_read(hdspm, HDSPM_statusRegister2);
3932 		lock = (status & 0x100000) ? 1 : 0;
3933 		sync = (status & 0x200000) ? 1 : 0;
3934 		break;
3935 
3936 	case MADIface:
3937 		break;
3938 	}
3939 
3940 	if (lock && sync)
3941 		return 2;
3942 	else if (lock)
3943 		return 1;
3944 
3945 	return 0;
3946 }
3947 
hdspm_aes_sync_check(struct hdspm * hdspm,int idx)3948 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3949 {
3950 	int status2, lock, sync;
3951 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3952 
3953 	lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3954 	sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3955 
3956 	if (sync)
3957 		return 2;
3958 	else if (lock)
3959 		return 1;
3960 	return 0;
3961 }
3962 
hdspm_tco_input_check(struct hdspm * hdspm,u32 mask)3963 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3964 {
3965 	u32 status;
3966 	status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3967 
3968 	return (status & mask) ? 1 : 0;
3969 }
3970 
3971 
hdspm_tco_sync_check(struct hdspm * hdspm)3972 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3973 {
3974 	int status;
3975 
3976 	if (hdspm->tco) {
3977 		switch (hdspm->io_type) {
3978 		case MADI:
3979 			status = hdspm_read(hdspm, HDSPM_statusRegister);
3980 			if (status & HDSPM_tcoLockMadi) {
3981 				if (status & HDSPM_tcoSync)
3982 					return 2;
3983 				else
3984 					return 1;
3985 			}
3986 			return 0;
3987 		case AES32:
3988 			status = hdspm_read(hdspm, HDSPM_statusRegister);
3989 			if (status & HDSPM_tcoLockAes) {
3990 				if (status & HDSPM_tcoSync)
3991 					return 2;
3992 				else
3993 					return 1;
3994 			}
3995 			return 0;
3996 		case RayDAT:
3997 		case AIO:
3998 			status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3999 
4000 			if (status & 0x8000000)
4001 				return 2; /* Sync */
4002 			if (status & 0x4000000)
4003 				return 1; /* Lock */
4004 			return 0; /* No signal */
4005 
4006 		default:
4007 			break;
4008 		}
4009 	}
4010 
4011 	return 3; /* N/A */
4012 }
4013 
4014 
snd_hdspm_get_sync_check(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4015 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4016 				    struct snd_ctl_elem_value *ucontrol)
4017 {
4018 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4019 	int val = -1;
4020 
4021 	switch (hdspm->io_type) {
4022 	case RayDAT:
4023 		switch (kcontrol->private_value) {
4024 		case 0: /* WC */
4025 			val = hdspm_wc_sync_check(hdspm); break;
4026 		case 7: /* TCO */
4027 			val = hdspm_tco_sync_check(hdspm); break;
4028 		case 8: /* SYNC IN */
4029 			val = hdspm_sync_in_sync_check(hdspm); break;
4030 		default:
4031 			val = hdspm_s1_sync_check(hdspm,
4032 					kcontrol->private_value-1);
4033 		}
4034 		break;
4035 
4036 	case AIO:
4037 		switch (kcontrol->private_value) {
4038 		case 0: /* WC */
4039 			val = hdspm_wc_sync_check(hdspm); break;
4040 		case 4: /* TCO */
4041 			val = hdspm_tco_sync_check(hdspm); break;
4042 		case 5: /* SYNC IN */
4043 			val = hdspm_sync_in_sync_check(hdspm); break;
4044 		default:
4045 			val = hdspm_s1_sync_check(hdspm,
4046 					kcontrol->private_value-1);
4047 		}
4048 		break;
4049 
4050 	case MADI:
4051 		switch (kcontrol->private_value) {
4052 		case 0: /* WC */
4053 			val = hdspm_wc_sync_check(hdspm); break;
4054 		case 1: /* MADI */
4055 			val = hdspm_madi_sync_check(hdspm); break;
4056 		case 2: /* TCO */
4057 			val = hdspm_tco_sync_check(hdspm); break;
4058 		case 3: /* SYNC_IN */
4059 			val = hdspm_sync_in_sync_check(hdspm); break;
4060 		}
4061 		break;
4062 
4063 	case MADIface:
4064 		val = hdspm_madi_sync_check(hdspm); /* MADI */
4065 		break;
4066 
4067 	case AES32:
4068 		switch (kcontrol->private_value) {
4069 		case 0: /* WC */
4070 			val = hdspm_wc_sync_check(hdspm); break;
4071 		case 9: /* TCO */
4072 			val = hdspm_tco_sync_check(hdspm); break;
4073 		case 10 /* SYNC IN */:
4074 			val = hdspm_sync_in_sync_check(hdspm); break;
4075 		default: /* AES1 to AES8 */
4076 			 val = hdspm_aes_sync_check(hdspm,
4077 					 kcontrol->private_value-1);
4078 		}
4079 		break;
4080 
4081 	}
4082 
4083 	if (hdspm->tco) {
4084 		switch (kcontrol->private_value) {
4085 		case 11:
4086 			/* Check TCO for lock state of its current input */
4087 			val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4088 			break;
4089 		case 12:
4090 			/* Check TCO for valid time code on LTC input. */
4091 			val = hdspm_tco_input_check(hdspm,
4092 				HDSPM_TCO1_LTC_Input_valid);
4093 			break;
4094 		default:
4095 			break;
4096 		}
4097 	}
4098 
4099 	if (-1 == val)
4100 		val = 3;
4101 
4102 	ucontrol->value.enumerated.item[0] = val;
4103 	return 0;
4104 }
4105 
4106 
4107 
4108 /*
4109  * TCO controls
4110  */
hdspm_tco_write(struct hdspm * hdspm)4111 static void hdspm_tco_write(struct hdspm *hdspm)
4112 {
4113 	unsigned int tc[4] = { 0, 0, 0, 0};
4114 
4115 	switch (hdspm->tco->input) {
4116 	case 0:
4117 		tc[2] |= HDSPM_TCO2_set_input_MSB;
4118 		break;
4119 	case 1:
4120 		tc[2] |= HDSPM_TCO2_set_input_LSB;
4121 		break;
4122 	default:
4123 		break;
4124 	}
4125 
4126 	switch (hdspm->tco->framerate) {
4127 	case 1:
4128 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4129 		break;
4130 	case 2:
4131 		tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4132 		break;
4133 	case 3:
4134 		tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4135 			HDSPM_TCO1_set_drop_frame_flag;
4136 		break;
4137 	case 4:
4138 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4139 			HDSPM_TCO1_LTC_Format_MSB;
4140 		break;
4141 	case 5:
4142 		tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4143 			HDSPM_TCO1_LTC_Format_MSB +
4144 			HDSPM_TCO1_set_drop_frame_flag;
4145 		break;
4146 	default:
4147 		break;
4148 	}
4149 
4150 	switch (hdspm->tco->wordclock) {
4151 	case 1:
4152 		tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4153 		break;
4154 	case 2:
4155 		tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4156 		break;
4157 	default:
4158 		break;
4159 	}
4160 
4161 	switch (hdspm->tco->samplerate) {
4162 	case 1:
4163 		tc[2] |= HDSPM_TCO2_set_freq;
4164 		break;
4165 	case 2:
4166 		tc[2] |= HDSPM_TCO2_set_freq_from_app;
4167 		break;
4168 	default:
4169 		break;
4170 	}
4171 
4172 	switch (hdspm->tco->pull) {
4173 	case 1:
4174 		tc[2] |= HDSPM_TCO2_set_pull_up;
4175 		break;
4176 	case 2:
4177 		tc[2] |= HDSPM_TCO2_set_pull_down;
4178 		break;
4179 	case 3:
4180 		tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4181 		break;
4182 	case 4:
4183 		tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4184 		break;
4185 	default:
4186 		break;
4187 	}
4188 
4189 	if (1 == hdspm->tco->term) {
4190 		tc[2] |= HDSPM_TCO2_set_term_75R;
4191 	}
4192 
4193 	hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4194 	hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4195 	hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4196 	hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4197 }
4198 
4199 
4200 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4201 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4202 	.name = xname, \
4203 	.index = xindex, \
4204 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4205 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4206 	.info = snd_hdspm_info_tco_sample_rate, \
4207 	.get = snd_hdspm_get_tco_sample_rate, \
4208 	.put = snd_hdspm_put_tco_sample_rate \
4209 }
4210 
snd_hdspm_info_tco_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4211 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4212 					  struct snd_ctl_elem_info *uinfo)
4213 {
4214 	/* TODO freq from app could be supported here, see tco->samplerate */
4215 	static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4216 	ENUMERATED_CTL_INFO(uinfo, texts);
4217 	return 0;
4218 }
4219 
snd_hdspm_get_tco_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4220 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4221 				      struct snd_ctl_elem_value *ucontrol)
4222 {
4223 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4224 
4225 	ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4226 
4227 	return 0;
4228 }
4229 
snd_hdspm_put_tco_sample_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4230 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4231 					 struct snd_ctl_elem_value *ucontrol)
4232 {
4233 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4234 
4235 	if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4236 		hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4237 
4238 		hdspm_tco_write(hdspm);
4239 
4240 		return 1;
4241 	}
4242 
4243 	return 0;
4244 }
4245 
4246 
4247 #define HDSPM_TCO_PULL(xname, xindex) \
4248 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4249 	.name = xname, \
4250 	.index = xindex, \
4251 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4252 		SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4253 	.info = snd_hdspm_info_tco_pull, \
4254 	.get = snd_hdspm_get_tco_pull, \
4255 	.put = snd_hdspm_put_tco_pull \
4256 }
4257 
snd_hdspm_info_tco_pull(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4258 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4259 				   struct snd_ctl_elem_info *uinfo)
4260 {
4261 	static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4262 		"+ 4 %", "- 4 %" };
4263 	ENUMERATED_CTL_INFO(uinfo, texts);
4264 	return 0;
4265 }
4266 
snd_hdspm_get_tco_pull(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4267 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4268 				  struct snd_ctl_elem_value *ucontrol)
4269 {
4270 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4271 
4272 	ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4273 
4274 	return 0;
4275 }
4276 
snd_hdspm_put_tco_pull(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4277 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4278 				  struct snd_ctl_elem_value *ucontrol)
4279 {
4280 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4281 
4282 	if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4283 		hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4284 
4285 		hdspm_tco_write(hdspm);
4286 
4287 		return 1;
4288 	}
4289 
4290 	return 0;
4291 }
4292 
4293 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4294 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4295 	.name = xname, \
4296 	.index = xindex, \
4297 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4298 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4299 	.info = snd_hdspm_info_tco_wck_conversion, \
4300 	.get = snd_hdspm_get_tco_wck_conversion, \
4301 	.put = snd_hdspm_put_tco_wck_conversion \
4302 }
4303 
snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4304 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4305 					     struct snd_ctl_elem_info *uinfo)
4306 {
4307 	static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4308 	ENUMERATED_CTL_INFO(uinfo, texts);
4309 	return 0;
4310 }
4311 
snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4312 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4313 					    struct snd_ctl_elem_value *ucontrol)
4314 {
4315 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4316 
4317 	ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4318 
4319 	return 0;
4320 }
4321 
snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4322 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4323 					    struct snd_ctl_elem_value *ucontrol)
4324 {
4325 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4326 
4327 	if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4328 		hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4329 
4330 		hdspm_tco_write(hdspm);
4331 
4332 		return 1;
4333 	}
4334 
4335 	return 0;
4336 }
4337 
4338 
4339 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4340 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4341 	.name = xname, \
4342 	.index = xindex, \
4343 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4344 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4345 	.info = snd_hdspm_info_tco_frame_rate, \
4346 	.get = snd_hdspm_get_tco_frame_rate, \
4347 	.put = snd_hdspm_put_tco_frame_rate \
4348 }
4349 
snd_hdspm_info_tco_frame_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4350 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4351 					  struct snd_ctl_elem_info *uinfo)
4352 {
4353 	static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4354 		"29.97 dfps", "30 fps", "30 dfps" };
4355 	ENUMERATED_CTL_INFO(uinfo, texts);
4356 	return 0;
4357 }
4358 
snd_hdspm_get_tco_frame_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4359 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4360 					struct snd_ctl_elem_value *ucontrol)
4361 {
4362 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4363 
4364 	ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4365 
4366 	return 0;
4367 }
4368 
snd_hdspm_put_tco_frame_rate(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4369 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4370 					struct snd_ctl_elem_value *ucontrol)
4371 {
4372 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4373 
4374 	if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4375 		hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4376 
4377 		hdspm_tco_write(hdspm);
4378 
4379 		return 1;
4380 	}
4381 
4382 	return 0;
4383 }
4384 
4385 
4386 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4387 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4388 	.name = xname, \
4389 	.index = xindex, \
4390 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4391 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4392 	.info = snd_hdspm_info_tco_sync_source, \
4393 	.get = snd_hdspm_get_tco_sync_source, \
4394 	.put = snd_hdspm_put_tco_sync_source \
4395 }
4396 
snd_hdspm_info_tco_sync_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4397 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4398 					  struct snd_ctl_elem_info *uinfo)
4399 {
4400 	static const char *const texts[] = { "LTC", "Video", "WCK" };
4401 	ENUMERATED_CTL_INFO(uinfo, texts);
4402 	return 0;
4403 }
4404 
snd_hdspm_get_tco_sync_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4405 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4406 					 struct snd_ctl_elem_value *ucontrol)
4407 {
4408 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4409 
4410 	ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4411 
4412 	return 0;
4413 }
4414 
snd_hdspm_put_tco_sync_source(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4415 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4416 					 struct snd_ctl_elem_value *ucontrol)
4417 {
4418 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4419 
4420 	if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4421 		hdspm->tco->input = ucontrol->value.enumerated.item[0];
4422 
4423 		hdspm_tco_write(hdspm);
4424 
4425 		return 1;
4426 	}
4427 
4428 	return 0;
4429 }
4430 
4431 
4432 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4433 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4434 	.name = xname, \
4435 	.index = xindex, \
4436 	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4437 			SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4438 	.info = snd_hdspm_info_tco_word_term, \
4439 	.get = snd_hdspm_get_tco_word_term, \
4440 	.put = snd_hdspm_put_tco_word_term \
4441 }
4442 
snd_hdspm_info_tco_word_term(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4443 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4444 					struct snd_ctl_elem_info *uinfo)
4445 {
4446 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4447 	uinfo->count = 1;
4448 	uinfo->value.integer.min = 0;
4449 	uinfo->value.integer.max = 1;
4450 
4451 	return 0;
4452 }
4453 
4454 
snd_hdspm_get_tco_word_term(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4455 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4456 				       struct snd_ctl_elem_value *ucontrol)
4457 {
4458 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4459 
4460 	ucontrol->value.integer.value[0] = hdspm->tco->term;
4461 
4462 	return 0;
4463 }
4464 
4465 
snd_hdspm_put_tco_word_term(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4466 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4467 				       struct snd_ctl_elem_value *ucontrol)
4468 {
4469 	struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4470 
4471 	if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4472 		hdspm->tco->term = ucontrol->value.integer.value[0];
4473 
4474 		hdspm_tco_write(hdspm);
4475 
4476 		return 1;
4477 	}
4478 
4479 	return 0;
4480 }
4481 
4482 
4483 
4484 
4485 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4486 	HDSPM_MIXER("Mixer", 0),
4487 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4488 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4489 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4490 	HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4491 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4492 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4493 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4494 	HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4495 	HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4496 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4497 	HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4498 	HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4499 	HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4500 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4501 	HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4502 	HDSPM_INPUT_SELECT("Input Select", 0),
4503 	HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4504 };
4505 
4506 
4507 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4508 	HDSPM_MIXER("Mixer", 0),
4509 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4510 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4511 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4512 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4513 	HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4514 	HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4515 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4516 	HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4517 	HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4518 };
4519 
4520 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4521 	HDSPM_MIXER("Mixer", 0),
4522 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4523 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4524 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4525 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4526 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4527 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4528 	HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4529 	HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4530 	HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4531 	HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4532 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4533 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4534 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4535 	HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4536 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4537 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4538 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4539 	HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4540 	HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4541 	HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4542 	HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4543 	HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4544 	HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4545 	HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4546 	HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4547 	HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4548 
4549 		/*
4550 		   HDSPM_INPUT_SELECT("Input Select", 0),
4551 		   HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4552 		   HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4553 		   HDSPM_SPDIF_IN("SPDIF In", 0);
4554 		   HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4555 		   HDSPM_INPUT_LEVEL("Input Level", 0);
4556 		   HDSPM_OUTPUT_LEVEL("Output Level", 0);
4557 		   HDSPM_PHONES("Phones", 0);
4558 		   */
4559 };
4560 
4561 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4562 	HDSPM_MIXER("Mixer", 0),
4563 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4564 	HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4565 	HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4566 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4567 	HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4568 	HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4569 	HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4570 	HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4571 	HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4572 	HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4573 	HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4574 	HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4575 	HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4576 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4577 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4578 	HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4579 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4580 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4581 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4582 	HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4583 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4584 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4585 	HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4586 	HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4587 };
4588 
4589 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4590 	HDSPM_MIXER("Mixer", 0),
4591 	HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4592 	HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4593 	HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4594 	HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4595 	HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4596 	HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4597 	HDSPM_SYNC_CHECK("WC Sync Check", 0),
4598 	HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4599 	HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4600 	HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4601 	HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4602 	HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4603 	HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4604 	HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4605 	HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4606 	HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4607 	HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4608 	HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4609 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4610 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4611 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4612 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4613 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4614 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4615 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4616 	HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4617 	HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4618 	HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4619 	HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4620 	HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4621 	HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4622 	HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4623 	HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4624 	HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4625 	HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4626 };
4627 
4628 
4629 
4630 /* Control elements for the optional TCO module */
4631 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4632 	HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4633 	HDSPM_TCO_PULL("TCO Pull", 0),
4634 	HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4635 	HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4636 	HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4637 	HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4638 	HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4639 	HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4640 	HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4641 	HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4642 };
4643 
4644 
4645 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4646 
4647 
hdspm_update_simple_mixer_controls(struct hdspm * hdspm)4648 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4649 {
4650 	int i;
4651 
4652 	for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4653 		if (hdspm->system_sample_rate > 48000) {
4654 			hdspm->playback_mixer_ctls[i]->vd[0].access =
4655 				SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4656 				SNDRV_CTL_ELEM_ACCESS_READ |
4657 				SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4658 		} else {
4659 			hdspm->playback_mixer_ctls[i]->vd[0].access =
4660 				SNDRV_CTL_ELEM_ACCESS_READWRITE |
4661 				SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4662 		}
4663 		snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4664 				SNDRV_CTL_EVENT_MASK_INFO,
4665 				&hdspm->playback_mixer_ctls[i]->id);
4666 	}
4667 
4668 	return 0;
4669 }
4670 
4671 
snd_hdspm_create_controls(struct snd_card * card,struct hdspm * hdspm)4672 static int snd_hdspm_create_controls(struct snd_card *card,
4673 					struct hdspm *hdspm)
4674 {
4675 	unsigned int idx, limit;
4676 	int err;
4677 	struct snd_kcontrol *kctl;
4678 	struct snd_kcontrol_new *list = NULL;
4679 
4680 	switch (hdspm->io_type) {
4681 	case MADI:
4682 		list = snd_hdspm_controls_madi;
4683 		limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4684 		break;
4685 	case MADIface:
4686 		list = snd_hdspm_controls_madiface;
4687 		limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4688 		break;
4689 	case AIO:
4690 		list = snd_hdspm_controls_aio;
4691 		limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4692 		break;
4693 	case RayDAT:
4694 		list = snd_hdspm_controls_raydat;
4695 		limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4696 		break;
4697 	case AES32:
4698 		list = snd_hdspm_controls_aes32;
4699 		limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4700 		break;
4701 	}
4702 
4703 	if (NULL != list) {
4704 		for (idx = 0; idx < limit; idx++) {
4705 			err = snd_ctl_add(card,
4706 					snd_ctl_new1(&list[idx], hdspm));
4707 			if (err < 0)
4708 				return err;
4709 		}
4710 	}
4711 
4712 
4713 	/* create simple 1:1 playback mixer controls */
4714 	snd_hdspm_playback_mixer.name = "Chn";
4715 	if (hdspm->system_sample_rate >= 128000) {
4716 		limit = hdspm->qs_out_channels;
4717 	} else if (hdspm->system_sample_rate >= 64000) {
4718 		limit = hdspm->ds_out_channels;
4719 	} else {
4720 		limit = hdspm->ss_out_channels;
4721 	}
4722 	for (idx = 0; idx < limit; ++idx) {
4723 		snd_hdspm_playback_mixer.index = idx + 1;
4724 		kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4725 		err = snd_ctl_add(card, kctl);
4726 		if (err < 0)
4727 			return err;
4728 		hdspm->playback_mixer_ctls[idx] = kctl;
4729 	}
4730 
4731 
4732 	if (hdspm->tco) {
4733 		/* add tco control elements */
4734 		list = snd_hdspm_controls_tco;
4735 		limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4736 		for (idx = 0; idx < limit; idx++) {
4737 			err = snd_ctl_add(card,
4738 					snd_ctl_new1(&list[idx], hdspm));
4739 			if (err < 0)
4740 				return err;
4741 		}
4742 	}
4743 
4744 	return 0;
4745 }
4746 
4747 /*------------------------------------------------------------
4748    /proc interface
4749  ------------------------------------------------------------*/
4750 
4751 static void
snd_hdspm_proc_read_tco(struct snd_info_entry * entry,struct snd_info_buffer * buffer)4752 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4753 					struct snd_info_buffer *buffer)
4754 {
4755 	struct hdspm *hdspm = entry->private_data;
4756 	unsigned int status, control;
4757 	int a, ltc, frames, seconds, minutes, hours;
4758 	unsigned int period;
4759 	u64 freq_const = 0;
4760 	u32 rate;
4761 
4762 	snd_iprintf(buffer, "--- TCO ---\n");
4763 
4764 	status = hdspm_read(hdspm, HDSPM_statusRegister);
4765 	control = hdspm->control_register;
4766 
4767 
4768 	if (status & HDSPM_tco_detect) {
4769 		snd_iprintf(buffer, "TCO module detected.\n");
4770 		a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4771 		if (a & HDSPM_TCO1_LTC_Input_valid) {
4772 			snd_iprintf(buffer, "  LTC valid, ");
4773 			switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4774 						HDSPM_TCO1_LTC_Format_MSB)) {
4775 			case 0:
4776 				snd_iprintf(buffer, "24 fps, ");
4777 				break;
4778 			case HDSPM_TCO1_LTC_Format_LSB:
4779 				snd_iprintf(buffer, "25 fps, ");
4780 				break;
4781 			case HDSPM_TCO1_LTC_Format_MSB:
4782 				snd_iprintf(buffer, "29.97 fps, ");
4783 				break;
4784 			default:
4785 				snd_iprintf(buffer, "30 fps, ");
4786 				break;
4787 			}
4788 			if (a & HDSPM_TCO1_set_drop_frame_flag) {
4789 				snd_iprintf(buffer, "drop frame\n");
4790 			} else {
4791 				snd_iprintf(buffer, "full frame\n");
4792 			}
4793 		} else {
4794 			snd_iprintf(buffer, "  no LTC\n");
4795 		}
4796 		if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4797 			snd_iprintf(buffer, "  Video: NTSC\n");
4798 		} else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4799 			snd_iprintf(buffer, "  Video: PAL\n");
4800 		} else {
4801 			snd_iprintf(buffer, "  No video\n");
4802 		}
4803 		if (a & HDSPM_TCO1_TCO_lock) {
4804 			snd_iprintf(buffer, "  Sync: lock\n");
4805 		} else {
4806 			snd_iprintf(buffer, "  Sync: no lock\n");
4807 		}
4808 
4809 		switch (hdspm->io_type) {
4810 		case MADI:
4811 		case AES32:
4812 			freq_const = 110069313433624ULL;
4813 			break;
4814 		case RayDAT:
4815 		case AIO:
4816 			freq_const = 104857600000000ULL;
4817 			break;
4818 		case MADIface:
4819 			break; /* no TCO possible */
4820 		}
4821 
4822 		period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4823 		snd_iprintf(buffer, "    period: %u\n", period);
4824 
4825 
4826 		/* rate = freq_const/period; */
4827 		rate = div_u64(freq_const, period);
4828 
4829 		if (control & HDSPM_QuadSpeed) {
4830 			rate *= 4;
4831 		} else if (control & HDSPM_DoubleSpeed) {
4832 			rate *= 2;
4833 		}
4834 
4835 		snd_iprintf(buffer, "  Frequency: %u Hz\n",
4836 				(unsigned int) rate);
4837 
4838 		ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4839 		frames = ltc & 0xF;
4840 		ltc >>= 4;
4841 		frames += (ltc & 0x3) * 10;
4842 		ltc >>= 4;
4843 		seconds = ltc & 0xF;
4844 		ltc >>= 4;
4845 		seconds += (ltc & 0x7) * 10;
4846 		ltc >>= 4;
4847 		minutes = ltc & 0xF;
4848 		ltc >>= 4;
4849 		minutes += (ltc & 0x7) * 10;
4850 		ltc >>= 4;
4851 		hours = ltc & 0xF;
4852 		ltc >>= 4;
4853 		hours += (ltc & 0x3) * 10;
4854 		snd_iprintf(buffer,
4855 			"  LTC In: %02d:%02d:%02d:%02d\n",
4856 			hours, minutes, seconds, frames);
4857 
4858 	} else {
4859 		snd_iprintf(buffer, "No TCO module detected.\n");
4860 	}
4861 }
4862 
4863 static void
snd_hdspm_proc_read_madi(struct snd_info_entry * entry,struct snd_info_buffer * buffer)4864 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4865 			 struct snd_info_buffer *buffer)
4866 {
4867 	struct hdspm *hdspm = entry->private_data;
4868 	unsigned int status, status2;
4869 
4870 	char *pref_sync_ref;
4871 	char *autosync_ref;
4872 	char *system_clock_mode;
4873 	int x, x2;
4874 
4875 	status = hdspm_read(hdspm, HDSPM_statusRegister);
4876 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4877 
4878 	snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4879 			hdspm->card_name, hdspm->card->number + 1,
4880 			hdspm->firmware_rev,
4881 			(status2 & HDSPM_version0) |
4882 			(status2 & HDSPM_version1) | (status2 &
4883 				HDSPM_version2));
4884 
4885 	snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4886 			(hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4887 			hdspm->serial);
4888 
4889 	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4890 			hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4891 
4892 	snd_iprintf(buffer, "--- System ---\n");
4893 
4894 	snd_iprintf(buffer,
4895 		"IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4896 		status & HDSPM_audioIRQPending,
4897 		(status & HDSPM_midi0IRQPending) ? 1 : 0,
4898 		(status & HDSPM_midi1IRQPending) ? 1 : 0,
4899 		hdspm->irq_count);
4900 	snd_iprintf(buffer,
4901 		"HW pointer: id = %d, rawptr = %d (%d->%d) "
4902 		"estimated= %ld (bytes)\n",
4903 		((status & HDSPM_BufferID) ? 1 : 0),
4904 		(status & HDSPM_BufferPositionMask),
4905 		(status & HDSPM_BufferPositionMask) %
4906 		(2 * (int)hdspm->period_bytes),
4907 		((status & HDSPM_BufferPositionMask) - 64) %
4908 		(2 * (int)hdspm->period_bytes),
4909 		(long) hdspm_hw_pointer(hdspm) * 4);
4910 
4911 	snd_iprintf(buffer,
4912 		"MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4913 		hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4914 		hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4915 		hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4916 		hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4917 	snd_iprintf(buffer,
4918 		"MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4919 		hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4920 		hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4921 	snd_iprintf(buffer,
4922 		"Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4923 		"status2=0x%x\n",
4924 		hdspm->control_register, hdspm->control2_register,
4925 		status, status2);
4926 
4927 
4928 	snd_iprintf(buffer, "--- Settings ---\n");
4929 
4930 	x = hdspm_get_latency(hdspm);
4931 
4932 	snd_iprintf(buffer,
4933 		"Size (Latency): %d samples (2 periods of %lu bytes)\n",
4934 		x, (unsigned long) hdspm->period_bytes);
4935 
4936 	snd_iprintf(buffer, "Line out: %s\n",
4937 		(hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4938 
4939 	snd_iprintf(buffer,
4940 		"ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4941 		"Auto Input %s\n",
4942 		(hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4943 		(hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4944 		(hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4945 
4946 
4947 	if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4948 		system_clock_mode = "AutoSync";
4949 	else
4950 		system_clock_mode = "Master";
4951 	snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4952 
4953 	switch (hdspm_pref_sync_ref(hdspm)) {
4954 	case HDSPM_SYNC_FROM_WORD:
4955 		pref_sync_ref = "Word Clock";
4956 		break;
4957 	case HDSPM_SYNC_FROM_MADI:
4958 		pref_sync_ref = "MADI Sync";
4959 		break;
4960 	case HDSPM_SYNC_FROM_TCO:
4961 		pref_sync_ref = "TCO";
4962 		break;
4963 	case HDSPM_SYNC_FROM_SYNC_IN:
4964 		pref_sync_ref = "Sync In";
4965 		break;
4966 	default:
4967 		pref_sync_ref = "XXXX Clock";
4968 		break;
4969 	}
4970 	snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4971 			pref_sync_ref);
4972 
4973 	snd_iprintf(buffer, "System Clock Frequency: %d\n",
4974 			hdspm->system_sample_rate);
4975 
4976 
4977 	snd_iprintf(buffer, "--- Status:\n");
4978 
4979 	x = status & HDSPM_madiSync;
4980 	x2 = status2 & HDSPM_wcSync;
4981 
4982 	snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4983 			(status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4984 			"NoLock",
4985 			(status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4986 			"NoLock");
4987 
4988 	switch (hdspm_autosync_ref(hdspm)) {
4989 	case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4990 		autosync_ref = "Sync In";
4991 		break;
4992 	case HDSPM_AUTOSYNC_FROM_TCO:
4993 		autosync_ref = "TCO";
4994 		break;
4995 	case HDSPM_AUTOSYNC_FROM_WORD:
4996 		autosync_ref = "Word Clock";
4997 		break;
4998 	case HDSPM_AUTOSYNC_FROM_MADI:
4999 		autosync_ref = "MADI Sync";
5000 		break;
5001 	case HDSPM_AUTOSYNC_FROM_NONE:
5002 		autosync_ref = "Input not valid";
5003 		break;
5004 	default:
5005 		autosync_ref = "---";
5006 		break;
5007 	}
5008 	snd_iprintf(buffer,
5009 		"AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5010 		autosync_ref, hdspm_external_sample_rate(hdspm),
5011 		(status & HDSPM_madiFreqMask) >> 22,
5012 		(status2 & HDSPM_wcFreqMask) >> 5);
5013 
5014 	snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5015 		(status & HDSPM_AB_int) ? "Coax" : "Optical",
5016 		(status & HDSPM_RX_64ch) ? "64 channels" :
5017 		"56 channels");
5018 
5019 	/* call readout function for TCO specific status */
5020 	snd_hdspm_proc_read_tco(entry, buffer);
5021 
5022 	snd_iprintf(buffer, "\n");
5023 }
5024 
5025 static void
snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,struct snd_info_buffer * buffer)5026 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5027 			  struct snd_info_buffer *buffer)
5028 {
5029 	struct hdspm *hdspm = entry->private_data;
5030 	unsigned int status;
5031 	unsigned int status2;
5032 	unsigned int timecode;
5033 	unsigned int wcLock, wcSync;
5034 	int pref_syncref;
5035 	char *autosync_ref;
5036 	int x;
5037 
5038 	status = hdspm_read(hdspm, HDSPM_statusRegister);
5039 	status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5040 	timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5041 
5042 	snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5043 		    hdspm->card_name, hdspm->card->number + 1,
5044 		    hdspm->firmware_rev);
5045 
5046 	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5047 		    hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5048 
5049 	snd_iprintf(buffer, "--- System ---\n");
5050 
5051 	snd_iprintf(buffer,
5052 		    "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5053 		    status & HDSPM_audioIRQPending,
5054 		    (status & HDSPM_midi0IRQPending) ? 1 : 0,
5055 		    (status & HDSPM_midi1IRQPending) ? 1 : 0,
5056 		    hdspm->irq_count);
5057 	snd_iprintf(buffer,
5058 		    "HW pointer: id = %d, rawptr = %d (%d->%d) "
5059 		    "estimated= %ld (bytes)\n",
5060 		    ((status & HDSPM_BufferID) ? 1 : 0),
5061 		    (status & HDSPM_BufferPositionMask),
5062 		    (status & HDSPM_BufferPositionMask) %
5063 		    (2 * (int)hdspm->period_bytes),
5064 		    ((status & HDSPM_BufferPositionMask) - 64) %
5065 		    (2 * (int)hdspm->period_bytes),
5066 		    (long) hdspm_hw_pointer(hdspm) * 4);
5067 
5068 	snd_iprintf(buffer,
5069 		    "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5070 		    hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5071 		    hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5072 		    hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5073 		    hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5074 	snd_iprintf(buffer,
5075 		    "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5076 		    hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5077 		    hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5078 	snd_iprintf(buffer,
5079 		    "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5080 		    "status2=0x%x\n",
5081 		    hdspm->control_register, hdspm->control2_register,
5082 		    status, status2);
5083 
5084 	snd_iprintf(buffer, "--- Settings ---\n");
5085 
5086 	x = hdspm_get_latency(hdspm);
5087 
5088 	snd_iprintf(buffer,
5089 		    "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5090 		    x, (unsigned long) hdspm->period_bytes);
5091 
5092 	snd_iprintf(buffer, "Line out: %s\n",
5093 		    (hdspm->
5094 		     control_register & HDSPM_LineOut) ? "on " : "off");
5095 
5096 	snd_iprintf(buffer,
5097 		    "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5098 		    (hdspm->
5099 		     control_register & HDSPM_clr_tms) ? "on" : "off",
5100 		    (hdspm->
5101 		     control_register & HDSPM_Emphasis) ? "on" : "off",
5102 		    (hdspm->
5103 		     control_register & HDSPM_Dolby) ? "on" : "off");
5104 
5105 
5106 	pref_syncref = hdspm_pref_sync_ref(hdspm);
5107 	if (pref_syncref == 0)
5108 		snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5109 	else
5110 		snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5111 				pref_syncref);
5112 
5113 	snd_iprintf(buffer, "System Clock Frequency: %d\n",
5114 		    hdspm->system_sample_rate);
5115 
5116 	snd_iprintf(buffer, "Double speed: %s\n",
5117 			hdspm->control_register & HDSPM_DS_DoubleWire?
5118 			"Double wire" : "Single wire");
5119 	snd_iprintf(buffer, "Quad speed: %s\n",
5120 			hdspm->control_register & HDSPM_QS_DoubleWire?
5121 			"Double wire" :
5122 			hdspm->control_register & HDSPM_QS_QuadWire?
5123 			"Quad wire" : "Single wire");
5124 
5125 	snd_iprintf(buffer, "--- Status:\n");
5126 
5127 	wcLock = status & HDSPM_AES32_wcLock;
5128 	wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5129 
5130 	snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5131 		    (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5132 		    HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5133 
5134 	for (x = 0; x < 8; x++) {
5135 		snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5136 			    x+1,
5137 			    (status2 & (HDSPM_LockAES >> x)) ?
5138 			    "Sync   " : "No Lock",
5139 			    HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5140 	}
5141 
5142 	switch (hdspm_autosync_ref(hdspm)) {
5143 	case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5144 		autosync_ref = "None"; break;
5145 	case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5146 		autosync_ref = "Word Clock"; break;
5147 	case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5148 		autosync_ref = "AES1"; break;
5149 	case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5150 		autosync_ref = "AES2"; break;
5151 	case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5152 		autosync_ref = "AES3"; break;
5153 	case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5154 		autosync_ref = "AES4"; break;
5155 	case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5156 		autosync_ref = "AES5"; break;
5157 	case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5158 		autosync_ref = "AES6"; break;
5159 	case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5160 		autosync_ref = "AES7"; break;
5161 	case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5162 		autosync_ref = "AES8"; break;
5163 	case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5164 		autosync_ref = "TCO"; break;
5165 	case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5166 		autosync_ref = "Sync In"; break;
5167 	default:
5168 		autosync_ref = "---"; break;
5169 	}
5170 	snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5171 
5172 	/* call readout function for TCO specific status */
5173 	snd_hdspm_proc_read_tco(entry, buffer);
5174 
5175 	snd_iprintf(buffer, "\n");
5176 }
5177 
5178 static void
snd_hdspm_proc_read_raydat(struct snd_info_entry * entry,struct snd_info_buffer * buffer)5179 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5180 			 struct snd_info_buffer *buffer)
5181 {
5182 	struct hdspm *hdspm = entry->private_data;
5183 	unsigned int status1, status2, status3, i;
5184 	unsigned int lock, sync;
5185 
5186 	status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5187 	status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5188 	status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5189 
5190 	snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5191 	snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5192 	snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5193 
5194 
5195 	snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5196 
5197 	snd_iprintf(buffer, "Clock mode      : %s\n",
5198 		(hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5199 	snd_iprintf(buffer, "System frequency: %d Hz\n",
5200 		hdspm_get_system_sample_rate(hdspm));
5201 
5202 	snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5203 
5204 	lock = 0x1;
5205 	sync = 0x100;
5206 
5207 	for (i = 0; i < 8; i++) {
5208 		snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5209 				i,
5210 				(status1 & lock) ? 1 : 0,
5211 				(status1 & sync) ? 1 : 0,
5212 				texts_freq[(status2 >> (i * 4)) & 0xF]);
5213 
5214 		lock = lock<<1;
5215 		sync = sync<<1;
5216 	}
5217 
5218 	snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5219 			(status1 & 0x1000000) ? 1 : 0,
5220 			(status1 & 0x2000000) ? 1 : 0,
5221 			texts_freq[(status1 >> 16) & 0xF]);
5222 
5223 	snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5224 			(status1 & 0x4000000) ? 1 : 0,
5225 			(status1 & 0x8000000) ? 1 : 0,
5226 			texts_freq[(status1 >> 20) & 0xF]);
5227 
5228 	snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5229 			(status3 & 0x400) ? 1 : 0,
5230 			(status3 & 0x800) ? 1 : 0,
5231 			texts_freq[(status2 >> 12) & 0xF]);
5232 
5233 }
5234 
5235 #ifdef CONFIG_SND_DEBUG
5236 static void
snd_hdspm_proc_read_debug(struct snd_info_entry * entry,struct snd_info_buffer * buffer)5237 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5238 			  struct snd_info_buffer *buffer)
5239 {
5240 	struct hdspm *hdspm = entry->private_data;
5241 
5242 	int j,i;
5243 
5244 	for (i = 0; i < 256 /* 1024*64 */; i += j) {
5245 		snd_iprintf(buffer, "0x%08X: ", i);
5246 		for (j = 0; j < 16; j += 4)
5247 			snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5248 		snd_iprintf(buffer, "\n");
5249 	}
5250 }
5251 #endif
5252 
5253 
snd_hdspm_proc_ports_in(struct snd_info_entry * entry,struct snd_info_buffer * buffer)5254 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5255 			  struct snd_info_buffer *buffer)
5256 {
5257 	struct hdspm *hdspm = entry->private_data;
5258 	int i;
5259 
5260 	snd_iprintf(buffer, "# generated by hdspm\n");
5261 
5262 	for (i = 0; i < hdspm->max_channels_in; i++) {
5263 		snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5264 	}
5265 }
5266 
snd_hdspm_proc_ports_out(struct snd_info_entry * entry,struct snd_info_buffer * buffer)5267 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5268 			  struct snd_info_buffer *buffer)
5269 {
5270 	struct hdspm *hdspm = entry->private_data;
5271 	int i;
5272 
5273 	snd_iprintf(buffer, "# generated by hdspm\n");
5274 
5275 	for (i = 0; i < hdspm->max_channels_out; i++) {
5276 		snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5277 	}
5278 }
5279 
5280 
snd_hdspm_proc_init(struct hdspm * hdspm)5281 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5282 {
5283 	struct snd_info_entry *entry;
5284 
5285 	if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5286 		switch (hdspm->io_type) {
5287 		case AES32:
5288 			snd_info_set_text_ops(entry, hdspm,
5289 					snd_hdspm_proc_read_aes32);
5290 			break;
5291 		case MADI:
5292 			snd_info_set_text_ops(entry, hdspm,
5293 					snd_hdspm_proc_read_madi);
5294 			break;
5295 		case MADIface:
5296 			/* snd_info_set_text_ops(entry, hdspm,
5297 			 snd_hdspm_proc_read_madiface); */
5298 			break;
5299 		case RayDAT:
5300 			snd_info_set_text_ops(entry, hdspm,
5301 					snd_hdspm_proc_read_raydat);
5302 			break;
5303 		case AIO:
5304 			break;
5305 		}
5306 	}
5307 
5308 	if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5309 		snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5310 	}
5311 
5312 	if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5313 		snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5314 	}
5315 
5316 #ifdef CONFIG_SND_DEBUG
5317 	/* debug file to read all hdspm registers */
5318 	if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5319 		snd_info_set_text_ops(entry, hdspm,
5320 				snd_hdspm_proc_read_debug);
5321 #endif
5322 }
5323 
5324 /*------------------------------------------------------------
5325    hdspm intitialize
5326  ------------------------------------------------------------*/
5327 
snd_hdspm_set_defaults(struct hdspm * hdspm)5328 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5329 {
5330 	/* ASSUMPTION: hdspm->lock is either held, or there is no need to
5331 	   hold it (e.g. during module initialization).
5332 	   */
5333 
5334 	/* set defaults:       */
5335 
5336 	hdspm->settings_register = 0;
5337 
5338 	switch (hdspm->io_type) {
5339 	case MADI:
5340 	case MADIface:
5341 		hdspm->control_register =
5342 			0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5343 		break;
5344 
5345 	case RayDAT:
5346 	case AIO:
5347 		hdspm->settings_register = 0x1 + 0x1000;
5348 		/* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5349 		 * line_out */
5350 		hdspm->control_register =
5351 			0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5352 		break;
5353 
5354 	case AES32:
5355 		hdspm->control_register =
5356 			HDSPM_ClockModeMaster |	/* Master Clock Mode on */
5357 			hdspm_encode_latency(7) | /* latency max=8192samples */
5358 			HDSPM_SyncRef0 |	/* AES1 is syncclock */
5359 			HDSPM_LineOut |	/* Analog output in */
5360 			HDSPM_Professional;  /* Professional mode */
5361 		break;
5362 	}
5363 
5364 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5365 
5366 	if (AES32 == hdspm->io_type) {
5367 		/* No control2 register for AES32 */
5368 #ifdef SNDRV_BIG_ENDIAN
5369 		hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5370 #else
5371 		hdspm->control2_register = 0;
5372 #endif
5373 
5374 		hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5375 	}
5376 	hdspm_compute_period_size(hdspm);
5377 
5378 	/* silence everything */
5379 
5380 	all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5381 
5382 	if (hdspm_is_raydat_or_aio(hdspm))
5383 		hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5384 
5385 	/* set a default rate so that the channel map is set up. */
5386 	hdspm_set_rate(hdspm, 48000, 1);
5387 
5388 	return 0;
5389 }
5390 
5391 
5392 /*------------------------------------------------------------
5393    interrupt
5394  ------------------------------------------------------------*/
5395 
snd_hdspm_interrupt(int irq,void * dev_id)5396 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5397 {
5398 	struct hdspm *hdspm = (struct hdspm *) dev_id;
5399 	unsigned int status;
5400 	int i, audio, midi, schedule = 0;
5401 	/* cycles_t now; */
5402 
5403 	status = hdspm_read(hdspm, HDSPM_statusRegister);
5404 
5405 	audio = status & HDSPM_audioIRQPending;
5406 	midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5407 			HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5408 
5409 	/* now = get_cycles(); */
5410 	/*
5411 	 *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5412 	 *          6       4096   ~256053425     ~514672358
5413 	 *          5       2048   ~128024983     ~257373821
5414 	 *          4       1024    ~64023706     ~128718089
5415 	 *          3        512    ~32005945      ~64385999
5416 	 *          2        256    ~16003039      ~32260176
5417 	 *          1        128     ~7998738      ~16194507
5418 	 *          0         64     ~3998231       ~8191558
5419 	 */
5420 	/*
5421 	  dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5422 	   now-hdspm->last_interrupt, status & 0xFFC0);
5423 	   hdspm->last_interrupt = now;
5424 	*/
5425 
5426 	if (!audio && !midi)
5427 		return IRQ_NONE;
5428 
5429 	hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5430 	hdspm->irq_count++;
5431 
5432 
5433 	if (audio) {
5434 		if (hdspm->capture_substream)
5435 			snd_pcm_period_elapsed(hdspm->capture_substream);
5436 
5437 		if (hdspm->playback_substream)
5438 			snd_pcm_period_elapsed(hdspm->playback_substream);
5439 	}
5440 
5441 	if (midi) {
5442 		i = 0;
5443 		while (i < hdspm->midiPorts) {
5444 			if ((hdspm_read(hdspm,
5445 				hdspm->midi[i].statusIn) & 0xff) &&
5446 					(status & hdspm->midi[i].irq)) {
5447 				/* we disable interrupts for this input until
5448 				 * processing is done
5449 				 */
5450 				hdspm->control_register &= ~hdspm->midi[i].ie;
5451 				hdspm_write(hdspm, HDSPM_controlRegister,
5452 						hdspm->control_register);
5453 				hdspm->midi[i].pending = 1;
5454 				schedule = 1;
5455 			}
5456 
5457 			i++;
5458 		}
5459 
5460 		if (schedule)
5461 			tasklet_hi_schedule(&hdspm->midi_tasklet);
5462 	}
5463 
5464 	return IRQ_HANDLED;
5465 }
5466 
5467 /*------------------------------------------------------------
5468    pcm interface
5469   ------------------------------------------------------------*/
5470 
5471 
snd_hdspm_hw_pointer(struct snd_pcm_substream * substream)5472 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5473 					      *substream)
5474 {
5475 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5476 	return hdspm_hw_pointer(hdspm);
5477 }
5478 
5479 
snd_hdspm_reset(struct snd_pcm_substream * substream)5480 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5481 {
5482 	struct snd_pcm_runtime *runtime = substream->runtime;
5483 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5484 	struct snd_pcm_substream *other;
5485 
5486 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5487 		other = hdspm->capture_substream;
5488 	else
5489 		other = hdspm->playback_substream;
5490 
5491 	if (hdspm->running)
5492 		runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5493 	else
5494 		runtime->status->hw_ptr = 0;
5495 	if (other) {
5496 		struct snd_pcm_substream *s;
5497 		struct snd_pcm_runtime *oruntime = other->runtime;
5498 		snd_pcm_group_for_each_entry(s, substream) {
5499 			if (s == other) {
5500 				oruntime->status->hw_ptr =
5501 					runtime->status->hw_ptr;
5502 				break;
5503 			}
5504 		}
5505 	}
5506 	return 0;
5507 }
5508 
snd_hdspm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)5509 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5510 			       struct snd_pcm_hw_params *params)
5511 {
5512 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5513 	int err;
5514 	int i;
5515 	pid_t this_pid;
5516 	pid_t other_pid;
5517 
5518 	spin_lock_irq(&hdspm->lock);
5519 
5520 	if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5521 		this_pid = hdspm->playback_pid;
5522 		other_pid = hdspm->capture_pid;
5523 	} else {
5524 		this_pid = hdspm->capture_pid;
5525 		other_pid = hdspm->playback_pid;
5526 	}
5527 
5528 	if (other_pid > 0 && this_pid != other_pid) {
5529 
5530 		/* The other stream is open, and not by the same
5531 		   task as this one. Make sure that the parameters
5532 		   that matter are the same.
5533 		   */
5534 
5535 		if (params_rate(params) != hdspm->system_sample_rate) {
5536 			spin_unlock_irq(&hdspm->lock);
5537 			_snd_pcm_hw_param_setempty(params,
5538 					SNDRV_PCM_HW_PARAM_RATE);
5539 			return -EBUSY;
5540 		}
5541 
5542 		if (params_period_size(params) != hdspm->period_bytes / 4) {
5543 			spin_unlock_irq(&hdspm->lock);
5544 			_snd_pcm_hw_param_setempty(params,
5545 					SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5546 			return -EBUSY;
5547 		}
5548 
5549 	}
5550 	/* We're fine. */
5551 	spin_unlock_irq(&hdspm->lock);
5552 
5553 	/* how to make sure that the rate matches an externally-set one ?   */
5554 
5555 	spin_lock_irq(&hdspm->lock);
5556 	err = hdspm_set_rate(hdspm, params_rate(params), 0);
5557 	if (err < 0) {
5558 		dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5559 		spin_unlock_irq(&hdspm->lock);
5560 		_snd_pcm_hw_param_setempty(params,
5561 				SNDRV_PCM_HW_PARAM_RATE);
5562 		return err;
5563 	}
5564 	spin_unlock_irq(&hdspm->lock);
5565 
5566 	err = hdspm_set_interrupt_interval(hdspm,
5567 			params_period_size(params));
5568 	if (err < 0) {
5569 		dev_info(hdspm->card->dev,
5570 			 "err on hdspm_set_interrupt_interval: %d\n", err);
5571 		_snd_pcm_hw_param_setempty(params,
5572 				SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5573 		return err;
5574 	}
5575 
5576 	/* Memory allocation, takashi's method, dont know if we should
5577 	 * spinlock
5578 	 */
5579 	/* malloc all buffer even if not enabled to get sure */
5580 	/* Update for MADI rev 204: we need to allocate for all channels,
5581 	 * otherwise it doesn't work at 96kHz */
5582 
5583 	err =
5584 		snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5585 	if (err < 0) {
5586 		dev_info(hdspm->card->dev,
5587 			 "err on snd_pcm_lib_malloc_pages: %d\n", err);
5588 		return err;
5589 	}
5590 
5591 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5592 
5593 		hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5594 				params_channels(params));
5595 
5596 		for (i = 0; i < params_channels(params); ++i)
5597 			snd_hdspm_enable_out(hdspm, i, 1);
5598 
5599 		hdspm->playback_buffer =
5600 			(unsigned char *) substream->runtime->dma_area;
5601 		dev_dbg(hdspm->card->dev,
5602 			"Allocated sample buffer for playback at %p\n",
5603 				hdspm->playback_buffer);
5604 	} else {
5605 		hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5606 				params_channels(params));
5607 
5608 		for (i = 0; i < params_channels(params); ++i)
5609 			snd_hdspm_enable_in(hdspm, i, 1);
5610 
5611 		hdspm->capture_buffer =
5612 			(unsigned char *) substream->runtime->dma_area;
5613 		dev_dbg(hdspm->card->dev,
5614 			"Allocated sample buffer for capture at %p\n",
5615 				hdspm->capture_buffer);
5616 	}
5617 
5618 	/*
5619 	   dev_dbg(hdspm->card->dev,
5620 	   "Allocated sample buffer for %s at 0x%08X\n",
5621 	   substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5622 	   "playback" : "capture",
5623 	   snd_pcm_sgbuf_get_addr(substream, 0));
5624 	   */
5625 	/*
5626 	   dev_dbg(hdspm->card->dev,
5627 	   "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5628 	   substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5629 	   "playback" : "capture",
5630 	   params_rate(params), params_channels(params),
5631 	   params_buffer_size(params));
5632 	   */
5633 
5634 
5635 	/*  For AES cards, the float format bit is the same as the
5636 	 *  preferred sync reference. Since we don't want to break
5637 	 *  sync settings, we have to skip the remaining part of this
5638 	 *  function.
5639 	 */
5640 	if (hdspm->io_type == AES32) {
5641 		return 0;
5642 	}
5643 
5644 
5645 	/* Switch to native float format if requested */
5646 	if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5647 		if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5648 			dev_info(hdspm->card->dev,
5649 				 "Switching to native 32bit LE float format.\n");
5650 
5651 		hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5652 	} else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5653 		if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5654 			dev_info(hdspm->card->dev,
5655 				 "Switching to native 32bit LE integer format.\n");
5656 
5657 		hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5658 	}
5659 	hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5660 
5661 	return 0;
5662 }
5663 
snd_hdspm_hw_free(struct snd_pcm_substream * substream)5664 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5665 {
5666 	int i;
5667 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5668 
5669 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5670 
5671 		/* params_channels(params) should be enough,
5672 		   but to get sure in case of error */
5673 		for (i = 0; i < hdspm->max_channels_out; ++i)
5674 			snd_hdspm_enable_out(hdspm, i, 0);
5675 
5676 		hdspm->playback_buffer = NULL;
5677 	} else {
5678 		for (i = 0; i < hdspm->max_channels_in; ++i)
5679 			snd_hdspm_enable_in(hdspm, i, 0);
5680 
5681 		hdspm->capture_buffer = NULL;
5682 
5683 	}
5684 
5685 	snd_pcm_lib_free_pages(substream);
5686 
5687 	return 0;
5688 }
5689 
5690 
snd_hdspm_channel_info(struct snd_pcm_substream * substream,struct snd_pcm_channel_info * info)5691 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5692 		struct snd_pcm_channel_info *info)
5693 {
5694 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5695 
5696 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5697 		if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5698 			dev_info(hdspm->card->dev,
5699 				 "snd_hdspm_channel_info: output channel out of range (%d)\n",
5700 				 info->channel);
5701 			return -EINVAL;
5702 		}
5703 
5704 		if (hdspm->channel_map_out[info->channel] < 0) {
5705 			dev_info(hdspm->card->dev,
5706 				 "snd_hdspm_channel_info: output channel %d mapped out\n",
5707 				 info->channel);
5708 			return -EINVAL;
5709 		}
5710 
5711 		info->offset = hdspm->channel_map_out[info->channel] *
5712 			HDSPM_CHANNEL_BUFFER_BYTES;
5713 	} else {
5714 		if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5715 			dev_info(hdspm->card->dev,
5716 				 "snd_hdspm_channel_info: input channel out of range (%d)\n",
5717 				 info->channel);
5718 			return -EINVAL;
5719 		}
5720 
5721 		if (hdspm->channel_map_in[info->channel] < 0) {
5722 			dev_info(hdspm->card->dev,
5723 				 "snd_hdspm_channel_info: input channel %d mapped out\n",
5724 				 info->channel);
5725 			return -EINVAL;
5726 		}
5727 
5728 		info->offset = hdspm->channel_map_in[info->channel] *
5729 			HDSPM_CHANNEL_BUFFER_BYTES;
5730 	}
5731 
5732 	info->first = 0;
5733 	info->step = 32;
5734 	return 0;
5735 }
5736 
5737 
snd_hdspm_ioctl(struct snd_pcm_substream * substream,unsigned int cmd,void * arg)5738 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5739 		unsigned int cmd, void *arg)
5740 {
5741 	switch (cmd) {
5742 	case SNDRV_PCM_IOCTL1_RESET:
5743 		return snd_hdspm_reset(substream);
5744 
5745 	case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5746 		{
5747 			struct snd_pcm_channel_info *info = arg;
5748 			return snd_hdspm_channel_info(substream, info);
5749 		}
5750 	default:
5751 		break;
5752 	}
5753 
5754 	return snd_pcm_lib_ioctl(substream, cmd, arg);
5755 }
5756 
snd_hdspm_trigger(struct snd_pcm_substream * substream,int cmd)5757 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5758 {
5759 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5760 	struct snd_pcm_substream *other;
5761 	int running;
5762 
5763 	spin_lock(&hdspm->lock);
5764 	running = hdspm->running;
5765 	switch (cmd) {
5766 	case SNDRV_PCM_TRIGGER_START:
5767 		running |= 1 << substream->stream;
5768 		break;
5769 	case SNDRV_PCM_TRIGGER_STOP:
5770 		running &= ~(1 << substream->stream);
5771 		break;
5772 	default:
5773 		snd_BUG();
5774 		spin_unlock(&hdspm->lock);
5775 		return -EINVAL;
5776 	}
5777 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5778 		other = hdspm->capture_substream;
5779 	else
5780 		other = hdspm->playback_substream;
5781 
5782 	if (other) {
5783 		struct snd_pcm_substream *s;
5784 		snd_pcm_group_for_each_entry(s, substream) {
5785 			if (s == other) {
5786 				snd_pcm_trigger_done(s, substream);
5787 				if (cmd == SNDRV_PCM_TRIGGER_START)
5788 					running |= 1 << s->stream;
5789 				else
5790 					running &= ~(1 << s->stream);
5791 				goto _ok;
5792 			}
5793 		}
5794 		if (cmd == SNDRV_PCM_TRIGGER_START) {
5795 			if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5796 					&& substream->stream ==
5797 					SNDRV_PCM_STREAM_CAPTURE)
5798 				hdspm_silence_playback(hdspm);
5799 		} else {
5800 			if (running &&
5801 				substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5802 				hdspm_silence_playback(hdspm);
5803 		}
5804 	} else {
5805 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5806 			hdspm_silence_playback(hdspm);
5807 	}
5808 _ok:
5809 	snd_pcm_trigger_done(substream, substream);
5810 	if (!hdspm->running && running)
5811 		hdspm_start_audio(hdspm);
5812 	else if (hdspm->running && !running)
5813 		hdspm_stop_audio(hdspm);
5814 	hdspm->running = running;
5815 	spin_unlock(&hdspm->lock);
5816 
5817 	return 0;
5818 }
5819 
snd_hdspm_prepare(struct snd_pcm_substream * substream)5820 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5821 {
5822 	return 0;
5823 }
5824 
5825 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5826 	.info = (SNDRV_PCM_INFO_MMAP |
5827 		 SNDRV_PCM_INFO_MMAP_VALID |
5828 		 SNDRV_PCM_INFO_NONINTERLEAVED |
5829 		 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5830 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
5831 	.rates = (SNDRV_PCM_RATE_32000 |
5832 		  SNDRV_PCM_RATE_44100 |
5833 		  SNDRV_PCM_RATE_48000 |
5834 		  SNDRV_PCM_RATE_64000 |
5835 		  SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5836 		  SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5837 	.rate_min = 32000,
5838 	.rate_max = 192000,
5839 	.channels_min = 1,
5840 	.channels_max = HDSPM_MAX_CHANNELS,
5841 	.buffer_bytes_max =
5842 	    HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5843 	.period_bytes_min = (32 * 4),
5844 	.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5845 	.periods_min = 2,
5846 	.periods_max = 512,
5847 	.fifo_size = 0
5848 };
5849 
5850 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5851 	.info = (SNDRV_PCM_INFO_MMAP |
5852 		 SNDRV_PCM_INFO_MMAP_VALID |
5853 		 SNDRV_PCM_INFO_NONINTERLEAVED |
5854 		 SNDRV_PCM_INFO_SYNC_START),
5855 	.formats = SNDRV_PCM_FMTBIT_S32_LE,
5856 	.rates = (SNDRV_PCM_RATE_32000 |
5857 		  SNDRV_PCM_RATE_44100 |
5858 		  SNDRV_PCM_RATE_48000 |
5859 		  SNDRV_PCM_RATE_64000 |
5860 		  SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5861 		  SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5862 	.rate_min = 32000,
5863 	.rate_max = 192000,
5864 	.channels_min = 1,
5865 	.channels_max = HDSPM_MAX_CHANNELS,
5866 	.buffer_bytes_max =
5867 	    HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5868 	.period_bytes_min = (32 * 4),
5869 	.period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5870 	.periods_min = 2,
5871 	.periods_max = 512,
5872 	.fifo_size = 0
5873 };
5874 
snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)5875 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5876 					   struct snd_pcm_hw_rule *rule)
5877 {
5878 	struct hdspm *hdspm = rule->private;
5879 	struct snd_interval *c =
5880 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5881 	struct snd_interval *r =
5882 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5883 
5884 	if (r->min > 96000 && r->max <= 192000) {
5885 		struct snd_interval t = {
5886 			.min = hdspm->qs_in_channels,
5887 			.max = hdspm->qs_in_channels,
5888 			.integer = 1,
5889 		};
5890 		return snd_interval_refine(c, &t);
5891 	} else if (r->min > 48000 && r->max <= 96000) {
5892 		struct snd_interval t = {
5893 			.min = hdspm->ds_in_channels,
5894 			.max = hdspm->ds_in_channels,
5895 			.integer = 1,
5896 		};
5897 		return snd_interval_refine(c, &t);
5898 	} else if (r->max < 64000) {
5899 		struct snd_interval t = {
5900 			.min = hdspm->ss_in_channels,
5901 			.max = hdspm->ss_in_channels,
5902 			.integer = 1,
5903 		};
5904 		return snd_interval_refine(c, &t);
5905 	}
5906 
5907 	return 0;
5908 }
5909 
snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)5910 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5911 					   struct snd_pcm_hw_rule * rule)
5912 {
5913 	struct hdspm *hdspm = rule->private;
5914 	struct snd_interval *c =
5915 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5916 	struct snd_interval *r =
5917 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5918 
5919 	if (r->min > 96000 && r->max <= 192000) {
5920 		struct snd_interval t = {
5921 			.min = hdspm->qs_out_channels,
5922 			.max = hdspm->qs_out_channels,
5923 			.integer = 1,
5924 		};
5925 		return snd_interval_refine(c, &t);
5926 	} else if (r->min > 48000 && r->max <= 96000) {
5927 		struct snd_interval t = {
5928 			.min = hdspm->ds_out_channels,
5929 			.max = hdspm->ds_out_channels,
5930 			.integer = 1,
5931 		};
5932 		return snd_interval_refine(c, &t);
5933 	} else if (r->max < 64000) {
5934 		struct snd_interval t = {
5935 			.min = hdspm->ss_out_channels,
5936 			.max = hdspm->ss_out_channels,
5937 			.integer = 1,
5938 		};
5939 		return snd_interval_refine(c, &t);
5940 	} else {
5941 	}
5942 	return 0;
5943 }
5944 
snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)5945 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5946 					   struct snd_pcm_hw_rule * rule)
5947 {
5948 	struct hdspm *hdspm = rule->private;
5949 	struct snd_interval *c =
5950 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5951 	struct snd_interval *r =
5952 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5953 
5954 	if (c->min >= hdspm->ss_in_channels) {
5955 		struct snd_interval t = {
5956 			.min = 32000,
5957 			.max = 48000,
5958 			.integer = 1,
5959 		};
5960 		return snd_interval_refine(r, &t);
5961 	} else if (c->max <= hdspm->qs_in_channels) {
5962 		struct snd_interval t = {
5963 			.min = 128000,
5964 			.max = 192000,
5965 			.integer = 1,
5966 		};
5967 		return snd_interval_refine(r, &t);
5968 	} else if (c->max <= hdspm->ds_in_channels) {
5969 		struct snd_interval t = {
5970 			.min = 64000,
5971 			.max = 96000,
5972 			.integer = 1,
5973 		};
5974 		return snd_interval_refine(r, &t);
5975 	}
5976 
5977 	return 0;
5978 }
snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)5979 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5980 					   struct snd_pcm_hw_rule *rule)
5981 {
5982 	struct hdspm *hdspm = rule->private;
5983 	struct snd_interval *c =
5984 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5985 	struct snd_interval *r =
5986 	    hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5987 
5988 	if (c->min >= hdspm->ss_out_channels) {
5989 		struct snd_interval t = {
5990 			.min = 32000,
5991 			.max = 48000,
5992 			.integer = 1,
5993 		};
5994 		return snd_interval_refine(r, &t);
5995 	} else if (c->max <= hdspm->qs_out_channels) {
5996 		struct snd_interval t = {
5997 			.min = 128000,
5998 			.max = 192000,
5999 			.integer = 1,
6000 		};
6001 		return snd_interval_refine(r, &t);
6002 	} else if (c->max <= hdspm->ds_out_channels) {
6003 		struct snd_interval t = {
6004 			.min = 64000,
6005 			.max = 96000,
6006 			.integer = 1,
6007 		};
6008 		return snd_interval_refine(r, &t);
6009 	}
6010 
6011 	return 0;
6012 }
6013 
snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)6014 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6015 				      struct snd_pcm_hw_rule *rule)
6016 {
6017 	unsigned int list[3];
6018 	struct hdspm *hdspm = rule->private;
6019 	struct snd_interval *c = hw_param_interval(params,
6020 			SNDRV_PCM_HW_PARAM_CHANNELS);
6021 
6022 	list[0] = hdspm->qs_in_channels;
6023 	list[1] = hdspm->ds_in_channels;
6024 	list[2] = hdspm->ss_in_channels;
6025 	return snd_interval_list(c, 3, list, 0);
6026 }
6027 
snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)6028 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6029 				      struct snd_pcm_hw_rule *rule)
6030 {
6031 	unsigned int list[3];
6032 	struct hdspm *hdspm = rule->private;
6033 	struct snd_interval *c = hw_param_interval(params,
6034 			SNDRV_PCM_HW_PARAM_CHANNELS);
6035 
6036 	list[0] = hdspm->qs_out_channels;
6037 	list[1] = hdspm->ds_out_channels;
6038 	list[2] = hdspm->ss_out_channels;
6039 	return snd_interval_list(c, 3, list, 0);
6040 }
6041 
6042 
6043 static unsigned int hdspm_aes32_sample_rates[] = {
6044 	32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6045 };
6046 
6047 static struct snd_pcm_hw_constraint_list
6048 hdspm_hw_constraints_aes32_sample_rates = {
6049 	.count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6050 	.list = hdspm_aes32_sample_rates,
6051 	.mask = 0
6052 };
6053 
snd_hdspm_open(struct snd_pcm_substream * substream)6054 static int snd_hdspm_open(struct snd_pcm_substream *substream)
6055 {
6056 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6057 	struct snd_pcm_runtime *runtime = substream->runtime;
6058 	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6059 
6060 	spin_lock_irq(&hdspm->lock);
6061 	snd_pcm_set_sync(substream);
6062 	runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
6063 		snd_hdspm_capture_subinfo;
6064 
6065 	if (playback) {
6066 		if (hdspm->capture_substream == NULL)
6067 			hdspm_stop_audio(hdspm);
6068 
6069 		hdspm->playback_pid = current->pid;
6070 		hdspm->playback_substream = substream;
6071 	} else {
6072 		if (hdspm->playback_substream == NULL)
6073 			hdspm_stop_audio(hdspm);
6074 
6075 		hdspm->capture_pid = current->pid;
6076 		hdspm->capture_substream = substream;
6077 	}
6078 
6079 	spin_unlock_irq(&hdspm->lock);
6080 
6081 	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6082 	snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6083 
6084 	switch (hdspm->io_type) {
6085 	case AIO:
6086 	case RayDAT:
6087 		snd_pcm_hw_constraint_minmax(runtime,
6088 					     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6089 					     32, 4096);
6090 		/* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6091 		snd_pcm_hw_constraint_single(runtime,
6092 					     SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6093 					     16384);
6094 		break;
6095 
6096 	default:
6097 		snd_pcm_hw_constraint_minmax(runtime,
6098 					     SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6099 					     64, 8192);
6100 		snd_pcm_hw_constraint_single(runtime,
6101 					     SNDRV_PCM_HW_PARAM_PERIODS, 2);
6102 		break;
6103 	}
6104 
6105 	if (AES32 == hdspm->io_type) {
6106 		runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6107 		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6108 				&hdspm_hw_constraints_aes32_sample_rates);
6109 	} else {
6110 		snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6111 				(playback ?
6112 				 snd_hdspm_hw_rule_rate_out_channels :
6113 				 snd_hdspm_hw_rule_rate_in_channels), hdspm,
6114 				SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6115 	}
6116 
6117 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6118 			(playback ? snd_hdspm_hw_rule_out_channels :
6119 			 snd_hdspm_hw_rule_in_channels), hdspm,
6120 			SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6121 
6122 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6123 			(playback ? snd_hdspm_hw_rule_out_channels_rate :
6124 			 snd_hdspm_hw_rule_in_channels_rate), hdspm,
6125 			SNDRV_PCM_HW_PARAM_RATE, -1);
6126 
6127 	return 0;
6128 }
6129 
snd_hdspm_release(struct snd_pcm_substream * substream)6130 static int snd_hdspm_release(struct snd_pcm_substream *substream)
6131 {
6132 	struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6133 	bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6134 
6135 	spin_lock_irq(&hdspm->lock);
6136 
6137 	if (playback) {
6138 		hdspm->playback_pid = -1;
6139 		hdspm->playback_substream = NULL;
6140 	} else {
6141 		hdspm->capture_pid = -1;
6142 		hdspm->capture_substream = NULL;
6143 	}
6144 
6145 	spin_unlock_irq(&hdspm->lock);
6146 
6147 	return 0;
6148 }
6149 
snd_hdspm_hwdep_dummy_op(struct snd_hwdep * hw,struct file * file)6150 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6151 {
6152 	/* we have nothing to initialize but the call is required */
6153 	return 0;
6154 }
6155 
copy_u32_le(void __user * dest,void __iomem * src)6156 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6157 {
6158 	u32 val = readl(src);
6159 	return copy_to_user(dest, &val, 4);
6160 }
6161 
snd_hdspm_hwdep_ioctl(struct snd_hwdep * hw,struct file * file,unsigned int cmd,unsigned long arg)6162 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6163 		unsigned int cmd, unsigned long arg)
6164 {
6165 	void __user *argp = (void __user *)arg;
6166 	struct hdspm *hdspm = hw->private_data;
6167 	struct hdspm_mixer_ioctl mixer;
6168 	struct hdspm_config info;
6169 	struct hdspm_status status;
6170 	struct hdspm_version hdspm_version;
6171 	struct hdspm_peak_rms *levels;
6172 	struct hdspm_ltc ltc;
6173 	unsigned int statusregister;
6174 	long unsigned int s;
6175 	int i = 0;
6176 
6177 	switch (cmd) {
6178 
6179 	case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6180 		levels = &hdspm->peak_rms;
6181 		for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6182 			levels->input_peaks[i] =
6183 				readl(hdspm->iobase +
6184 						HDSPM_MADI_INPUT_PEAK + i*4);
6185 			levels->playback_peaks[i] =
6186 				readl(hdspm->iobase +
6187 						HDSPM_MADI_PLAYBACK_PEAK + i*4);
6188 			levels->output_peaks[i] =
6189 				readl(hdspm->iobase +
6190 						HDSPM_MADI_OUTPUT_PEAK + i*4);
6191 
6192 			levels->input_rms[i] =
6193 				((uint64_t) readl(hdspm->iobase +
6194 					HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6195 				(uint64_t) readl(hdspm->iobase +
6196 						HDSPM_MADI_INPUT_RMS_L + i*4);
6197 			levels->playback_rms[i] =
6198 				((uint64_t)readl(hdspm->iobase +
6199 					HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6200 				(uint64_t)readl(hdspm->iobase +
6201 					HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6202 			levels->output_rms[i] =
6203 				((uint64_t)readl(hdspm->iobase +
6204 					HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6205 				(uint64_t)readl(hdspm->iobase +
6206 						HDSPM_MADI_OUTPUT_RMS_L + i*4);
6207 		}
6208 
6209 		if (hdspm->system_sample_rate > 96000) {
6210 			levels->speed = qs;
6211 		} else if (hdspm->system_sample_rate > 48000) {
6212 			levels->speed = ds;
6213 		} else {
6214 			levels->speed = ss;
6215 		}
6216 		levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6217 
6218 		s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6219 		if (0 != s) {
6220 			/* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6221 			 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6222 			 */
6223 			return -EFAULT;
6224 		}
6225 		break;
6226 
6227 	case SNDRV_HDSPM_IOCTL_GET_LTC:
6228 		ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6229 		i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6230 		if (i & HDSPM_TCO1_LTC_Input_valid) {
6231 			switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6232 				HDSPM_TCO1_LTC_Format_MSB)) {
6233 			case 0:
6234 				ltc.format = fps_24;
6235 				break;
6236 			case HDSPM_TCO1_LTC_Format_LSB:
6237 				ltc.format = fps_25;
6238 				break;
6239 			case HDSPM_TCO1_LTC_Format_MSB:
6240 				ltc.format = fps_2997;
6241 				break;
6242 			default:
6243 				ltc.format = fps_30;
6244 				break;
6245 			}
6246 			if (i & HDSPM_TCO1_set_drop_frame_flag) {
6247 				ltc.frame = drop_frame;
6248 			} else {
6249 				ltc.frame = full_frame;
6250 			}
6251 		} else {
6252 			ltc.format = format_invalid;
6253 			ltc.frame = frame_invalid;
6254 		}
6255 		if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6256 			ltc.input_format = ntsc;
6257 		} else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6258 			ltc.input_format = pal;
6259 		} else {
6260 			ltc.input_format = no_video;
6261 		}
6262 
6263 		s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6264 		if (0 != s) {
6265 			/*
6266 			  dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6267 			return -EFAULT;
6268 		}
6269 
6270 		break;
6271 
6272 	case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6273 
6274 		memset(&info, 0, sizeof(info));
6275 		spin_lock_irq(&hdspm->lock);
6276 		info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6277 		info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6278 
6279 		info.system_sample_rate = hdspm->system_sample_rate;
6280 		info.autosync_sample_rate =
6281 			hdspm_external_sample_rate(hdspm);
6282 		info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6283 		info.clock_source = hdspm_clock_source(hdspm);
6284 		info.autosync_ref = hdspm_autosync_ref(hdspm);
6285 		info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6286 		info.passthru = 0;
6287 		spin_unlock_irq(&hdspm->lock);
6288 		if (copy_to_user(argp, &info, sizeof(info)))
6289 			return -EFAULT;
6290 		break;
6291 
6292 	case SNDRV_HDSPM_IOCTL_GET_STATUS:
6293 		memset(&status, 0, sizeof(status));
6294 
6295 		status.card_type = hdspm->io_type;
6296 
6297 		status.autosync_source = hdspm_autosync_ref(hdspm);
6298 
6299 		status.card_clock = 110069313433624ULL;
6300 		status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6301 
6302 		switch (hdspm->io_type) {
6303 		case MADI:
6304 		case MADIface:
6305 			status.card_specific.madi.sync_wc =
6306 				hdspm_wc_sync_check(hdspm);
6307 			status.card_specific.madi.sync_madi =
6308 				hdspm_madi_sync_check(hdspm);
6309 			status.card_specific.madi.sync_tco =
6310 				hdspm_tco_sync_check(hdspm);
6311 			status.card_specific.madi.sync_in =
6312 				hdspm_sync_in_sync_check(hdspm);
6313 
6314 			statusregister =
6315 				hdspm_read(hdspm, HDSPM_statusRegister);
6316 			status.card_specific.madi.madi_input =
6317 				(statusregister & HDSPM_AB_int) ? 1 : 0;
6318 			status.card_specific.madi.channel_format =
6319 				(statusregister & HDSPM_RX_64ch) ? 1 : 0;
6320 			/* TODO: Mac driver sets it when f_s>48kHz */
6321 			status.card_specific.madi.frame_format = 0;
6322 
6323 		default:
6324 			break;
6325 		}
6326 
6327 		if (copy_to_user(argp, &status, sizeof(status)))
6328 			return -EFAULT;
6329 
6330 
6331 		break;
6332 
6333 	case SNDRV_HDSPM_IOCTL_GET_VERSION:
6334 		memset(&hdspm_version, 0, sizeof(hdspm_version));
6335 
6336 		hdspm_version.card_type = hdspm->io_type;
6337 		strlcpy(hdspm_version.cardname, hdspm->card_name,
6338 				sizeof(hdspm_version.cardname));
6339 		hdspm_version.serial = hdspm->serial;
6340 		hdspm_version.firmware_rev = hdspm->firmware_rev;
6341 		hdspm_version.addons = 0;
6342 		if (hdspm->tco)
6343 			hdspm_version.addons |= HDSPM_ADDON_TCO;
6344 
6345 		if (copy_to_user(argp, &hdspm_version,
6346 					sizeof(hdspm_version)))
6347 			return -EFAULT;
6348 		break;
6349 
6350 	case SNDRV_HDSPM_IOCTL_GET_MIXER:
6351 		if (copy_from_user(&mixer, argp, sizeof(mixer)))
6352 			return -EFAULT;
6353 		if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6354 					sizeof(struct hdspm_mixer)))
6355 			return -EFAULT;
6356 		break;
6357 
6358 	default:
6359 		return -EINVAL;
6360 	}
6361 	return 0;
6362 }
6363 
6364 static const struct snd_pcm_ops snd_hdspm_ops = {
6365 	.open = snd_hdspm_open,
6366 	.close = snd_hdspm_release,
6367 	.ioctl = snd_hdspm_ioctl,
6368 	.hw_params = snd_hdspm_hw_params,
6369 	.hw_free = snd_hdspm_hw_free,
6370 	.prepare = snd_hdspm_prepare,
6371 	.trigger = snd_hdspm_trigger,
6372 	.pointer = snd_hdspm_hw_pointer,
6373 	.page = snd_pcm_sgbuf_ops_page,
6374 };
6375 
snd_hdspm_create_hwdep(struct snd_card * card,struct hdspm * hdspm)6376 static int snd_hdspm_create_hwdep(struct snd_card *card,
6377 				  struct hdspm *hdspm)
6378 {
6379 	struct snd_hwdep *hw;
6380 	int err;
6381 
6382 	err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6383 	if (err < 0)
6384 		return err;
6385 
6386 	hdspm->hwdep = hw;
6387 	hw->private_data = hdspm;
6388 	strcpy(hw->name, "HDSPM hwdep interface");
6389 
6390 	hw->ops.open = snd_hdspm_hwdep_dummy_op;
6391 	hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6392 	hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6393 	hw->ops.release = snd_hdspm_hwdep_dummy_op;
6394 
6395 	return 0;
6396 }
6397 
6398 
6399 /*------------------------------------------------------------
6400    memory interface
6401  ------------------------------------------------------------*/
snd_hdspm_preallocate_memory(struct hdspm * hdspm)6402 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6403 {
6404 	int err;
6405 	struct snd_pcm *pcm;
6406 	size_t wanted;
6407 
6408 	pcm = hdspm->pcm;
6409 
6410 	wanted = HDSPM_DMA_AREA_BYTES;
6411 
6412 	err =
6413 	     snd_pcm_lib_preallocate_pages_for_all(pcm,
6414 						   SNDRV_DMA_TYPE_DEV_SG,
6415 						   snd_dma_pci_data(hdspm->pci),
6416 						   wanted,
6417 						   wanted);
6418 	if (err < 0) {
6419 		dev_dbg(hdspm->card->dev,
6420 			"Could not preallocate %zd Bytes\n", wanted);
6421 
6422 		return err;
6423 	} else
6424 		dev_dbg(hdspm->card->dev,
6425 			" Preallocated %zd Bytes\n", wanted);
6426 
6427 	return 0;
6428 }
6429 
6430 
hdspm_set_sgbuf(struct hdspm * hdspm,struct snd_pcm_substream * substream,unsigned int reg,int channels)6431 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6432 			    struct snd_pcm_substream *substream,
6433 			     unsigned int reg, int channels)
6434 {
6435 	int i;
6436 
6437 	/* continuous memory segment */
6438 	for (i = 0; i < (channels * 16); i++)
6439 		hdspm_write(hdspm, reg + 4 * i,
6440 				snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6441 }
6442 
6443 
6444 /* ------------- ALSA Devices ---------------------------- */
snd_hdspm_create_pcm(struct snd_card * card,struct hdspm * hdspm)6445 static int snd_hdspm_create_pcm(struct snd_card *card,
6446 				struct hdspm *hdspm)
6447 {
6448 	struct snd_pcm *pcm;
6449 	int err;
6450 
6451 	err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6452 	if (err < 0)
6453 		return err;
6454 
6455 	hdspm->pcm = pcm;
6456 	pcm->private_data = hdspm;
6457 	strcpy(pcm->name, hdspm->card_name);
6458 
6459 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6460 			&snd_hdspm_ops);
6461 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6462 			&snd_hdspm_ops);
6463 
6464 	pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6465 
6466 	err = snd_hdspm_preallocate_memory(hdspm);
6467 	if (err < 0)
6468 		return err;
6469 
6470 	return 0;
6471 }
6472 
snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)6473 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6474 {
6475 	int i;
6476 
6477 	for (i = 0; i < hdspm->midiPorts; i++)
6478 		snd_hdspm_flush_midi_input(hdspm, i);
6479 }
6480 
snd_hdspm_create_alsa_devices(struct snd_card * card,struct hdspm * hdspm)6481 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6482 					 struct hdspm *hdspm)
6483 {
6484 	int err, i;
6485 
6486 	dev_dbg(card->dev, "Create card...\n");
6487 	err = snd_hdspm_create_pcm(card, hdspm);
6488 	if (err < 0)
6489 		return err;
6490 
6491 	i = 0;
6492 	while (i < hdspm->midiPorts) {
6493 		err = snd_hdspm_create_midi(card, hdspm, i);
6494 		if (err < 0) {
6495 			return err;
6496 		}
6497 		i++;
6498 	}
6499 
6500 	err = snd_hdspm_create_controls(card, hdspm);
6501 	if (err < 0)
6502 		return err;
6503 
6504 	err = snd_hdspm_create_hwdep(card, hdspm);
6505 	if (err < 0)
6506 		return err;
6507 
6508 	dev_dbg(card->dev, "proc init...\n");
6509 	snd_hdspm_proc_init(hdspm);
6510 
6511 	hdspm->system_sample_rate = -1;
6512 	hdspm->last_external_sample_rate = -1;
6513 	hdspm->last_internal_sample_rate = -1;
6514 	hdspm->playback_pid = -1;
6515 	hdspm->capture_pid = -1;
6516 	hdspm->capture_substream = NULL;
6517 	hdspm->playback_substream = NULL;
6518 
6519 	dev_dbg(card->dev, "Set defaults...\n");
6520 	err = snd_hdspm_set_defaults(hdspm);
6521 	if (err < 0)
6522 		return err;
6523 
6524 	dev_dbg(card->dev, "Update mixer controls...\n");
6525 	hdspm_update_simple_mixer_controls(hdspm);
6526 
6527 	dev_dbg(card->dev, "Initializeing complete ???\n");
6528 
6529 	err = snd_card_register(card);
6530 	if (err < 0) {
6531 		dev_err(card->dev, "error registering card\n");
6532 		return err;
6533 	}
6534 
6535 	dev_dbg(card->dev, "... yes now\n");
6536 
6537 	return 0;
6538 }
6539 
snd_hdspm_create(struct snd_card * card,struct hdspm * hdspm)6540 static int snd_hdspm_create(struct snd_card *card,
6541 			    struct hdspm *hdspm)
6542 {
6543 
6544 	struct pci_dev *pci = hdspm->pci;
6545 	int err;
6546 	unsigned long io_extent;
6547 
6548 	hdspm->irq = -1;
6549 	hdspm->card = card;
6550 
6551 	spin_lock_init(&hdspm->lock);
6552 
6553 	pci_read_config_word(hdspm->pci,
6554 			PCI_CLASS_REVISION, &hdspm->firmware_rev);
6555 
6556 	strcpy(card->mixername, "Xilinx FPGA");
6557 	strcpy(card->driver, "HDSPM");
6558 
6559 	switch (hdspm->firmware_rev) {
6560 	case HDSPM_RAYDAT_REV:
6561 		hdspm->io_type = RayDAT;
6562 		hdspm->card_name = "RME RayDAT";
6563 		hdspm->midiPorts = 2;
6564 		break;
6565 	case HDSPM_AIO_REV:
6566 		hdspm->io_type = AIO;
6567 		hdspm->card_name = "RME AIO";
6568 		hdspm->midiPorts = 1;
6569 		break;
6570 	case HDSPM_MADIFACE_REV:
6571 		hdspm->io_type = MADIface;
6572 		hdspm->card_name = "RME MADIface";
6573 		hdspm->midiPorts = 1;
6574 		break;
6575 	default:
6576 		if ((hdspm->firmware_rev == 0xf0) ||
6577 			((hdspm->firmware_rev >= 0xe6) &&
6578 					(hdspm->firmware_rev <= 0xea))) {
6579 			hdspm->io_type = AES32;
6580 			hdspm->card_name = "RME AES32";
6581 			hdspm->midiPorts = 2;
6582 		} else if ((hdspm->firmware_rev == 0xd2) ||
6583 			((hdspm->firmware_rev >= 0xc8)  &&
6584 				(hdspm->firmware_rev <= 0xcf))) {
6585 			hdspm->io_type = MADI;
6586 			hdspm->card_name = "RME MADI";
6587 			hdspm->midiPorts = 3;
6588 		} else {
6589 			dev_err(card->dev,
6590 				"unknown firmware revision %x\n",
6591 				hdspm->firmware_rev);
6592 			return -ENODEV;
6593 		}
6594 	}
6595 
6596 	err = pci_enable_device(pci);
6597 	if (err < 0)
6598 		return err;
6599 
6600 	pci_set_master(hdspm->pci);
6601 
6602 	err = pci_request_regions(pci, "hdspm");
6603 	if (err < 0)
6604 		return err;
6605 
6606 	hdspm->port = pci_resource_start(pci, 0);
6607 	io_extent = pci_resource_len(pci, 0);
6608 
6609 	dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n",
6610 			hdspm->port, hdspm->port + io_extent - 1);
6611 
6612 	hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6613 	if (!hdspm->iobase) {
6614 		dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
6615 				hdspm->port, hdspm->port + io_extent - 1);
6616 		return -EBUSY;
6617 	}
6618 	dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6619 			(unsigned long)hdspm->iobase, hdspm->port,
6620 			hdspm->port + io_extent - 1);
6621 
6622 	if (request_irq(pci->irq, snd_hdspm_interrupt,
6623 			IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6624 		dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6625 		return -EBUSY;
6626 	}
6627 
6628 	dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6629 
6630 	hdspm->irq = pci->irq;
6631 
6632 	dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6633 			sizeof(struct hdspm_mixer));
6634 	hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6635 	if (!hdspm->mixer) {
6636 		dev_err(card->dev,
6637 			"unable to kmalloc Mixer memory of %d Bytes\n",
6638 				(int)sizeof(struct hdspm_mixer));
6639 		return -ENOMEM;
6640 	}
6641 
6642 	hdspm->port_names_in = NULL;
6643 	hdspm->port_names_out = NULL;
6644 
6645 	switch (hdspm->io_type) {
6646 	case AES32:
6647 		hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6648 		hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6649 		hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6650 
6651 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6652 			channel_map_aes32;
6653 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6654 			channel_map_aes32;
6655 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6656 			channel_map_aes32;
6657 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6658 			texts_ports_aes32;
6659 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6660 			texts_ports_aes32;
6661 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6662 			texts_ports_aes32;
6663 
6664 		hdspm->max_channels_out = hdspm->max_channels_in =
6665 			AES32_CHANNELS;
6666 		hdspm->port_names_in = hdspm->port_names_out =
6667 			texts_ports_aes32;
6668 		hdspm->channel_map_in = hdspm->channel_map_out =
6669 			channel_map_aes32;
6670 
6671 		break;
6672 
6673 	case MADI:
6674 	case MADIface:
6675 		hdspm->ss_in_channels = hdspm->ss_out_channels =
6676 			MADI_SS_CHANNELS;
6677 		hdspm->ds_in_channels = hdspm->ds_out_channels =
6678 			MADI_DS_CHANNELS;
6679 		hdspm->qs_in_channels = hdspm->qs_out_channels =
6680 			MADI_QS_CHANNELS;
6681 
6682 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6683 			channel_map_unity_ss;
6684 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6685 			channel_map_unity_ss;
6686 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6687 			channel_map_unity_ss;
6688 
6689 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6690 			texts_ports_madi;
6691 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6692 			texts_ports_madi;
6693 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6694 			texts_ports_madi;
6695 		break;
6696 
6697 	case AIO:
6698 		hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6699 		hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6700 		hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6701 		hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6702 		hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6703 		hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6704 
6705 		if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6706 			dev_info(card->dev, "AEB input board found\n");
6707 			hdspm->ss_in_channels += 4;
6708 			hdspm->ds_in_channels += 4;
6709 			hdspm->qs_in_channels += 4;
6710 		}
6711 
6712 		if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6713 			dev_info(card->dev, "AEB output board found\n");
6714 			hdspm->ss_out_channels += 4;
6715 			hdspm->ds_out_channels += 4;
6716 			hdspm->qs_out_channels += 4;
6717 		}
6718 
6719 		hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6720 		hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6721 		hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6722 
6723 		hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6724 		hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6725 		hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6726 
6727 		hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6728 		hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6729 		hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6730 		hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6731 		hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6732 		hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6733 
6734 		break;
6735 
6736 	case RayDAT:
6737 		hdspm->ss_in_channels = hdspm->ss_out_channels =
6738 			RAYDAT_SS_CHANNELS;
6739 		hdspm->ds_in_channels = hdspm->ds_out_channels =
6740 			RAYDAT_DS_CHANNELS;
6741 		hdspm->qs_in_channels = hdspm->qs_out_channels =
6742 			RAYDAT_QS_CHANNELS;
6743 
6744 		hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6745 		hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6746 
6747 		hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6748 			channel_map_raydat_ss;
6749 		hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6750 			channel_map_raydat_ds;
6751 		hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6752 			channel_map_raydat_qs;
6753 		hdspm->channel_map_in = hdspm->channel_map_out =
6754 			channel_map_raydat_ss;
6755 
6756 		hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6757 			texts_ports_raydat_ss;
6758 		hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6759 			texts_ports_raydat_ds;
6760 		hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6761 			texts_ports_raydat_qs;
6762 
6763 
6764 		break;
6765 
6766 	}
6767 
6768 	/* TCO detection */
6769 	switch (hdspm->io_type) {
6770 	case AIO:
6771 	case RayDAT:
6772 		if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6773 				HDSPM_s2_tco_detect) {
6774 			hdspm->midiPorts++;
6775 			hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6776 					GFP_KERNEL);
6777 			if (NULL != hdspm->tco) {
6778 				hdspm_tco_write(hdspm);
6779 			}
6780 			dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6781 		} else {
6782 			hdspm->tco = NULL;
6783 		}
6784 		break;
6785 
6786 	case MADI:
6787 	case AES32:
6788 		if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6789 			hdspm->midiPorts++;
6790 			hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6791 					GFP_KERNEL);
6792 			if (NULL != hdspm->tco) {
6793 				hdspm_tco_write(hdspm);
6794 			}
6795 			dev_info(card->dev, "MADI/AES TCO module found\n");
6796 		} else {
6797 			hdspm->tco = NULL;
6798 		}
6799 		break;
6800 
6801 	default:
6802 		hdspm->tco = NULL;
6803 	}
6804 
6805 	/* texts */
6806 	switch (hdspm->io_type) {
6807 	case AES32:
6808 		if (hdspm->tco) {
6809 			hdspm->texts_autosync = texts_autosync_aes_tco;
6810 			hdspm->texts_autosync_items =
6811 				ARRAY_SIZE(texts_autosync_aes_tco);
6812 		} else {
6813 			hdspm->texts_autosync = texts_autosync_aes;
6814 			hdspm->texts_autosync_items =
6815 				ARRAY_SIZE(texts_autosync_aes);
6816 		}
6817 		break;
6818 
6819 	case MADI:
6820 		if (hdspm->tco) {
6821 			hdspm->texts_autosync = texts_autosync_madi_tco;
6822 			hdspm->texts_autosync_items = 4;
6823 		} else {
6824 			hdspm->texts_autosync = texts_autosync_madi;
6825 			hdspm->texts_autosync_items = 3;
6826 		}
6827 		break;
6828 
6829 	case MADIface:
6830 
6831 		break;
6832 
6833 	case RayDAT:
6834 		if (hdspm->tco) {
6835 			hdspm->texts_autosync = texts_autosync_raydat_tco;
6836 			hdspm->texts_autosync_items = 9;
6837 		} else {
6838 			hdspm->texts_autosync = texts_autosync_raydat;
6839 			hdspm->texts_autosync_items = 8;
6840 		}
6841 		break;
6842 
6843 	case AIO:
6844 		if (hdspm->tco) {
6845 			hdspm->texts_autosync = texts_autosync_aio_tco;
6846 			hdspm->texts_autosync_items = 6;
6847 		} else {
6848 			hdspm->texts_autosync = texts_autosync_aio;
6849 			hdspm->texts_autosync_items = 5;
6850 		}
6851 		break;
6852 
6853 	}
6854 
6855 	tasklet_init(&hdspm->midi_tasklet,
6856 			hdspm_midi_tasklet, (unsigned long) hdspm);
6857 
6858 
6859 	if (hdspm->io_type != MADIface) {
6860 		hdspm->serial = (hdspm_read(hdspm,
6861 				HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6862 		/* id contains either a user-provided value or the default
6863 		 * NULL. If it's the default, we're safe to
6864 		 * fill card->id with the serial number.
6865 		 *
6866 		 * If the serial number is 0xFFFFFF, then we're dealing with
6867 		 * an old PCI revision that comes without a sane number. In
6868 		 * this case, we don't set card->id to avoid collisions
6869 		 * when running with multiple cards.
6870 		 */
6871 		if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6872 			sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6873 			snd_card_set_id(card, card->id);
6874 		}
6875 	}
6876 
6877 	dev_dbg(card->dev, "create alsa devices.\n");
6878 	err = snd_hdspm_create_alsa_devices(card, hdspm);
6879 	if (err < 0)
6880 		return err;
6881 
6882 	snd_hdspm_initialize_midi_flush(hdspm);
6883 
6884 	return 0;
6885 }
6886 
6887 
snd_hdspm_free(struct hdspm * hdspm)6888 static int snd_hdspm_free(struct hdspm * hdspm)
6889 {
6890 
6891 	if (hdspm->port) {
6892 
6893 		/* stop th audio, and cancel all interrupts */
6894 		hdspm->control_register &=
6895 		    ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6896 		      HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6897 		      HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6898 		hdspm_write(hdspm, HDSPM_controlRegister,
6899 			    hdspm->control_register);
6900 	}
6901 
6902 	if (hdspm->irq >= 0)
6903 		free_irq(hdspm->irq, (void *) hdspm);
6904 
6905 	kfree(hdspm->mixer);
6906 	iounmap(hdspm->iobase);
6907 
6908 	if (hdspm->port)
6909 		pci_release_regions(hdspm->pci);
6910 
6911 	pci_disable_device(hdspm->pci);
6912 	return 0;
6913 }
6914 
6915 
snd_hdspm_card_free(struct snd_card * card)6916 static void snd_hdspm_card_free(struct snd_card *card)
6917 {
6918 	struct hdspm *hdspm = card->private_data;
6919 
6920 	if (hdspm)
6921 		snd_hdspm_free(hdspm);
6922 }
6923 
6924 
snd_hdspm_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)6925 static int snd_hdspm_probe(struct pci_dev *pci,
6926 			   const struct pci_device_id *pci_id)
6927 {
6928 	static int dev;
6929 	struct hdspm *hdspm;
6930 	struct snd_card *card;
6931 	int err;
6932 
6933 	if (dev >= SNDRV_CARDS)
6934 		return -ENODEV;
6935 	if (!enable[dev]) {
6936 		dev++;
6937 		return -ENOENT;
6938 	}
6939 
6940 	err = snd_card_new(&pci->dev, index[dev], id[dev],
6941 			   THIS_MODULE, sizeof(struct hdspm), &card);
6942 	if (err < 0)
6943 		return err;
6944 
6945 	hdspm = card->private_data;
6946 	card->private_free = snd_hdspm_card_free;
6947 	hdspm->dev = dev;
6948 	hdspm->pci = pci;
6949 
6950 	err = snd_hdspm_create(card, hdspm);
6951 	if (err < 0) {
6952 		snd_card_free(card);
6953 		return err;
6954 	}
6955 
6956 	if (hdspm->io_type != MADIface) {
6957 		sprintf(card->shortname, "%s_%x",
6958 			hdspm->card_name,
6959 			hdspm->serial);
6960 		sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6961 			hdspm->card_name,
6962 			hdspm->serial,
6963 			hdspm->port, hdspm->irq);
6964 	} else {
6965 		sprintf(card->shortname, "%s", hdspm->card_name);
6966 		sprintf(card->longname, "%s at 0x%lx, irq %d",
6967 				hdspm->card_name, hdspm->port, hdspm->irq);
6968 	}
6969 
6970 	err = snd_card_register(card);
6971 	if (err < 0) {
6972 		snd_card_free(card);
6973 		return err;
6974 	}
6975 
6976 	pci_set_drvdata(pci, card);
6977 
6978 	dev++;
6979 	return 0;
6980 }
6981 
snd_hdspm_remove(struct pci_dev * pci)6982 static void snd_hdspm_remove(struct pci_dev *pci)
6983 {
6984 	snd_card_free(pci_get_drvdata(pci));
6985 }
6986 
6987 static struct pci_driver hdspm_driver = {
6988 	.name = KBUILD_MODNAME,
6989 	.id_table = snd_hdspm_ids,
6990 	.probe = snd_hdspm_probe,
6991 	.remove = snd_hdspm_remove,
6992 };
6993 
6994 module_pci_driver(hdspm_driver);
6995