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Searched refs:clock (Results 1 – 25 of 61) sorted by relevance

123

/sound/pci/lola/
Dlola_clock.c102 chip->clock.cur_freq)) in lola_set_granularity()
140 chip->clock.nid = nid; in lola_init_clock_widget()
141 chip->clock.items = val & 0xff; in lola_init_clock_widget()
143 chip->clock.items); in lola_init_clock_widget()
144 if (chip->clock.items > MAX_SAMPLE_CLOCK_COUNT) { in lola_init_clock_widget()
146 chip->clock.items); in lola_init_clock_widget()
150 nitems = chip->clock.items; in lola_init_clock_widget()
180 chip->clock.cur_index = idx_list; in lola_init_clock_widget()
181 chip->clock.cur_freq = 48000; in lola_init_clock_widget()
182 chip->clock.cur_valid = true; in lola_init_clock_widget()
[all …]
/sound/pci/echoaudio/
Ddarla24_dsp.c99 u8 clock; in set_sample_rate() local
103 clock = GD24_96000; in set_sample_rate()
106 clock = GD24_88200; in set_sample_rate()
109 clock = GD24_48000; in set_sample_rate()
112 clock = GD24_44100; in set_sample_rate()
115 clock = GD24_32000; in set_sample_rate()
118 clock = GD24_22050; in set_sample_rate()
121 clock = GD24_16000; in set_sample_rate()
124 clock = GD24_11025; in set_sample_rate()
127 clock = GD24_8000; in set_sample_rate()
[all …]
Dgina24_dsp.c33 static int set_input_clock(struct echoaudio *chip, u16 clock);
164 u32 control_reg, clock; in set_sample_rate() local
180 clock = 0; in set_sample_rate()
187 clock = GML_96KHZ; in set_sample_rate()
190 clock = GML_88KHZ; in set_sample_rate()
193 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
196 clock = GML_44KHZ; in set_sample_rate()
199 clock |= GML_SPDIF_SAMPLE_RATE0; in set_sample_rate()
202 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | in set_sample_rate()
206 clock = GML_22KHZ; in set_sample_rate()
[all …]
Dlayla24_dsp.c32 static int set_input_clock(struct echoaudio *chip, u16 clock);
159 u32 control_reg, clock, base_rate; in set_sample_rate() local
179 clock = 0; in set_sample_rate()
183 clock = GML_96KHZ; in set_sample_rate()
186 clock = GML_88KHZ; in set_sample_rate()
189 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
192 clock = GML_44KHZ; in set_sample_rate()
195 clock |= GML_SPDIF_SAMPLE_RATE0; in set_sample_rate()
198 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | in set_sample_rate()
202 clock = GML_22KHZ; in set_sample_rate()
[all …]
Dmona_dsp.c33 static int set_input_clock(struct echoaudio *chip, u16 clock);
198 u32 control_reg, clock; in set_sample_rate() local
243 clock = 0; in set_sample_rate()
250 clock = GML_96KHZ; in set_sample_rate()
253 clock = GML_88KHZ; in set_sample_rate()
256 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
259 clock = GML_44KHZ; in set_sample_rate()
262 clock |= GML_SPDIF_SAMPLE_RATE0; in set_sample_rate()
265 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | in set_sample_rate()
269 clock = GML_22KHZ; in set_sample_rate()
[all …]
Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
41 clock = INDIGO_EXPRESS_32000; in set_sample_rate()
44 clock = INDIGO_EXPRESS_44100; in set_sample_rate()
47 clock = INDIGO_EXPRESS_48000; in set_sample_rate()
50 clock = INDIGO_EXPRESS_32000|INDIGO_EXPRESS_DOUBLE_SPEED; in set_sample_rate()
53 clock = INDIGO_EXPRESS_44100|INDIGO_EXPRESS_DOUBLE_SPEED; in set_sample_rate()
56 clock = INDIGO_EXPRESS_48000|INDIGO_EXPRESS_DOUBLE_SPEED; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
65 "set_sample_rate: %d clock %d\n", rate, clock); in set_sample_rate()
Dlayla20_dsp.c188 u16 clock; in set_input_clock() local
195 clock = LAYLA20_CLOCK_INTERNAL; in set_input_clock()
198 clock = LAYLA20_CLOCK_SPDIF; in set_input_clock()
201 clock = LAYLA20_CLOCK_WORD; in set_input_clock()
204 clock = LAYLA20_CLOCK_SUPER; in set_input_clock()
214 chip->comm_page->input_clock = cpu_to_le16(clock); in set_input_clock()
226 static int set_output_clock(struct echoaudio *chip, u16 clock) in set_output_clock() argument
228 switch (clock) { in set_output_clock()
230 clock = LAYLA20_OUTPUT_CLOCK_SUPER; in set_output_clock()
233 clock = LAYLA20_OUTPUT_CLOCK_WORD; in set_output_clock()
[all …]
Dechoaudio_3g.c258 u32 control_reg, clock, base_rate, frq_reg; in set_sample_rate() local
275 clock = 0; in set_sample_rate()
281 clock = E3G_96KHZ; in set_sample_rate()
284 clock = E3G_88KHZ; in set_sample_rate()
287 clock = E3G_48KHZ; in set_sample_rate()
290 clock = E3G_44KHZ; in set_sample_rate()
293 clock = E3G_32KHZ; in set_sample_rate()
296 clock = E3G_CONTINUOUS_CLOCK; in set_sample_rate()
298 clock |= E3G_DOUBLE_SPEED_MODE; in set_sample_rate()
302 control_reg |= clock; in set_sample_rate()
[all …]
Dmia_dsp.c32 static int set_input_clock(struct echoaudio *chip, u16 clock);
154 static int set_input_clock(struct echoaudio *chip, u16 clock) in set_input_clock() argument
156 dev_dbg(chip->card->dev, "set_input_clock(%d)\n", clock); in set_input_clock()
157 if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL && in set_input_clock()
158 clock != ECHO_CLOCK_SPDIF)) in set_input_clock()
161 chip->input_clock = clock; in set_input_clock()
Dgina20_dsp.c149 static int set_input_clock(struct echoaudio *chip, u16 clock) in set_input_clock() argument
152 switch (clock) { in set_input_clock()
158 chip->input_clock = clock; in set_input_clock()
166 chip->input_clock = clock; in set_input_clock()
/sound/firewire/fireworks/
Dfireworks_command.c275 command_get_clock(struct snd_efw *efw, struct efc_clock *clock) in command_get_clock() argument
282 (__be32 *)clock, sizeof(struct efc_clock)); in command_get_clock()
284 be32_to_cpus(&clock->source); in command_get_clock()
285 be32_to_cpus(&clock->sampling_rate); in command_get_clock()
286 be32_to_cpus(&clock->index); in command_get_clock()
297 struct efc_clock clock = {0}; in command_set_clock() local
307 err = command_get_clock(efw, &clock); in command_set_clock()
312 if ((clock.source == source) && (clock.sampling_rate == rate)) in command_set_clock()
316 if ((source != UINT_MAX) && (clock.source != source)) in command_set_clock()
317 clock.source = source; in command_set_clock()
[all …]
/sound/soc/sh/
Dfsi.c259 struct fsi_clk clock; member
740 struct fsi_clk *clock = &fsi->clock; in fsi_clk_init() local
743 clock->xck = NULL; in fsi_clk_init()
744 clock->ick = NULL; in fsi_clk_init()
745 clock->div = NULL; in fsi_clk_init()
746 clock->rate = 0; in fsi_clk_init()
747 clock->count = 0; in fsi_clk_init()
748 clock->set_rate = set_rate; in fsi_clk_init()
750 clock->own = devm_clk_get(dev, NULL); in fsi_clk_init()
751 if (IS_ERR(clock->own)) in fsi_clk_init()
[all …]
/sound/usb/
Dclock.c339 int altsetting, int clock) in get_sample_rate_v2() argument
348 snd_usb_ctrl_intf(chip) | (clock << 8), in get_sample_rate_v2()
366 int clock; in set_sample_rate_v2() local
370 clock = snd_usb_clock_find_source(chip, fmt->clock, true); in set_sample_rate_v2()
371 if (clock < 0) in set_sample_rate_v2()
372 return clock; in set_sample_rate_v2()
374 prev_rate = get_sample_rate_v2(chip, iface, fmt->altsetting, clock); in set_sample_rate_v2()
378 cs_desc = snd_usb_find_clock_source(chip->ctrl_intf, clock); in set_sample_rate_v2()
385 snd_usb_ctrl_intf(chip) | (clock << 8), in set_sample_rate_v2()
394 cur_rate = get_sample_rate_v2(chip, iface, fmt->altsetting, clock); in set_sample_rate_v2()
Dformat.c292 int clock = snd_usb_clock_find_source(chip, fp->clock, false); in parse_audio_format_rates_v2() local
294 if (clock < 0) { in parse_audio_format_rates_v2()
297 __func__, clock); in parse_audio_format_rates_v2()
305 snd_usb_ctrl_intf(chip) | (clock << 8), in parse_audio_format_rates_v2()
311 __func__, clock); in parse_audio_format_rates_v2()
327 snd_usb_ctrl_intf(chip) | (clock << 8), in parse_audio_format_rates_v2()
333 __func__, clock); in parse_audio_format_rates_v2()
Dstream.c489 int num, protocol, clock = 0; in snd_usb_parse_audio_interface() local
609 clock = input_term->bCSourceID; in snd_usb_parse_audio_interface()
618 clock = output_term->bCSourceID; in snd_usb_parse_audio_interface()
679 fp->clock = clock; in snd_usb_parse_audio_interface()
/sound/drivers/vx/
Dvx_uer.c208 int clock; in vx_set_internal_clock() local
211 clock = vx_calc_clock_from_freq(chip, freq); in vx_set_internal_clock()
212 snd_printdd(KERN_DEBUG "set internal clock to 0x%x from freq %d\n", clock, freq); in vx_set_internal_clock()
215 vx_outb(chip, HIFREQ, (clock >> 8) & 0x0f); in vx_set_internal_clock()
216 vx_outb(chip, LOFREQ, clock & 0xff); in vx_set_internal_clock()
218 vx_outl(chip, HIFREQ, (clock >> 8) & 0x0f); in vx_set_internal_clock()
219 vx_outl(chip, LOFREQ, clock & 0xff); in vx_set_internal_clock()
/sound/firewire/digi00x/
Ddigi00x-proc.c42 enum snd_dg00x_clock clock; in proc_read_clock() local
49 if (snd_dg00x_stream_get_clock(dg00x, &clock) < 0) in proc_read_clock()
54 snd_iprintf(buf, "Clock Source: %s\n", source_name[clock]); in proc_read_clock()
56 if (clock == SND_DG00X_CLOCK_INTERNAL) in proc_read_clock()
Ddigi00x-pcm.c116 enum snd_dg00x_clock clock; in pcm_open() local
130 err = snd_dg00x_stream_get_clock(dg00x, &clock); in pcm_open()
133 if (clock != SND_DG00X_CLOCK_INTERNAL) { in pcm_open()
143 if ((clock != SND_DG00X_CLOCK_INTERNAL) || in pcm_open()
/sound/soc/codecs/
Dmax98925.c260 int rate, int clock, int *value, int *n, int *m) in max98925_rate_value() argument
268 *n = rate_table[i].divisors[clock][0]; in max98925_rate_value()
269 *m = rate_table[i].divisors[clock][1]; in max98925_rate_value()
354 unsigned int dai_sr = 0, clock, mdll, n, m; in max98925_set_clock() local
382 clock = 0; in max98925_set_clock()
386 clock = 1; in max98925_set_clock()
390 clock = 0; in max98925_set_clock()
394 clock = 2; in max98925_set_clock()
403 if (max98925_rate_value(codec, rate, clock, &dai_sr, &n, &m)) in max98925_set_clock()
Dwm8753.c1194 u16 clock; in wm8753_mode1v_set_dai_fmt() local
1197 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; in wm8753_mode1v_set_dai_fmt()
1198 snd_soc_write(codec, WM8753_CLOCK, clock); in wm8753_mode1v_set_dai_fmt()
1212 u16 clock; in wm8753_mode2_set_dai_fmt() local
1215 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; in wm8753_mode2_set_dai_fmt()
1216 snd_soc_write(codec, WM8753_CLOCK, clock); in wm8753_mode2_set_dai_fmt()
1224 u16 clock; in wm8753_mode3_4_set_dai_fmt() local
1227 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; in wm8753_mode3_4_set_dai_fmt()
1228 snd_soc_write(codec, WM8753_CLOCK, clock | 0x4); in wm8753_mode3_4_set_dai_fmt()
/sound/firewire/tascam/
Dtascam-stream.c29 enum snd_tscm_clock clock) in set_clock() argument
58 if (clock != INT_MAX) { in set_clock()
60 data |= clock + 1; in set_clock()
112 int snd_tscm_stream_get_clock(struct snd_tscm *tscm, enum snd_tscm_clock *clock) in snd_tscm_stream_get_clock() argument
121 *clock = ((data & 0x00ff0000) >> 16) - 1; in snd_tscm_stream_get_clock()
122 if (*clock < 0 || *clock > SND_TSCM_CLOCK_ADAT) in snd_tscm_stream_get_clock()
Dtascam-pcm.c71 enum snd_tscm_clock clock; in pcm_open() local
83 err = snd_tscm_stream_get_clock(tscm, &clock); in pcm_open()
84 if (clock != SND_TSCM_CLOCK_INTERNAL || in pcm_open()
/sound/firewire/bebob/
Dbebob_focusrite.c187 if (bebob->spec->clock->types == saffirepro_10_clk_src_types) in saffirepro_both_clk_src_get()
274 .clock = &saffirepro_26_clk_spec,
285 .clock = &saffirepro_10_clk_spec,
306 .clock = &saffire_both_clk_spec,
317 .clock = &saffire_both_clk_spec,
Dbebob_maudio.c730 .clock = &special_clk_spec,
746 .clock = NULL,
758 .clock = NULL,
770 .clock = NULL,
782 .clock = NULL,
794 .clock = NULL,
/sound/i2c/
Di2c.c183 static void snd_i2c_bit_direction(struct snd_i2c_bus *bus, int clock, int data) in snd_i2c_bit_direction() argument
186 bus->hw_ops.bit->direction(bus, clock, data); in snd_i2c_bit_direction()
189 static void snd_i2c_bit_set(struct snd_i2c_bus *bus, int clock, int data) in snd_i2c_bit_set() argument
191 bus->hw_ops.bit->setlines(bus, clock, data); in snd_i2c_bit_set()

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