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Searched refs:scr (Results 1 – 5 of 5) sorted by relevance

/sound/soc/mxs/
Dmxs-saif.c93 u32 scr; in mxs_saif_set_clk() local
114 scr = __raw_readl(master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
115 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; in mxs_saif_set_clk()
116 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
132 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
135 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
144 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; in mxs_saif_set_clk()
155 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); in mxs_saif_set_clk()
170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); in mxs_saif_set_clk()
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/sound/soc/fsl/
Dimx-ssi.c90 u32 strcr = 0, scr; in imx_ssi_set_dai_fmt() local
92 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); in imx_ssi_set_dai_fmt()
100 scr |= SSI_SCR_NET; in imx_ssi_set_dai_fmt()
102 scr &= ~SSI_I2S_MODE_MASK; in imx_ssi_set_dai_fmt()
103 scr |= SSI_SCR_I2S_MODE_SLAVE; in imx_ssi_set_dai_fmt()
148 scr |= SSI_SCR_NET; in imx_ssi_set_dai_fmt()
150 scr |= SSI_SCR_SYN; in imx_ssi_set_dai_fmt()
154 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_fmt()
167 u32 scr; in imx_ssi_set_dai_sysclk() local
169 scr = readl(ssi->base + SSI_SCR); in imx_ssi_set_dai_sysclk()
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Dfsl_ssi.c107 u32 scr; member
485 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, in fsl_ssi_config() local
487 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); in fsl_ssi_config()
508 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE); in fsl_ssi_config()
543 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { in fsl_ssi_config()
574 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); in fsl_ssi_config()
600 reg->rx.scr = 0; in fsl_ssi_setup_reg_vals()
603 reg->tx.scr = 0; in fsl_ssi_setup_reg_vals()
606 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; in fsl_ssi_setup_reg_vals()
608 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; in fsl_ssi_setup_reg_vals()
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Dfsl_spdif.c467 u32 scr, mask; in fsl_spdif_startup() local
498 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | in fsl_spdif_startup()
510 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; in fsl_spdif_startup()
517 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); in fsl_spdif_startup()
542 u32 scr, mask, i; in fsl_spdif_shutdown() local
545 scr = 0; in fsl_spdif_shutdown()
552 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; in fsl_spdif_shutdown()
557 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); in fsl_spdif_shutdown()
/sound/pci/ice1712/
Dquartet.c40 unsigned int scr; /* system control register */ member
452 return spec->scr; in get_scr()
471 spec->scr = val; in set_scr()
679 PRIV_ENUM2(AIN34_SEL, SCR_AIN34_SEL, scr, "Line In 3/4", "Hi-Z"),