1 /*
2 * lirc_serial.c
3 *
4 * lirc_serial - Device driver that records pulse- and pause-lengths
5 * (space-lengths) between DDCD event on a serial port.
6 *
7 * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de>
8 * Copyright (C) 1998 Trent Piepho <xyzzy@u.washington.edu>
9 * Copyright (C) 1998 Ben Pfaff <blp@gnu.org>
10 * Copyright (C) 1999 Christoph Bartelmus <lirc@bartelmus.de>
11 * Copyright (C) 2007 Andrei Tanas <andrei@tanas.ca> (suspend/resume support)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * Steve's changes to improve transmission fidelity:
30 * - for systems with the rdtsc instruction and the clock counter, a
31 * send_pule that times the pulses directly using the counter.
32 * This means that the LIRC_SERIAL_TRANSMITTER_LATENCY fudge is
33 * not needed. Measurement shows very stable waveform, even where
34 * PCI activity slows the access to the UART, which trips up other
35 * versions.
36 * - For other system, non-integer-microsecond pulse/space lengths,
37 * done using fixed point binary. So, much more accurate carrier
38 * frequency.
39 * - fine tuned transmitter latency, taking advantage of fractional
40 * microseconds in previous change
41 * - Fixed bug in the way transmitter latency was accounted for by
42 * tuning the pulse lengths down - the send_pulse routine ignored
43 * this overhead as it timed the overall pulse length - so the
44 * pulse frequency was right but overall pulse length was too
45 * long. Fixed by accounting for latency on each pulse/space
46 * iteration.
47 *
48 * Steve Davies <steve@daviesfam.org> July 2001
49 */
50
51 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52
53 #include <linux/module.h>
54 #include <linux/errno.h>
55 #include <linux/signal.h>
56 #include <linux/sched.h>
57 #include <linux/fs.h>
58 #include <linux/interrupt.h>
59 #include <linux/ioport.h>
60 #include <linux/kernel.h>
61 #include <linux/serial_reg.h>
62 #include <linux/ktime.h>
63 #include <linux/string.h>
64 #include <linux/types.h>
65 #include <linux/wait.h>
66 #include <linux/mm.h>
67 #include <linux/delay.h>
68 #include <linux/poll.h>
69 #include <linux/platform_device.h>
70 #include <linux/gpio.h>
71 #include <linux/io.h>
72 #include <linux/irq.h>
73 #include <linux/fcntl.h>
74 #include <linux/spinlock.h>
75
76 /* From Intel IXP42X Developer's Manual (#252480-005): */
77 /* ftp://download.intel.com/design/network/manuals/25248005.pdf */
78 #define UART_IE_IXP42X_UUE 0x40 /* IXP42X UART Unit enable */
79 #define UART_IE_IXP42X_RTOIE 0x10 /* IXP42X Receiver Data Timeout int.enable */
80
81 #include <media/lirc.h>
82 #include <media/lirc_dev.h>
83
84 #define LIRC_DRIVER_NAME "lirc_serial"
85
86 struct lirc_serial {
87 int signal_pin;
88 int signal_pin_change;
89 u8 on;
90 u8 off;
91 long (*send_pulse)(unsigned long length);
92 void (*send_space)(long length);
93 int features;
94 spinlock_t lock;
95 };
96
97 #define LIRC_HOMEBREW 0
98 #define LIRC_IRDEO 1
99 #define LIRC_IRDEO_REMOTE 2
100 #define LIRC_ANIMAX 3
101 #define LIRC_IGOR 4
102 #define LIRC_NSLU2 5
103
104 /*** module parameters ***/
105 static int type;
106 static int io;
107 static int irq;
108 static bool iommap;
109 static int ioshift;
110 static bool softcarrier = true;
111 static bool share_irq;
112 static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */
113 static bool txsense; /* 0 = active high, 1 = active low */
114
115 /* forward declarations */
116 static long send_pulse_irdeo(unsigned long length);
117 static long send_pulse_homebrew(unsigned long length);
118 static void send_space_irdeo(long length);
119 static void send_space_homebrew(long length);
120
121 static struct lirc_serial hardware[] = {
122 [LIRC_HOMEBREW] = {
123 .lock = __SPIN_LOCK_UNLOCKED(hardware[LIRC_HOMEBREW].lock),
124 .signal_pin = UART_MSR_DCD,
125 .signal_pin_change = UART_MSR_DDCD,
126 .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR),
127 .off = (UART_MCR_RTS | UART_MCR_OUT2),
128 .send_pulse = send_pulse_homebrew,
129 .send_space = send_space_homebrew,
130 #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER
131 .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE |
132 LIRC_CAN_SET_SEND_CARRIER |
133 LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2)
134 #else
135 .features = LIRC_CAN_REC_MODE2
136 #endif
137 },
138
139 [LIRC_IRDEO] = {
140 .lock = __SPIN_LOCK_UNLOCKED(hardware[LIRC_IRDEO].lock),
141 .signal_pin = UART_MSR_DSR,
142 .signal_pin_change = UART_MSR_DDSR,
143 .on = UART_MCR_OUT2,
144 .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2),
145 .send_pulse = send_pulse_irdeo,
146 .send_space = send_space_irdeo,
147 .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE |
148 LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2)
149 },
150
151 [LIRC_IRDEO_REMOTE] = {
152 .lock = __SPIN_LOCK_UNLOCKED(hardware[LIRC_IRDEO_REMOTE].lock),
153 .signal_pin = UART_MSR_DSR,
154 .signal_pin_change = UART_MSR_DDSR,
155 .on = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2),
156 .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2),
157 .send_pulse = send_pulse_irdeo,
158 .send_space = send_space_irdeo,
159 .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE |
160 LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2)
161 },
162
163 [LIRC_ANIMAX] = {
164 .lock = __SPIN_LOCK_UNLOCKED(hardware[LIRC_ANIMAX].lock),
165 .signal_pin = UART_MSR_DCD,
166 .signal_pin_change = UART_MSR_DDCD,
167 .on = 0,
168 .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2),
169 .send_pulse = NULL,
170 .send_space = NULL,
171 .features = LIRC_CAN_REC_MODE2
172 },
173
174 [LIRC_IGOR] = {
175 .lock = __SPIN_LOCK_UNLOCKED(hardware[LIRC_IGOR].lock),
176 .signal_pin = UART_MSR_DSR,
177 .signal_pin_change = UART_MSR_DDSR,
178 .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR),
179 .off = (UART_MCR_RTS | UART_MCR_OUT2),
180 .send_pulse = send_pulse_homebrew,
181 .send_space = send_space_homebrew,
182 #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER
183 .features = (LIRC_CAN_SET_SEND_DUTY_CYCLE |
184 LIRC_CAN_SET_SEND_CARRIER |
185 LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2)
186 #else
187 .features = LIRC_CAN_REC_MODE2
188 #endif
189 },
190 };
191
192 #define RS_ISR_PASS_LIMIT 256
193
194 /*
195 * A long pulse code from a remote might take up to 300 bytes. The
196 * daemon should read the bytes as soon as they are generated, so take
197 * the number of keys you think you can push before the daemon runs
198 * and multiply by 300. The driver will warn you if you overrun this
199 * buffer. If you have a slow computer or non-busmastering IDE disks,
200 * maybe you will need to increase this.
201 */
202
203 /* This MUST be a power of two! It has to be larger than 1 as well. */
204
205 #define RBUF_LEN 256
206
207 static ktime_t lastkt;
208
209 static struct lirc_buffer rbuf;
210
211 static unsigned int freq = 38000;
212 static unsigned int duty_cycle = 50;
213
214 /* Initialized in init_timing_params() */
215 static unsigned long period;
216 static unsigned long pulse_width;
217 static unsigned long space_width;
218
219 #if defined(__i386__)
220 /*
221 * From:
222 * Linux I/O port programming mini-HOWTO
223 * Author: Riku Saikkonen <Riku.Saikkonen@hut.fi>
224 * v, 28 December 1997
225 *
226 * [...]
227 * Actually, a port I/O instruction on most ports in the 0-0x3ff range
228 * takes almost exactly 1 microsecond, so if you're, for example, using
229 * the parallel port directly, just do additional inb()s from that port
230 * to delay.
231 * [...]
232 */
233 /* transmitter latency 1.5625us 0x1.90 - this figure arrived at from
234 * comment above plus trimming to match actual measured frequency.
235 * This will be sensitive to cpu speed, though hopefully most of the 1.5us
236 * is spent in the uart access. Still - for reference test machine was a
237 * 1.13GHz Athlon system - Steve
238 */
239
240 /*
241 * changed from 400 to 450 as this works better on slower machines;
242 * faster machines will use the rdtsc code anyway
243 */
244 #define LIRC_SERIAL_TRANSMITTER_LATENCY 450
245
246 #else
247
248 /* does anybody have information on other platforms ? */
249 /* 256 = 1<<8 */
250 #define LIRC_SERIAL_TRANSMITTER_LATENCY 256
251
252 #endif /* __i386__ */
253 /*
254 * FIXME: should we be using hrtimers instead of this
255 * LIRC_SERIAL_TRANSMITTER_LATENCY nonsense?
256 */
257
258 /* fetch serial input packet (1 byte) from register offset */
sinp(int offset)259 static u8 sinp(int offset)
260 {
261 if (iommap)
262 /* the register is memory-mapped */
263 offset <<= ioshift;
264
265 return inb(io + offset);
266 }
267
268 /* write serial output packet (1 byte) of value to register offset */
soutp(int offset,u8 value)269 static void soutp(int offset, u8 value)
270 {
271 if (iommap)
272 /* the register is memory-mapped */
273 offset <<= ioshift;
274
275 outb(value, io + offset);
276 }
277
on(void)278 static void on(void)
279 {
280 if (txsense)
281 soutp(UART_MCR, hardware[type].off);
282 else
283 soutp(UART_MCR, hardware[type].on);
284 }
285
off(void)286 static void off(void)
287 {
288 if (txsense)
289 soutp(UART_MCR, hardware[type].on);
290 else
291 soutp(UART_MCR, hardware[type].off);
292 }
293
294 #ifndef MAX_UDELAY_MS
295 #define MAX_UDELAY_US 5000
296 #else
297 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
298 #endif
299
safe_udelay(unsigned long usecs)300 static void safe_udelay(unsigned long usecs)
301 {
302 while (usecs > MAX_UDELAY_US) {
303 udelay(MAX_UDELAY_US);
304 usecs -= MAX_UDELAY_US;
305 }
306 udelay(usecs);
307 }
308
309 #ifdef USE_RDTSC
310 /*
311 * This is an overflow/precision juggle, complicated in that we can't
312 * do long long divide in the kernel
313 */
314
315 /*
316 * When we use the rdtsc instruction to measure clocks, we keep the
317 * pulse and space widths as clock cycles. As this is CPU speed
318 * dependent, the widths must be calculated in init_port and ioctl
319 * time
320 */
321
init_timing_params(unsigned int new_duty_cycle,unsigned int new_freq)322 static int init_timing_params(unsigned int new_duty_cycle,
323 unsigned int new_freq)
324 {
325 __u64 loops_per_sec, work;
326
327 duty_cycle = new_duty_cycle;
328 freq = new_freq;
329
330 loops_per_sec = __this_cpu_read(cpu.info.loops_per_jiffy);
331 loops_per_sec *= HZ;
332
333 /* How many clocks in a microsecond?, avoiding long long divide */
334 work = loops_per_sec;
335 work *= 4295; /* 4295 = 2^32 / 1e6 */
336
337 /*
338 * Carrier period in clocks, approach good up to 32GHz clock,
339 * gets carrier frequency within 8Hz
340 */
341 period = loops_per_sec >> 3;
342 period /= (freq >> 3);
343
344 /* Derive pulse and space from the period */
345 pulse_width = period * duty_cycle / 100;
346 space_width = period - pulse_width;
347 pr_debug("in init_timing_params, freq=%d, duty_cycle=%d, clk/jiffy=%ld, pulse=%ld, space=%ld, conv_us_to_clocks=%ld\n",
348 freq, duty_cycle, __this_cpu_read(cpu_info.loops_per_jiffy),
349 pulse_width, space_width, conv_us_to_clocks);
350 return 0;
351 }
352 #else /* ! USE_RDTSC */
init_timing_params(unsigned int new_duty_cycle,unsigned int new_freq)353 static int init_timing_params(unsigned int new_duty_cycle,
354 unsigned int new_freq)
355 {
356 /*
357 * period, pulse/space width are kept with 8 binary places -
358 * IE multiplied by 256.
359 */
360 if (256 * 1000000L / new_freq * new_duty_cycle / 100 <=
361 LIRC_SERIAL_TRANSMITTER_LATENCY)
362 return -EINVAL;
363 if (256 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
364 LIRC_SERIAL_TRANSMITTER_LATENCY)
365 return -EINVAL;
366 duty_cycle = new_duty_cycle;
367 freq = new_freq;
368 period = 256 * 1000000L / freq;
369 pulse_width = period * duty_cycle / 100;
370 space_width = period - pulse_width;
371 pr_debug("in init_timing_params, freq=%d pulse=%ld, space=%ld\n",
372 freq, pulse_width, space_width);
373 return 0;
374 }
375 #endif /* USE_RDTSC */
376
377
378 /* return value: space length delta */
379
send_pulse_irdeo(unsigned long length)380 static long send_pulse_irdeo(unsigned long length)
381 {
382 long rawbits, ret;
383 int i;
384 unsigned char output;
385 unsigned char chunk, shifted;
386
387 /* how many bits have to be sent ? */
388 rawbits = length * 1152 / 10000;
389 if (duty_cycle > 50)
390 chunk = 3;
391 else
392 chunk = 1;
393 for (i = 0, output = 0x7f; rawbits > 0; rawbits -= 3) {
394 shifted = chunk << (i * 3);
395 shifted >>= 1;
396 output &= (~shifted);
397 i++;
398 if (i == 3) {
399 soutp(UART_TX, output);
400 while (!(sinp(UART_LSR) & UART_LSR_THRE))
401 ;
402 output = 0x7f;
403 i = 0;
404 }
405 }
406 if (i != 0) {
407 soutp(UART_TX, output);
408 while (!(sinp(UART_LSR) & UART_LSR_TEMT))
409 ;
410 }
411
412 if (i == 0)
413 ret = (-rawbits) * 10000 / 1152;
414 else
415 ret = (3 - i) * 3 * 10000 / 1152 + (-rawbits) * 10000 / 1152;
416
417 return ret;
418 }
419
420 /* Version using udelay() */
421
422 /*
423 * here we use fixed point arithmetic, with 8
424 * fractional bits. that gets us within 0.1% or so of the right average
425 * frequency, albeit with some jitter in pulse length - Steve
426 *
427 * This should use ndelay instead.
428 */
429
430 /* To match 8 fractional bits used for pulse/space length */
431
send_pulse_homebrew_softcarrier(unsigned long length)432 static long send_pulse_homebrew_softcarrier(unsigned long length)
433 {
434 int flag;
435 unsigned long actual, target, d;
436
437 length <<= 8;
438
439 actual = 0; target = 0; flag = 0;
440 while (actual < length) {
441 if (flag) {
442 off();
443 target += space_width;
444 } else {
445 on();
446 target += pulse_width;
447 }
448 d = (target - actual -
449 LIRC_SERIAL_TRANSMITTER_LATENCY + 128) >> 8;
450 /*
451 * Note - we've checked in ioctl that the pulse/space
452 * widths are big enough so that d is > 0
453 */
454 udelay(d);
455 actual += (d << 8) + LIRC_SERIAL_TRANSMITTER_LATENCY;
456 flag = !flag;
457 }
458 return (actual-length) >> 8;
459 }
460
send_pulse_homebrew(unsigned long length)461 static long send_pulse_homebrew(unsigned long length)
462 {
463 if (length <= 0)
464 return 0;
465
466 if (softcarrier)
467 return send_pulse_homebrew_softcarrier(length);
468
469 on();
470 safe_udelay(length);
471 return 0;
472 }
473
send_space_irdeo(long length)474 static void send_space_irdeo(long length)
475 {
476 if (length <= 0)
477 return;
478
479 safe_udelay(length);
480 }
481
send_space_homebrew(long length)482 static void send_space_homebrew(long length)
483 {
484 off();
485 if (length <= 0)
486 return;
487 safe_udelay(length);
488 }
489
rbwrite(int l)490 static void rbwrite(int l)
491 {
492 if (lirc_buffer_full(&rbuf)) {
493 /* no new signals will be accepted */
494 pr_debug("Buffer overrun\n");
495 return;
496 }
497 lirc_buffer_write(&rbuf, (void *)&l);
498 }
499
frbwrite(int l)500 static void frbwrite(int l)
501 {
502 /* simple noise filter */
503 static int pulse, space;
504 static unsigned int ptr;
505
506 if (ptr > 0 && (l & PULSE_BIT)) {
507 pulse += l & PULSE_MASK;
508 if (pulse > 250) {
509 rbwrite(space);
510 rbwrite(pulse | PULSE_BIT);
511 ptr = 0;
512 pulse = 0;
513 }
514 return;
515 }
516 if (!(l & PULSE_BIT)) {
517 if (ptr == 0) {
518 if (l > 20000) {
519 space = l;
520 ptr++;
521 return;
522 }
523 } else {
524 if (l > 20000) {
525 space += pulse;
526 if (space > PULSE_MASK)
527 space = PULSE_MASK;
528 space += l;
529 if (space > PULSE_MASK)
530 space = PULSE_MASK;
531 pulse = 0;
532 return;
533 }
534 rbwrite(space);
535 rbwrite(pulse | PULSE_BIT);
536 ptr = 0;
537 pulse = 0;
538 }
539 }
540 rbwrite(l);
541 }
542
lirc_irq_handler(int i,void * blah)543 static irqreturn_t lirc_irq_handler(int i, void *blah)
544 {
545 ktime_t kt;
546 int counter, dcd;
547 u8 status;
548 ktime_t delkt;
549 int data;
550 static int last_dcd = -1;
551
552 if ((sinp(UART_IIR) & UART_IIR_NO_INT)) {
553 /* not our interrupt */
554 return IRQ_NONE;
555 }
556
557 counter = 0;
558 do {
559 counter++;
560 status = sinp(UART_MSR);
561 if (counter > RS_ISR_PASS_LIMIT) {
562 pr_warn("AIEEEE: We're caught!\n");
563 break;
564 }
565 if ((status & hardware[type].signal_pin_change)
566 && sense != -1) {
567 /* get current time */
568 kt = ktime_get();
569
570 /* New mode, written by Trent Piepho
571 <xyzzy@u.washington.edu>. */
572
573 /*
574 * The old format was not very portable.
575 * We now use an int to pass pulses
576 * and spaces to user space.
577 *
578 * If PULSE_BIT is set a pulse has been
579 * received, otherwise a space has been
580 * received. The driver needs to know if your
581 * receiver is active high or active low, or
582 * the space/pulse sense could be
583 * inverted. The bits denoted by PULSE_MASK are
584 * the length in microseconds. Lengths greater
585 * than or equal to 16 seconds are clamped to
586 * PULSE_MASK. All other bits are unused.
587 * This is a much simpler interface for user
588 * programs, as well as eliminating "out of
589 * phase" errors with space/pulse
590 * autodetection.
591 */
592
593 /* calc time since last interrupt in microseconds */
594 dcd = (status & hardware[type].signal_pin) ? 1 : 0;
595
596 if (dcd == last_dcd) {
597 pr_warn("ignoring spike: %d %d %llx %llx\n",
598 dcd, sense, ktime_to_us(kt),
599 ktime_to_us(lastkt));
600 continue;
601 }
602
603 delkt = ktime_sub(kt, lastkt);
604 if (ktime_compare(delkt, ktime_set(15, 0)) > 0) {
605 data = PULSE_MASK; /* really long time */
606 if (!(dcd^sense)) {
607 /* sanity check */
608 pr_warn("AIEEEE: %d %d %llx %llx\n",
609 dcd, sense, ktime_to_us(kt),
610 ktime_to_us(lastkt));
611 /*
612 * detecting pulse while this
613 * MUST be a space!
614 */
615 sense = sense ? 0 : 1;
616 }
617 } else
618 data = (int) ktime_to_us(delkt);
619 frbwrite(dcd^sense ? data : (data|PULSE_BIT));
620 lastkt = kt;
621 last_dcd = dcd;
622 wake_up_interruptible(&rbuf.wait_poll);
623 }
624 } while (!(sinp(UART_IIR) & UART_IIR_NO_INT)); /* still pending ? */
625 return IRQ_HANDLED;
626 }
627
628
hardware_init_port(void)629 static int hardware_init_port(void)
630 {
631 u8 scratch, scratch2, scratch3;
632
633 /*
634 * This is a simple port existence test, borrowed from the autoconfig
635 * function in drivers/serial/8250.c
636 */
637 scratch = sinp(UART_IER);
638 soutp(UART_IER, 0);
639 #ifdef __i386__
640 outb(0xff, 0x080);
641 #endif
642 scratch2 = sinp(UART_IER) & 0x0f;
643 soutp(UART_IER, 0x0f);
644 #ifdef __i386__
645 outb(0x00, 0x080);
646 #endif
647 scratch3 = sinp(UART_IER) & 0x0f;
648 soutp(UART_IER, scratch);
649 if (scratch2 != 0 || scratch3 != 0x0f) {
650 /* we fail, there's nothing here */
651 pr_err("port existence test failed, cannot continue\n");
652 return -ENODEV;
653 }
654
655
656
657 /* Set DLAB 0. */
658 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
659
660 /* First of all, disable all interrupts */
661 soutp(UART_IER, sinp(UART_IER) &
662 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
663
664 /* Clear registers. */
665 sinp(UART_LSR);
666 sinp(UART_RX);
667 sinp(UART_IIR);
668 sinp(UART_MSR);
669
670 /* Set line for power source */
671 off();
672
673 /* Clear registers again to be sure. */
674 sinp(UART_LSR);
675 sinp(UART_RX);
676 sinp(UART_IIR);
677 sinp(UART_MSR);
678
679 switch (type) {
680 case LIRC_IRDEO:
681 case LIRC_IRDEO_REMOTE:
682 /* setup port to 7N1 @ 115200 Baud */
683 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 38kHz */
684
685 /* Set DLAB 1. */
686 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
687 /* Set divisor to 1 => 115200 Baud */
688 soutp(UART_DLM, 0);
689 soutp(UART_DLL, 1);
690 /* Set DLAB 0 + 7N1 */
691 soutp(UART_LCR, UART_LCR_WLEN7);
692 /* THR interrupt already disabled at this point */
693 break;
694 default:
695 break;
696 }
697
698 return 0;
699 }
700
lirc_serial_probe(struct platform_device * dev)701 static int lirc_serial_probe(struct platform_device *dev)
702 {
703 int i, nlow, nhigh, result;
704
705 result = devm_request_irq(&dev->dev, irq, lirc_irq_handler,
706 (share_irq ? IRQF_SHARED : 0),
707 LIRC_DRIVER_NAME, &hardware);
708 if (result < 0) {
709 if (result == -EBUSY)
710 dev_err(&dev->dev, "IRQ %d busy\n", irq);
711 else if (result == -EINVAL)
712 dev_err(&dev->dev, "Bad irq number or handler\n");
713 return result;
714 }
715
716 /* Reserve io region. */
717 /*
718 * Future MMAP-Developers: Attention!
719 * For memory mapped I/O you *might* need to use ioremap() first,
720 * for the NSLU2 it's done in boot code.
721 */
722 if (((iommap)
723 && (devm_request_mem_region(&dev->dev, iommap, 8 << ioshift,
724 LIRC_DRIVER_NAME) == NULL))
725 || ((!iommap)
726 && (devm_request_region(&dev->dev, io, 8,
727 LIRC_DRIVER_NAME) == NULL))) {
728 dev_err(&dev->dev, "port %04x already in use\n", io);
729 dev_warn(&dev->dev, "use 'setserial /dev/ttySX uart none'\n");
730 dev_warn(&dev->dev,
731 "or compile the serial port driver as module and\n");
732 dev_warn(&dev->dev, "make sure this module is loaded first\n");
733 return -EBUSY;
734 }
735
736 result = hardware_init_port();
737 if (result < 0)
738 return result;
739
740 /* Initialize pulse/space widths */
741 init_timing_params(duty_cycle, freq);
742
743 /* If pin is high, then this must be an active low receiver. */
744 if (sense == -1) {
745 /* wait 1/2 sec for the power supply */
746 msleep(500);
747
748 /*
749 * probe 9 times every 0.04s, collect "votes" for
750 * active high/low
751 */
752 nlow = 0;
753 nhigh = 0;
754 for (i = 0; i < 9; i++) {
755 if (sinp(UART_MSR) & hardware[type].signal_pin)
756 nlow++;
757 else
758 nhigh++;
759 msleep(40);
760 }
761 sense = nlow >= nhigh ? 1 : 0;
762 dev_info(&dev->dev, "auto-detected active %s receiver\n",
763 sense ? "low" : "high");
764 } else
765 dev_info(&dev->dev, "Manually using active %s receiver\n",
766 sense ? "low" : "high");
767
768 dev_dbg(&dev->dev, "Interrupt %d, port %04x obtained\n", irq, io);
769 return 0;
770 }
771
set_use_inc(void * data)772 static int set_use_inc(void *data)
773 {
774 unsigned long flags;
775
776 /* initialize timestamp */
777 lastkt = ktime_get();
778
779 spin_lock_irqsave(&hardware[type].lock, flags);
780
781 /* Set DLAB 0. */
782 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
783
784 soutp(UART_IER, sinp(UART_IER)|UART_IER_MSI);
785
786 spin_unlock_irqrestore(&hardware[type].lock, flags);
787
788 return 0;
789 }
790
set_use_dec(void * data)791 static void set_use_dec(void *data)
792 { unsigned long flags;
793
794 spin_lock_irqsave(&hardware[type].lock, flags);
795
796 /* Set DLAB 0. */
797 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
798
799 /* First of all, disable all interrupts */
800 soutp(UART_IER, sinp(UART_IER) &
801 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
802 spin_unlock_irqrestore(&hardware[type].lock, flags);
803 }
804
lirc_write(struct file * file,const char __user * buf,size_t n,loff_t * ppos)805 static ssize_t lirc_write(struct file *file, const char __user *buf,
806 size_t n, loff_t *ppos)
807 {
808 int i, count;
809 unsigned long flags;
810 long delta = 0;
811 int *wbuf;
812
813 if (!(hardware[type].features & LIRC_CAN_SEND_PULSE))
814 return -EPERM;
815
816 count = n / sizeof(int);
817 if (n % sizeof(int) || count % 2 == 0)
818 return -EINVAL;
819 wbuf = memdup_user(buf, n);
820 if (IS_ERR(wbuf))
821 return PTR_ERR(wbuf);
822 spin_lock_irqsave(&hardware[type].lock, flags);
823 if (type == LIRC_IRDEO) {
824 /* DTR, RTS down */
825 on();
826 }
827 for (i = 0; i < count; i++) {
828 if (i%2)
829 hardware[type].send_space(wbuf[i] - delta);
830 else
831 delta = hardware[type].send_pulse(wbuf[i]);
832 }
833 off();
834 spin_unlock_irqrestore(&hardware[type].lock, flags);
835 kfree(wbuf);
836 return n;
837 }
838
lirc_ioctl(struct file * filep,unsigned int cmd,unsigned long arg)839 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
840 {
841 int result;
842 u32 __user *uptr = (u32 __user *)arg;
843 u32 value;
844
845 switch (cmd) {
846 case LIRC_GET_SEND_MODE:
847 if (!(hardware[type].features&LIRC_CAN_SEND_MASK))
848 return -ENOIOCTLCMD;
849
850 result = put_user(LIRC_SEND2MODE
851 (hardware[type].features&LIRC_CAN_SEND_MASK),
852 uptr);
853 if (result)
854 return result;
855 break;
856
857 case LIRC_SET_SEND_MODE:
858 if (!(hardware[type].features&LIRC_CAN_SEND_MASK))
859 return -ENOIOCTLCMD;
860
861 result = get_user(value, uptr);
862 if (result)
863 return result;
864 /* only LIRC_MODE_PULSE supported */
865 if (value != LIRC_MODE_PULSE)
866 return -EINVAL;
867 break;
868
869 case LIRC_GET_LENGTH:
870 return -ENOIOCTLCMD;
871
872 case LIRC_SET_SEND_DUTY_CYCLE:
873 pr_debug("SET_SEND_DUTY_CYCLE\n");
874 if (!(hardware[type].features&LIRC_CAN_SET_SEND_DUTY_CYCLE))
875 return -ENOIOCTLCMD;
876
877 result = get_user(value, uptr);
878 if (result)
879 return result;
880 if (value <= 0 || value > 100)
881 return -EINVAL;
882 return init_timing_params(value, freq);
883
884 case LIRC_SET_SEND_CARRIER:
885 pr_debug("SET_SEND_CARRIER\n");
886 if (!(hardware[type].features&LIRC_CAN_SET_SEND_CARRIER))
887 return -ENOIOCTLCMD;
888
889 result = get_user(value, uptr);
890 if (result)
891 return result;
892 if (value > 500000 || value < 20000)
893 return -EINVAL;
894 return init_timing_params(duty_cycle, value);
895
896 default:
897 return lirc_dev_fop_ioctl(filep, cmd, arg);
898 }
899 return 0;
900 }
901
902 static const struct file_operations lirc_fops = {
903 .owner = THIS_MODULE,
904 .write = lirc_write,
905 .unlocked_ioctl = lirc_ioctl,
906 #ifdef CONFIG_COMPAT
907 .compat_ioctl = lirc_ioctl,
908 #endif
909 .read = lirc_dev_fop_read,
910 .poll = lirc_dev_fop_poll,
911 .open = lirc_dev_fop_open,
912 .release = lirc_dev_fop_close,
913 .llseek = no_llseek,
914 };
915
916 static struct lirc_driver driver = {
917 .name = LIRC_DRIVER_NAME,
918 .minor = -1,
919 .code_length = 1,
920 .sample_rate = 0,
921 .data = NULL,
922 .add_to_buf = NULL,
923 .rbuf = &rbuf,
924 .set_use_inc = set_use_inc,
925 .set_use_dec = set_use_dec,
926 .fops = &lirc_fops,
927 .dev = NULL,
928 .owner = THIS_MODULE,
929 };
930
931 static struct platform_device *lirc_serial_dev;
932
lirc_serial_suspend(struct platform_device * dev,pm_message_t state)933 static int lirc_serial_suspend(struct platform_device *dev,
934 pm_message_t state)
935 {
936 /* Set DLAB 0. */
937 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
938
939 /* Disable all interrupts */
940 soutp(UART_IER, sinp(UART_IER) &
941 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
942
943 /* Clear registers. */
944 sinp(UART_LSR);
945 sinp(UART_RX);
946 sinp(UART_IIR);
947 sinp(UART_MSR);
948
949 return 0;
950 }
951
952 /* twisty maze... need a forward-declaration here... */
953 static void lirc_serial_exit(void);
954
lirc_serial_resume(struct platform_device * dev)955 static int lirc_serial_resume(struct platform_device *dev)
956 {
957 unsigned long flags;
958 int result;
959
960 result = hardware_init_port();
961 if (result < 0)
962 return result;
963
964 spin_lock_irqsave(&hardware[type].lock, flags);
965 /* Enable Interrupt */
966 lastkt = ktime_get();
967 soutp(UART_IER, sinp(UART_IER)|UART_IER_MSI);
968 off();
969
970 lirc_buffer_clear(&rbuf);
971
972 spin_unlock_irqrestore(&hardware[type].lock, flags);
973
974 return 0;
975 }
976
977 static struct platform_driver lirc_serial_driver = {
978 .probe = lirc_serial_probe,
979 .suspend = lirc_serial_suspend,
980 .resume = lirc_serial_resume,
981 .driver = {
982 .name = "lirc_serial",
983 },
984 };
985
lirc_serial_init(void)986 static int __init lirc_serial_init(void)
987 {
988 int result;
989
990 /* Init read buffer. */
991 result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
992 if (result < 0)
993 return result;
994
995 result = platform_driver_register(&lirc_serial_driver);
996 if (result) {
997 printk("lirc register returned %d\n", result);
998 goto exit_buffer_free;
999 }
1000
1001 lirc_serial_dev = platform_device_alloc("lirc_serial", 0);
1002 if (!lirc_serial_dev) {
1003 result = -ENOMEM;
1004 goto exit_driver_unregister;
1005 }
1006
1007 result = platform_device_add(lirc_serial_dev);
1008 if (result)
1009 goto exit_device_put;
1010
1011 return 0;
1012
1013 exit_device_put:
1014 platform_device_put(lirc_serial_dev);
1015 exit_driver_unregister:
1016 platform_driver_unregister(&lirc_serial_driver);
1017 exit_buffer_free:
1018 lirc_buffer_free(&rbuf);
1019 return result;
1020 }
1021
lirc_serial_exit(void)1022 static void lirc_serial_exit(void)
1023 {
1024 platform_device_unregister(lirc_serial_dev);
1025 platform_driver_unregister(&lirc_serial_driver);
1026 lirc_buffer_free(&rbuf);
1027 }
1028
lirc_serial_init_module(void)1029 static int __init lirc_serial_init_module(void)
1030 {
1031 int result;
1032
1033 switch (type) {
1034 case LIRC_HOMEBREW:
1035 case LIRC_IRDEO:
1036 case LIRC_IRDEO_REMOTE:
1037 case LIRC_ANIMAX:
1038 case LIRC_IGOR:
1039 /* if nothing specified, use ttyS0/com1 and irq 4 */
1040 io = io ? io : 0x3f8;
1041 irq = irq ? irq : 4;
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046 if (!softcarrier) {
1047 switch (type) {
1048 case LIRC_HOMEBREW:
1049 case LIRC_IGOR:
1050 hardware[type].features &=
1051 ~(LIRC_CAN_SET_SEND_DUTY_CYCLE|
1052 LIRC_CAN_SET_SEND_CARRIER);
1053 break;
1054 }
1055 }
1056
1057 /* make sure sense is either -1, 0, or 1 */
1058 if (sense != -1)
1059 sense = !!sense;
1060
1061 result = lirc_serial_init();
1062 if (result)
1063 return result;
1064
1065 driver.features = hardware[type].features;
1066 driver.dev = &lirc_serial_dev->dev;
1067 driver.minor = lirc_register_driver(&driver);
1068 if (driver.minor < 0) {
1069 pr_err("register_chrdev failed!\n");
1070 lirc_serial_exit();
1071 return driver.minor;
1072 }
1073 return 0;
1074 }
1075
lirc_serial_exit_module(void)1076 static void __exit lirc_serial_exit_module(void)
1077 {
1078 lirc_unregister_driver(driver.minor);
1079 lirc_serial_exit();
1080 pr_debug("cleaned up module\n");
1081 }
1082
1083
1084 module_init(lirc_serial_init_module);
1085 module_exit(lirc_serial_exit_module);
1086
1087 MODULE_DESCRIPTION("Infra-red receiver driver for serial ports.");
1088 MODULE_AUTHOR("Ralph Metzler, Trent Piepho, Ben Pfaff, "
1089 "Christoph Bartelmus, Andrei Tanas");
1090 MODULE_LICENSE("GPL");
1091
1092 module_param(type, int, S_IRUGO);
1093 MODULE_PARM_DESC(type, "Hardware type (0 = home-brew, 1 = IRdeo,"
1094 " 2 = IRdeo Remote, 3 = AnimaX, 4 = IgorPlug,"
1095 " 5 = NSLU2 RX:CTS2/TX:GreenLED)");
1096
1097 module_param(io, int, S_IRUGO);
1098 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1099
1100 /* some architectures (e.g. intel xscale) have memory mapped registers */
1101 module_param(iommap, bool, S_IRUGO);
1102 MODULE_PARM_DESC(iommap, "physical base for memory mapped I/O"
1103 " (0 = no memory mapped io)");
1104
1105 /*
1106 * some architectures (e.g. intel xscale) align the 8bit serial registers
1107 * on 32bit word boundaries.
1108 * See linux-kernel/drivers/tty/serial/8250/8250.c serial_in()/out()
1109 */
1110 module_param(ioshift, int, S_IRUGO);
1111 MODULE_PARM_DESC(ioshift, "shift I/O register offset (0 = no shift)");
1112
1113 module_param(irq, int, S_IRUGO);
1114 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1115
1116 module_param(share_irq, bool, S_IRUGO);
1117 MODULE_PARM_DESC(share_irq, "Share interrupts (0 = off, 1 = on)");
1118
1119 module_param(sense, int, S_IRUGO);
1120 MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
1121 " (0 = active high, 1 = active low )");
1122
1123 #ifdef CONFIG_LIRC_SERIAL_TRANSMITTER
1124 module_param(txsense, bool, S_IRUGO);
1125 MODULE_PARM_DESC(txsense, "Sense of transmitter circuit"
1126 " (0 = active high, 1 = active low )");
1127 #endif
1128
1129 module_param(softcarrier, bool, S_IRUGO);
1130 MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
1131