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/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_layer.c45 atmel_hlcdc_layer_fb_flip_release_queue(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_fb_flip_release_queue() argument
53 for (i = 0; i < layer->max_planes; i++) { in atmel_hlcdc_layer_fb_flip_release_queue()
61 drm_flip_work_queue_task(&layer->gc, flip->task); in atmel_hlcdc_layer_fb_flip_release_queue()
62 drm_flip_work_commit(&layer->gc, layer->wq); in atmel_hlcdc_layer_fb_flip_release_queue()
65 static void atmel_hlcdc_layer_update_reset(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_update_reset() argument
68 struct atmel_hlcdc_layer_update *upd = &layer->update; in atmel_hlcdc_layer_update_reset()
75 bitmap_clear(slot->updated_configs, 0, layer->desc->nconfigs); in atmel_hlcdc_layer_update_reset()
77 sizeof(*slot->configs) * layer->desc->nconfigs); in atmel_hlcdc_layer_update_reset()
80 atmel_hlcdc_layer_fb_flip_release_queue(layer, slot->fb_flip); in atmel_hlcdc_layer_update_reset()
85 static void atmel_hlcdc_layer_update_apply(struct atmel_hlcdc_layer *layer) in atmel_hlcdc_layer_update_apply() argument
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Datmel_hlcdc_plane.c267 &plane->layer.desc->layout; in atmel_hlcdc_plane_update_pos_and_size()
270 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
277 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
284 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
303 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
326 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
340 atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff, in atmel_hlcdc_plane_update_pos_and_size()
343 atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff, 0); in atmel_hlcdc_plane_update_pos_and_size()
352 &plane->layer.desc->layout; in atmel_hlcdc_plane_update_general_settings()
366 atmel_hlcdc_layer_update_cfg(&plane->layer, in atmel_hlcdc_plane_update_general_settings()
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Datmel_hlcdc_layer.h371 void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer);
374 struct atmel_hlcdc_layer *layer,
378 struct atmel_hlcdc_layer *layer);
380 void atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer);
382 int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer);
384 void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg,
387 void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer,
391 void atmel_hlcdc_layer_update_set_finished(struct atmel_hlcdc_layer *layer,
395 void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer);
397 void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer);
Datmel_hlcdc_dc.c413 struct atmel_hlcdc_layer *layer = dc->layers[i]; in atmel_hlcdc_dc_irq_handler() local
415 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer) in atmel_hlcdc_dc_irq_handler()
418 atmel_hlcdc_layer_irq(layer); in atmel_hlcdc_dc_irq_handler()
566 dc->layers[planes->primary->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
567 &planes->primary->layer; in atmel_hlcdc_dc_modeset_init()
570 dc->layers[planes->cursor->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
571 &planes->cursor->layer; in atmel_hlcdc_dc_modeset_init()
574 dc->layers[planes->overlays[i]->layer.desc->id] = in atmel_hlcdc_dc_modeset_init()
575 &planes->overlays[i]->layer; in atmel_hlcdc_dc_modeset_init()
Datmel_hlcdc_dc.h96 struct atmel_hlcdc_layer layer; member
109 return container_of(l, struct atmel_hlcdc_plane, layer); in atmel_hlcdc_layer_to_plane()
/drivers/media/platform/davinci/
Dvpbe_display.c51 struct vpbe_layer *layer);
72 struct vpbe_layer *layer) in vpbe_isr_even_field() argument
74 if (layer->cur_frm == layer->next_frm) in vpbe_isr_even_field()
77 layer->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns(); in vpbe_isr_even_field()
78 vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE); in vpbe_isr_even_field()
80 layer->cur_frm = layer->next_frm; in vpbe_isr_even_field()
84 struct vpbe_layer *layer) in vpbe_isr_odd_field() argument
90 if (list_empty(&layer->dma_queue) || in vpbe_isr_odd_field()
91 (layer->cur_frm != layer->next_frm)) { in vpbe_isr_odd_field()
101 layer->next_frm = list_entry(layer->dma_queue.next, in vpbe_isr_odd_field()
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Dvpbe_osd.c117 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1)) argument
118 #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1)) argument
424 static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer, in _osd_set_zoom() argument
430 switch (layer) { in _osd_set_zoom()
458 static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer) in _osd_disable_layer() argument
460 switch (layer) { in _osd_disable_layer()
478 static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer) in osd_disable_layer() argument
481 struct osd_window_state *win = &osd->win[layer]; in osd_disable_layer()
492 _osd_disable_layer(sd, layer); in osd_disable_layer()
503 static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer) in _osd_enable_layer() argument
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/drivers/media/dvb-frontends/
Dmb86a20s.c385 unsigned layer) in mb86a20s_get_modulation() argument
394 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_modulation()
396 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_modulation()
417 unsigned layer) in mb86a20s_get_fec() argument
427 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_fec()
429 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_fec()
452 unsigned layer) in mb86a20s_get_interleaving() argument
465 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_interleaving()
467 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_interleaving()
478 unsigned layer) in mb86a20s_get_segment_count() argument
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Ddib8000.c1994 switch (c->layer[layer_index].modulation) { in dib8000_set_layer()
2010 switch (c->layer[layer_index].fec) { in dib8000_set_layer()
2029 time_intlv = fls(c->layer[layer_index].interleaving); in dib8000_set_layer()
2033 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment… in dib8000_set_layer()
2034 if (c->layer[layer_index].segment_count > 0) { in dib8000_set_layer()
2038 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64) in dib8000_set_layer()
2039 max_constellation = c->layer[layer_index].modulation; in dib8000_set_layer()
2042 if (c->layer[layer_index].modulation == QAM_64) in dib8000_set_layer()
2043 max_constellation = c->layer[layer_index].modulation; in dib8000_set_layer()
2199 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
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Dtc90522.c229 c->layer[0].fec = c->fec_inner; in tc90522s_get_frontend()
230 c->layer[0].modulation = c->modulation; in tc90522s_get_frontend()
231 c->layer[0].segment_count = val[3] & 0x3f; /* slots */ in tc90522s_get_frontend()
235 c->layer[1].fec = fec_conv_sat[v]; in tc90522s_get_frontend()
237 c->layer[1].segment_count = 0; in tc90522s_get_frontend()
239 c->layer[1].segment_count = val[4] & 0x3f; /* slots */ in tc90522s_get_frontend()
244 c->layer[1].modulation = QPSK; in tc90522s_get_frontend()
371 c->layer[0].segment_count = 0; in tc90522t_get_frontend()
374 c->layer[0].segment_count = v; in tc90522t_get_frontend()
375 c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2]; in tc90522t_get_frontend()
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/drivers/gpu/drm/sun4i/
Dsun4i_layer.c38 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_disable() local
39 struct sun4i_drv *drv = layer->drv; in sun4i_backend_layer_atomic_disable()
42 sun4i_backend_layer_enable(backend, layer->id, false); in sun4i_backend_layer_atomic_disable()
48 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_update() local
49 struct sun4i_drv *drv = layer->drv; in sun4i_backend_layer_atomic_update()
52 sun4i_backend_update_layer_coord(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
53 sun4i_backend_update_layer_formats(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
54 sun4i_backend_update_layer_buffer(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
55 sun4i_backend_layer_enable(backend, layer->id, true); in sun4i_backend_layer_atomic_update()
104 struct sun4i_layer *layer; in sun4i_layer_init_one() local
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Dsun4i_backend.c70 int layer, bool enable) in sun4i_backend_layer_enable() argument
74 DRM_DEBUG_DRIVER("Enabling layer %d\n", layer); in sun4i_backend_layer_enable()
77 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); in sun4i_backend_layer_enable()
82 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); in sun4i_backend_layer_enable()
114 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_coord() argument
119 DRM_DEBUG_DRIVER("Updating layer %d\n", layer); in sun4i_backend_update_layer_coord()
131 regmap_write(backend->regs, SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), in sun4i_backend_update_layer_coord()
137 regmap_write(backend->regs, SUN4I_BACKEND_LAYSIZE_REG(layer), in sun4i_backend_update_layer_coord()
144 regmap_write(backend->regs, SUN4I_BACKEND_LAYCOOR_REG(layer), in sun4i_backend_update_layer_coord()
153 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_formats() argument
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Dsun4i_backend.h160 int layer, bool enable);
162 int layer, struct drm_plane *plane);
164 int layer, struct drm_plane *plane);
166 int layer, struct drm_plane *plane);
/drivers/gpu/drm/arm/
Dmalidp_planes.c95 format_id = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id, in malidp_de_plane_check()
147 format_id = malidp_hw_get_format_id(map, mp->layer->id, format); in malidp_de_plane_update()
156 malidp_hw_write(mp->hwdev, format_id, mp->layer->base); in malidp_de_plane_update()
160 ptr = mp->layer->ptr + (i << 4); in malidp_de_plane_update()
166 mp->layer->base + MALIDP_LAYER_STRIDE); in malidp_de_plane_update()
170 mp->layer->base + MALIDP_LAYER_SIZE); in malidp_de_plane_update()
173 mp->layer->base + MALIDP_LAYER_COMP_SIZE); in malidp_de_plane_update()
177 mp->layer->base + MALIDP_LAYER_OFFSET); in malidp_de_plane_update()
181 mp->layer->base + MALIDP_LAYER_CONTROL); in malidp_de_plane_update()
196 mp->layer->base + MALIDP_LAYER_CONTROL); in malidp_de_plane_update()
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/drivers/pci/pcie/aer/
Daerdrv_errprint.c168 int layer, agent; in aer_print_error() local
177 layer = AER_GET_LAYER_ERROR(info->severity, info->status); in aer_print_error()
182 aer_error_layer[layer], id, aer_agent_string[agent]); in aer_print_error()
225 int layer, agent, status_strs_size, tlp_header_valid = 0; in cper_print_aer() local
242 layer = AER_GET_LAYER_ERROR(aer_severity, status); in cper_print_aer()
248 aer_error_layer[layer], aer_agent_string[agent]); in cper_print_aer()
/drivers/staging/most/Documentation/
Ddriver_usage.txt10 data using a single medium (physical layer). Media currently in use are
26 The driver consists basically of three layers. The hardware layer, the
27 core layer and the application layer. The core layer consists of the core
33 system architecture. A module of the hardware layer is referred to as an
34 HDM (hardware dependent module). Each module of this layer handles exactly
36 USB, MediaLB, I2C). A module of the application layer is referred to as an
37 AIM (application interfacing module). The modules of this layer give access
49 The hardware layer contains so called hardware dependent modules (HDM). For each
69 The core layer contains the mostcore module only, which processes the driver
76 The application layer contains so called application interfacing modules (AIM).
/drivers/net/ethernet/stmicro/stmmac/
DKconfig48 This selects the IPQ806x SoC glue layer support for the stmmac
68 This selects the Amlogic Meson SoC glue layer support for
80 This selects the Rockchip RK3288 SoC glue layer support for
91 This selects the Altera SOCFPGA SoC glue layer support
103 This selects STi SoC glue layer support for the stmmac
115 This selects STM32 SoC glue layer support for the stmmac
126 This selects Allwinner SoC glue layer support for the
/drivers/media/dvb-core/
Ddvb_frontend.c953 c->layer[i].fec = FEC_AUTO; in dvb_frontend_clear_cache()
954 c->layer[i].modulation = QAM_AUTO; in dvb_frontend_clear_cache()
955 c->layer[i].interleaving = 0; in dvb_frontend_clear_cache()
956 c->layer[i].segment_count = 0; in dvb_frontend_clear_cache()
1377 tvp->u.data = c->layer[0].fec; in dtv_property_process_get()
1380 tvp->u.data = c->layer[0].modulation; in dtv_property_process_get()
1383 tvp->u.data = c->layer[0].segment_count; in dtv_property_process_get()
1386 tvp->u.data = c->layer[0].interleaving; in dtv_property_process_get()
1389 tvp->u.data = c->layer[1].fec; in dtv_property_process_get()
1392 tvp->u.data = c->layer[1].modulation; in dtv_property_process_get()
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Ddvb_filter.c313 ai->layer = (headr[1] & 0x06) >> 1;
316 printk("Audiostream: Layer: %d", 4-ai->layer);
319 ai->bit_rate = bitrates[(3-ai->layer)][(headr[2] >> 4 )]*1000;
370 ai->layer = 0; // 0 for AC3 in dvb_filter_get_ac3info()
/drivers/staging/lustre/
DTODO5 * Clean up libcfs layer. Ideally we can remove include/linux/libcfs entirely.
6 * Clean up CLIO layer. Lustre client readahead/writeback control needs to better
/drivers/s390/net/
DKconfig77 prompt "qeth layer 2 device support"
80 Select this option to be able to run qeth devices in layer 2 mode.
86 prompt "qeth layer 3 device support"
89 Select this option to be able to run qeth devices in layer 3 mode.
/drivers/infiniband/sw/rxe/
DKconfig18 space verbs API, libibverbs. The other layer interfaces
19 with the Linux network stack at layer 3.
/drivers/ata/
DKconfig585 PATA controllers via the new ATA layer.
594 PATA controllers via the new ATA layer.
603 controllers via the new ATA layer.
612 PATA controllers via the new ATA layer
646 controllers via the new ATA layer.
655 PATA controllers via the new ATA layer, including RAID
665 ATA layer.
766 PATA controllers via the new ATA layer
775 controllers via the new ATA layer. For the RDC 1010, you need to
803 HT1000 PATA controllers, via the new ATA layer.
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/drivers/edac/
Dedac_mc.c272 struct edac_mc_layer *layer; in edac_mc_alloc() local
306 layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); in edac_mc_alloc()
332 layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); in edac_mc_alloc()
344 mci->layers = layer; in edac_mc_alloc()
345 memcpy(mci->layers, layers, sizeof(*layer) * n_layers); in edac_mc_alloc()
391 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); in edac_mc_alloc()
/drivers/staging/lustre/lnet/
DKconfig5 The Lustre network layer, also known as LNet, is a networking abstaction
8 case of Lustre routers only the LNet layer is required. Lately other

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