1/* 2 * Copyright (c) 2016 BayLibre, Inc. 3 * 4 * Licensed under GPLv2. 5 */ 6/dts-v1/; 7#include "da850.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "DA850/AM1808/OMAP-L138 LCDK"; 12 compatible = "ti,da850-lcdk", "ti,da850"; 13 14 aliases { 15 serial2 = &serial2; 16 }; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 memory { 23 device_type = "memory"; 24 reg = <0xc0000000 0x08000000>; 25 }; 26 27 sound { 28 compatible = "simple-audio-card"; 29 simple-audio-card,name = "DA850/OMAP-L138 LCDK"; 30 simple-audio-card,widgets = 31 "Line", "Line In", 32 "Line", "Line Out"; 33 simple-audio-card,routing = 34 "LINE1L", "Line In", 35 "LINE1R", "Line In", 36 "Line Out", "LLOUT", 37 "Line Out", "RLOUT"; 38 simple-audio-card,format = "dsp_b"; 39 simple-audio-card,bitclock-master = <&link0_codec>; 40 simple-audio-card,frame-master = <&link0_codec>; 41 simple-audio-card,bitclock-inversion; 42 43 simple-audio-card,cpu { 44 sound-dai = <&mcasp0>; 45 system-clock-frequency = <24576000>; 46 }; 47 48 link0_codec: simple-audio-card,codec { 49 sound-dai = <&tlv320aic3106>; 50 system-clock-frequency = <24576000>; 51 }; 52 }; 53}; 54 55&pmx_core { 56 status = "okay"; 57 58 mcasp0_pins: pinmux_mcasp0_pins { 59 pinctrl-single,bits = < 60 /* AHCLKX AFSX ACLKX */ 61 0x00 0x00101010 0x00f0f0f0 62 /* ARX13 ARX14 */ 63 0x04 0x00000110 0x00000ff0 64 >; 65 }; 66 67 nand_pins: nand_pins { 68 pinctrl-single,bits = < 69 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ 70 0x1c 0x10110010 0xf0ff00f0 71 /* 72 * EMA_D[0], EMA_D[1], EMA_D[2], 73 * EMA_D[3], EMA_D[4], EMA_D[5], 74 * EMA_D[6], EMA_D[7] 75 */ 76 0x24 0x11111111 0xffffffff 77 /* 78 * EMA_D[8], EMA_D[9], EMA_D[10], 79 * EMA_D[11], EMA_D[12], EMA_D[13], 80 * EMA_D[14], EMA_D[15] 81 */ 82 0x20 0x11111111 0xffffffff 83 /* EMA_A[1], EMA_A[2] */ 84 0x30 0x01100000 0x0ff00000 85 >; 86 }; 87}; 88 89&serial2 { 90 pinctrl-names = "default"; 91 pinctrl-0 = <&serial2_rxtx_pins>; 92 status = "okay"; 93}; 94 95&wdt { 96 status = "okay"; 97}; 98 99&rtc0 { 100 status = "okay"; 101}; 102 103&gpio { 104 status = "okay"; 105}; 106 107&mdio { 108 pinctrl-names = "default"; 109 pinctrl-0 = <&mdio_pins>; 110 bus_freq = <2200000>; 111 status = "okay"; 112}; 113 114ð0 { 115 pinctrl-names = "default"; 116 pinctrl-0 = <&mii_pins>; 117 status = "okay"; 118}; 119 120&mmc0 { 121 max-frequency = <50000000>; 122 bus-width = <4>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&mmc0_pins>; 125 cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; 126 status = "okay"; 127}; 128 129&i2c0 { 130 pinctrl-names = "default"; 131 pinctrl-0 = <&i2c0_pins>; 132 clock-frequency = <100000>; 133 status = "okay"; 134 135 tlv320aic3106: tlv320aic3106@18 { 136 #sound-dai-cells = <0>; 137 compatible = "ti,tlv320aic3106"; 138 reg = <0x18>; 139 status = "okay"; 140 }; 141}; 142 143&mcasp0 { 144 #sound-dai-cells = <0>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&mcasp0_pins>; 147 status = "okay"; 148 149 op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ 150 tdm-slots = <2>; 151 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 152 0 0 0 0 153 0 0 0 0 154 0 0 0 0 155 0 1 2 0 156 >; 157 tx-num-evt = <32>; 158 rx-num-evt = <32>; 159}; 160 161&aemif { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&nand_pins>; 164 status = "okay"; 165 cs3 { 166 #address-cells = <2>; 167 #size-cells = <1>; 168 clock-ranges; 169 ranges; 170 171 ti,cs-chipselect = <3>; 172 173 nand@2000000,0 { 174 compatible = "ti,davinci-nand"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 reg = <0 0x02000000 0x02000000 178 1 0x00000000 0x00008000>; 179 180 ti,davinci-chipselect = <1>; 181 ti,davinci-mask-ale = <0>; 182 ti,davinci-mask-cle = <0>; 183 ti,davinci-mask-chipsel = <0>; 184 185 ti,davinci-nand-buswidth = <16>; 186 ti,davinci-ecc-mode = "hw"; 187 ti,davinci-ecc-bits = <4>; 188 ti,davinci-nand-use-bbt; 189 190 /* 191 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: 192 * "To boot from NAND Flash, the AIS should be written 193 * to NAND block 1 (NAND block 0 is not used by default)". 194 * The same doc mentions that for ROM "Silicon Revision 2.1", 195 * "Updated NAND boot mode to offer boot from block 0 or block 1". 196 * However the limitaion is left here by default for compatibility 197 * with older silicon and because it needs new boot pin settings 198 * not possible in stock LCDK. 199 */ 200 partitions { 201 compatible = "fixed-partitions"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 205 partition@0 { 206 label = "u-boot env"; 207 reg = <0 0x020000>; 208 }; 209 partition@0x020000 { 210 /* The LCDK defaults to booting from this partition */ 211 label = "u-boot"; 212 reg = <0x020000 0x080000>; 213 }; 214 partition@0x0a0000 { 215 label = "free space"; 216 reg = <0x0a0000 0>; 217 }; 218 }; 219 }; 220 }; 221}; 222