1/* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * Copyright 2016 Toradex AG 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/clock/imx7d-clock.h> 45#include <dt-bindings/gpio/gpio.h> 46#include <dt-bindings/input/input.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include "imx7d-pinfunc.h" 49#include "skeleton.dtsi" 50 51/ { 52 aliases { 53 gpio0 = &gpio1; 54 gpio1 = &gpio2; 55 gpio2 = &gpio3; 56 gpio3 = &gpio4; 57 gpio4 = &gpio5; 58 gpio5 = &gpio6; 59 gpio6 = &gpio7; 60 i2c0 = &i2c1; 61 i2c1 = &i2c2; 62 i2c2 = &i2c3; 63 i2c3 = &i2c4; 64 mmc0 = &usdhc1; 65 mmc1 = &usdhc2; 66 mmc2 = &usdhc3; 67 serial0 = &uart1; 68 serial1 = &uart2; 69 serial2 = &uart3; 70 serial3 = &uart4; 71 serial4 = &uart5; 72 serial5 = &uart6; 73 serial6 = &uart7; 74 spi0 = &ecspi1; 75 spi1 = &ecspi2; 76 spi2 = &ecspi3; 77 spi3 = &ecspi4; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 cpu0: cpu@0 { 85 compatible = "arm,cortex-a7"; 86 device_type = "cpu"; 87 reg = <0>; 88 clock-frequency = <792000000>; 89 clock-latency = <61036>; /* two CLK32 periods */ 90 clocks = <&clks IMX7D_CLK_ARM>; 91 }; 92 }; 93 94 ckil: clock-cki { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <32768>; 98 clock-output-names = "ckil"; 99 }; 100 101 osc: clock-osc { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <24000000>; 105 clock-output-names = "osc"; 106 }; 107 108 soc { 109 #address-cells = <1>; 110 #size-cells = <1>; 111 compatible = "simple-bus"; 112 interrupt-parent = <&intc>; 113 ranges; 114 115 funnel@30041000 { 116 compatible = "arm,coresight-funnel", "arm,primecell"; 117 reg = <0x30041000 0x1000>; 118 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 119 clock-names = "apb_pclk"; 120 121 ca_funnel_ports: ports { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 /* funnel input ports */ 126 port@0 { 127 reg = <0>; 128 ca_funnel_in_port0: endpoint { 129 slave-mode; 130 remote-endpoint = <&etm0_out_port>; 131 }; 132 }; 133 134 /* funnel output port */ 135 port@2 { 136 reg = <0>; 137 ca_funnel_out_port0: endpoint { 138 remote-endpoint = <&hugo_funnel_in_port0>; 139 }; 140 }; 141 142 /* the other input ports are not connect to anything */ 143 }; 144 }; 145 146 etm@3007c000 { 147 compatible = "arm,coresight-etm3x", "arm,primecell"; 148 reg = <0x3007c000 0x1000>; 149 cpu = <&cpu0>; 150 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 151 clock-names = "apb_pclk"; 152 153 port { 154 etm0_out_port: endpoint { 155 remote-endpoint = <&ca_funnel_in_port0>; 156 }; 157 }; 158 }; 159 160 funnel@30083000 { 161 compatible = "arm,coresight-funnel", "arm,primecell"; 162 reg = <0x30083000 0x1000>; 163 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 164 clock-names = "apb_pclk"; 165 166 ports { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 /* funnel input ports */ 171 port@0 { 172 reg = <0>; 173 hugo_funnel_in_port0: endpoint { 174 slave-mode; 175 remote-endpoint = <&ca_funnel_out_port0>; 176 }; 177 }; 178 179 port@1 { 180 reg = <1>; 181 hugo_funnel_in_port1: endpoint { 182 slave-mode; /* M4 input */ 183 }; 184 }; 185 186 port@2 { 187 reg = <0>; 188 hugo_funnel_out_port0: endpoint { 189 remote-endpoint = <&etf_in_port>; 190 }; 191 }; 192 193 /* the other input ports are not connect to anything */ 194 }; 195 }; 196 197 etf@30084000 { 198 compatible = "arm,coresight-tmc", "arm,primecell"; 199 reg = <0x30084000 0x1000>; 200 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 201 clock-names = "apb_pclk"; 202 203 ports { 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 port@0 { 208 reg = <0>; 209 etf_in_port: endpoint { 210 slave-mode; 211 remote-endpoint = <&hugo_funnel_out_port0>; 212 }; 213 }; 214 215 port@1 { 216 reg = <0>; 217 etf_out_port: endpoint { 218 remote-endpoint = <&replicator_in_port0>; 219 }; 220 }; 221 }; 222 }; 223 224 etr@30086000 { 225 compatible = "arm,coresight-tmc", "arm,primecell"; 226 reg = <0x30086000 0x1000>; 227 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 228 clock-names = "apb_pclk"; 229 230 port { 231 etr_in_port: endpoint { 232 slave-mode; 233 remote-endpoint = <&replicator_out_port1>; 234 }; 235 }; 236 }; 237 238 tpiu@30087000 { 239 compatible = "arm,coresight-tpiu", "arm,primecell"; 240 reg = <0x30087000 0x1000>; 241 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 242 clock-names = "apb_pclk"; 243 244 port { 245 tpiu_in_port: endpoint { 246 slave-mode; 247 remote-endpoint = <&replicator_out_port1>; 248 }; 249 }; 250 }; 251 252 replicator { 253 /* 254 * non-configurable replicators don't show up on the 255 * AMBA bus. As such no need to add "arm,primecell" 256 */ 257 compatible = "arm,coresight-replicator"; 258 259 ports { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 /* replicator output ports */ 264 port@0 { 265 reg = <0>; 266 replicator_out_port0: endpoint { 267 remote-endpoint = <&tpiu_in_port>; 268 }; 269 }; 270 271 port@1 { 272 reg = <1>; 273 replicator_out_port1: endpoint { 274 remote-endpoint = <&etr_in_port>; 275 }; 276 }; 277 278 /* replicator input port */ 279 port@2 { 280 reg = <0>; 281 replicator_in_port0: endpoint { 282 slave-mode; 283 remote-endpoint = <&etf_out_port>; 284 }; 285 }; 286 }; 287 }; 288 289 intc: interrupt-controller@31001000 { 290 compatible = "arm,cortex-a7-gic"; 291 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 reg = <0x31001000 0x1000>, 295 <0x31002000 0x2000>, 296 <0x31004000 0x2000>, 297 <0x31006000 0x2000>; 298 }; 299 300 timer { 301 compatible = "arm,armv7-timer"; 302 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 303 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 304 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 305 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 306 }; 307 308 aips1: aips-bus@30000000 { 309 compatible = "fsl,aips-bus", "simple-bus"; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 reg = <0x30000000 0x400000>; 313 ranges; 314 315 gpio1: gpio@30200000 { 316 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 317 reg = <0x30200000 0x10000>; 318 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 319 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 gpio-ranges = <&iomuxc 0 13 32>; 337 }; 338 339 gpio3: gpio@30220000 { 340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 341 reg = <0x30220000 0x10000>; 342 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 gpio-ranges = <&iomuxc 0 45 29>; 349 }; 350 351 gpio4: gpio@30230000 { 352 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 353 reg = <0x30230000 0x10000>; 354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 356 gpio-controller; 357 #gpio-cells = <2>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 gpio-ranges = <&iomuxc 0 74 24>; 361 }; 362 363 gpio5: gpio@30240000 { 364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 365 reg = <0x30240000 0x10000>; 366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 gpio-ranges = <&iomuxc 0 98 18>; 373 }; 374 375 gpio6: gpio@30250000 { 376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 377 reg = <0x30250000 0x10000>; 378 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 gpio-ranges = <&iomuxc 0 116 23>; 385 }; 386 387 gpio7: gpio@30260000 { 388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 389 reg = <0x30260000 0x10000>; 390 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 392 gpio-controller; 393 #gpio-cells = <2>; 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 gpio-ranges = <&iomuxc 0 139 16>; 397 }; 398 399 wdog1: wdog@30280000 { 400 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 401 reg = <0x30280000 0x10000>; 402 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 404 }; 405 406 wdog2: wdog@30290000 { 407 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 408 reg = <0x30290000 0x10000>; 409 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 411 status = "disabled"; 412 }; 413 414 wdog3: wdog@302a0000 { 415 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 416 reg = <0x302a0000 0x10000>; 417 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 419 status = "disabled"; 420 }; 421 422 wdog4: wdog@302b0000 { 423 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 424 reg = <0x302b0000 0x10000>; 425 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 427 status = "disabled"; 428 }; 429 430 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 431 compatible = "fsl,imx7d-iomuxc-lpsr"; 432 reg = <0x302c0000 0x10000>; 433 fsl,input-sel = <&iomuxc>; 434 }; 435 436 gpt1: gpt@302d0000 { 437 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 438 reg = <0x302d0000 0x10000>; 439 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clks IMX7D_CLK_DUMMY>, 441 <&clks IMX7D_GPT1_ROOT_CLK>; 442 clock-names = "ipg", "per"; 443 }; 444 445 gpt2: gpt@302e0000 { 446 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 447 reg = <0x302e0000 0x10000>; 448 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clks IMX7D_CLK_DUMMY>, 450 <&clks IMX7D_GPT2_ROOT_CLK>; 451 clock-names = "ipg", "per"; 452 status = "disabled"; 453 }; 454 455 gpt3: gpt@302f0000 { 456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 457 reg = <0x302f0000 0x10000>; 458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clks IMX7D_CLK_DUMMY>, 460 <&clks IMX7D_GPT3_ROOT_CLK>; 461 clock-names = "ipg", "per"; 462 status = "disabled"; 463 }; 464 465 gpt4: gpt@30300000 { 466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 467 reg = <0x30300000 0x10000>; 468 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clks IMX7D_CLK_DUMMY>, 470 <&clks IMX7D_GPT4_ROOT_CLK>; 471 clock-names = "ipg", "per"; 472 status = "disabled"; 473 }; 474 475 iomuxc: iomuxc@30330000 { 476 compatible = "fsl,imx7d-iomuxc"; 477 reg = <0x30330000 0x10000>; 478 }; 479 480 gpr: iomuxc-gpr@30340000 { 481 compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; 482 reg = <0x30340000 0x10000>; 483 }; 484 485 ocotp: ocotp-ctrl@30350000 { 486 compatible = "syscon"; 487 reg = <0x30350000 0x10000>; 488 clocks = <&clks IMX7D_CLK_DUMMY>; 489 status = "disabled"; 490 }; 491 492 anatop: anatop@30360000 { 493 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 494 "syscon", "simple-bus"; 495 reg = <0x30360000 0x10000>; 496 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 498 499 reg_1p0d: regulator-vdd1p0d { 500 compatible = "fsl,anatop-regulator"; 501 regulator-name = "vdd1p0d"; 502 regulator-min-microvolt = <800000>; 503 regulator-max-microvolt = <1200000>; 504 anatop-reg-offset = <0x210>; 505 anatop-vol-bit-shift = <8>; 506 anatop-vol-bit-width = <5>; 507 anatop-min-bit-val = <8>; 508 anatop-min-voltage = <800000>; 509 anatop-max-voltage = <1200000>; 510 anatop-enable-bit = <31>; 511 }; 512 }; 513 514 snvs: snvs@30370000 { 515 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 516 reg = <0x30370000 0x10000>; 517 518 snvs_rtc: snvs-rtc-lp { 519 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 520 regmap = <&snvs>; 521 offset = <0x34>; 522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 524 }; 525 526 snvs_poweroff: snvs-poweroff { 527 compatible = "syscon-poweroff"; 528 regmap = <&snvs>; 529 offset = <0x38>; 530 mask = <0x60>; 531 }; 532 533 snvs_pwrkey: snvs-powerkey { 534 compatible = "fsl,sec-v4.0-pwrkey"; 535 regmap = <&snvs>; 536 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 537 linux,keycode = <KEY_POWER>; 538 wakeup-source; 539 }; 540 }; 541 542 clks: ccm@30380000 { 543 compatible = "fsl,imx7d-ccm"; 544 reg = <0x30380000 0x10000>; 545 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 547 #clock-cells = <1>; 548 clocks = <&ckil>, <&osc>; 549 clock-names = "ckil", "osc"; 550 }; 551 552 src: src@30390000 { 553 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; 554 reg = <0x30390000 0x10000>; 555 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 556 #reset-cells = <1>; 557 }; 558 }; 559 560 aips2: aips-bus@30400000 { 561 compatible = "fsl,aips-bus", "simple-bus"; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 reg = <0x30400000 0x400000>; 565 ranges; 566 567 adc1: adc@30610000 { 568 compatible = "fsl,imx7d-adc"; 569 reg = <0x30610000 0x10000>; 570 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 572 clock-names = "adc"; 573 status = "disabled"; 574 }; 575 576 adc2: adc@30620000 { 577 compatible = "fsl,imx7d-adc"; 578 reg = <0x30620000 0x10000>; 579 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 581 clock-names = "adc"; 582 status = "disabled"; 583 }; 584 585 ecspi4: ecspi@30630000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 589 reg = <0x30630000 0x10000>; 590 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 592 <&clks IMX7D_ECSPI4_ROOT_CLK>; 593 clock-names = "ipg", "per"; 594 status = "disabled"; 595 }; 596 597 pwm1: pwm@30660000 { 598 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 599 reg = <0x30660000 0x10000>; 600 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 602 <&clks IMX7D_PWM1_ROOT_CLK>; 603 clock-names = "ipg", "per"; 604 #pwm-cells = <2>; 605 status = "disabled"; 606 }; 607 608 pwm2: pwm@30670000 { 609 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 610 reg = <0x30670000 0x10000>; 611 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 613 <&clks IMX7D_PWM2_ROOT_CLK>; 614 clock-names = "ipg", "per"; 615 #pwm-cells = <2>; 616 status = "disabled"; 617 }; 618 619 pwm3: pwm@30680000 { 620 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 621 reg = <0x30680000 0x10000>; 622 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 624 <&clks IMX7D_PWM3_ROOT_CLK>; 625 clock-names = "ipg", "per"; 626 #pwm-cells = <2>; 627 status = "disabled"; 628 }; 629 630 pwm4: pwm@30690000 { 631 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 632 reg = <0x30690000 0x10000>; 633 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 635 <&clks IMX7D_PWM4_ROOT_CLK>; 636 clock-names = "ipg", "per"; 637 #pwm-cells = <2>; 638 status = "disabled"; 639 }; 640 641 lcdif: lcdif@30730000 { 642 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 643 reg = <0x30730000 0x10000>; 644 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 646 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 647 clock-names = "pix", "axi"; 648 status = "disabled"; 649 }; 650 }; 651 652 aips3: aips-bus@30800000 { 653 compatible = "fsl,aips-bus", "simple-bus"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 reg = <0x30800000 0x400000>; 657 ranges; 658 659 ecspi1: ecspi@30820000 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 663 reg = <0x30820000 0x10000>; 664 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 666 <&clks IMX7D_ECSPI1_ROOT_CLK>; 667 clock-names = "ipg", "per"; 668 status = "disabled"; 669 }; 670 671 ecspi2: ecspi@30830000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 675 reg = <0x30830000 0x10000>; 676 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 678 <&clks IMX7D_ECSPI2_ROOT_CLK>; 679 clock-names = "ipg", "per"; 680 status = "disabled"; 681 }; 682 683 ecspi3: ecspi@30840000 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 687 reg = <0x30840000 0x10000>; 688 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 690 <&clks IMX7D_ECSPI3_ROOT_CLK>; 691 clock-names = "ipg", "per"; 692 status = "disabled"; 693 }; 694 695 uart1: serial@30860000 { 696 compatible = "fsl,imx7d-uart", 697 "fsl,imx6q-uart"; 698 reg = <0x30860000 0x10000>; 699 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 701 <&clks IMX7D_UART1_ROOT_CLK>; 702 clock-names = "ipg", "per"; 703 status = "disabled"; 704 }; 705 706 uart2: serial@30890000 { 707 compatible = "fsl,imx7d-uart", 708 "fsl,imx6q-uart"; 709 reg = <0x30890000 0x10000>; 710 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 712 <&clks IMX7D_UART2_ROOT_CLK>; 713 clock-names = "ipg", "per"; 714 status = "disabled"; 715 }; 716 717 uart3: serial@30880000 { 718 compatible = "fsl,imx7d-uart", 719 "fsl,imx6q-uart"; 720 reg = <0x30880000 0x10000>; 721 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 723 <&clks IMX7D_UART3_ROOT_CLK>; 724 clock-names = "ipg", "per"; 725 status = "disabled"; 726 }; 727 728 sai1: sai@308a0000 { 729 #sound-dai-cells = <0>; 730 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 731 reg = <0x308a0000 0x10000>; 732 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 734 <&clks IMX7D_SAI1_ROOT_CLK>, 735 <&clks IMX7D_CLK_DUMMY>, 736 <&clks IMX7D_CLK_DUMMY>; 737 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 738 dma-names = "rx", "tx"; 739 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 740 status = "disabled"; 741 }; 742 743 sai2: sai@308b0000 { 744 #sound-dai-cells = <0>; 745 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 746 reg = <0x308b0000 0x10000>; 747 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 749 <&clks IMX7D_SAI2_ROOT_CLK>, 750 <&clks IMX7D_CLK_DUMMY>, 751 <&clks IMX7D_CLK_DUMMY>; 752 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 753 dma-names = "rx", "tx"; 754 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 755 status = "disabled"; 756 }; 757 758 sai3: sai@308c0000 { 759 #sound-dai-cells = <0>; 760 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 761 reg = <0x308c0000 0x10000>; 762 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 764 <&clks IMX7D_SAI3_ROOT_CLK>, 765 <&clks IMX7D_CLK_DUMMY>, 766 <&clks IMX7D_CLK_DUMMY>; 767 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 768 dma-names = "rx", "tx"; 769 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 770 status = "disabled"; 771 }; 772 773 flexcan1: can@30a00000 { 774 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 775 reg = <0x30a00000 0x10000>; 776 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&clks IMX7D_CLK_DUMMY>, 778 <&clks IMX7D_CAN1_ROOT_CLK>; 779 clock-names = "ipg", "per"; 780 status = "disabled"; 781 }; 782 783 flexcan2: can@30a10000 { 784 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 785 reg = <0x30a10000 0x10000>; 786 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&clks IMX7D_CLK_DUMMY>, 788 <&clks IMX7D_CAN2_ROOT_CLK>; 789 clock-names = "ipg", "per"; 790 status = "disabled"; 791 }; 792 793 i2c1: i2c@30a20000 { 794 #address-cells = <1>; 795 #size-cells = <0>; 796 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 797 reg = <0x30a20000 0x10000>; 798 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 800 status = "disabled"; 801 }; 802 803 i2c2: i2c@30a30000 { 804 #address-cells = <1>; 805 #size-cells = <0>; 806 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 807 reg = <0x30a30000 0x10000>; 808 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 810 status = "disabled"; 811 }; 812 813 i2c3: i2c@30a40000 { 814 #address-cells = <1>; 815 #size-cells = <0>; 816 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 817 reg = <0x30a40000 0x10000>; 818 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 820 status = "disabled"; 821 }; 822 823 i2c4: i2c@30a50000 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 827 reg = <0x30a50000 0x10000>; 828 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 830 status = "disabled"; 831 }; 832 833 uart4: serial@30a60000 { 834 compatible = "fsl,imx7d-uart", 835 "fsl,imx6q-uart"; 836 reg = <0x30a60000 0x10000>; 837 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 839 <&clks IMX7D_UART4_ROOT_CLK>; 840 clock-names = "ipg", "per"; 841 status = "disabled"; 842 }; 843 844 uart5: serial@30a70000 { 845 compatible = "fsl,imx7d-uart", 846 "fsl,imx6q-uart"; 847 reg = <0x30a70000 0x10000>; 848 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 850 <&clks IMX7D_UART5_ROOT_CLK>; 851 clock-names = "ipg", "per"; 852 status = "disabled"; 853 }; 854 855 uart6: serial@30a80000 { 856 compatible = "fsl,imx7d-uart", 857 "fsl,imx6q-uart"; 858 reg = <0x30a80000 0x10000>; 859 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 861 <&clks IMX7D_UART6_ROOT_CLK>; 862 clock-names = "ipg", "per"; 863 status = "disabled"; 864 }; 865 866 uart7: serial@30a90000 { 867 compatible = "fsl,imx7d-uart", 868 "fsl,imx6q-uart"; 869 reg = <0x30a90000 0x10000>; 870 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 872 <&clks IMX7D_UART7_ROOT_CLK>; 873 clock-names = "ipg", "per"; 874 status = "disabled"; 875 }; 876 877 usbotg1: usb@30b10000 { 878 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 879 reg = <0x30b10000 0x200>; 880 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&clks IMX7D_USB_CTRL_CLK>; 882 fsl,usbphy = <&usbphynop1>; 883 fsl,usbmisc = <&usbmisc1 0>; 884 phy-clkgate-delay-us = <400>; 885 status = "disabled"; 886 }; 887 888 usbh: usb@30b30000 { 889 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 890 reg = <0x30b30000 0x200>; 891 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clks IMX7D_USB_CTRL_CLK>; 893 fsl,usbphy = <&usbphynop3>; 894 fsl,usbmisc = <&usbmisc3 0>; 895 phy_type = "hsic"; 896 dr_mode = "host"; 897 phy-clkgate-delay-us = <400>; 898 status = "disabled"; 899 }; 900 901 usbmisc1: usbmisc@30b10200 { 902 #index-cells = <1>; 903 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 904 reg = <0x30b10200 0x200>; 905 }; 906 907 usbmisc3: usbmisc@30b30200 { 908 #index-cells = <1>; 909 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 910 reg = <0x30b30200 0x200>; 911 }; 912 913 usbphynop1: usbphynop1 { 914 compatible = "usb-nop-xceiv"; 915 clocks = <&clks IMX7D_USB_PHY1_CLK>; 916 clock-names = "main_clk"; 917 }; 918 919 usbphynop3: usbphynop3 { 920 compatible = "usb-nop-xceiv"; 921 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 922 clock-names = "main_clk"; 923 }; 924 925 usdhc1: usdhc@30b40000 { 926 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 927 reg = <0x30b40000 0x10000>; 928 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clks IMX7D_CLK_DUMMY>, 930 <&clks IMX7D_CLK_DUMMY>, 931 <&clks IMX7D_USDHC1_ROOT_CLK>; 932 clock-names = "ipg", "ahb", "per"; 933 bus-width = <4>; 934 status = "disabled"; 935 }; 936 937 usdhc2: usdhc@30b50000 { 938 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 939 reg = <0x30b50000 0x10000>; 940 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clks IMX7D_CLK_DUMMY>, 942 <&clks IMX7D_CLK_DUMMY>, 943 <&clks IMX7D_USDHC2_ROOT_CLK>; 944 clock-names = "ipg", "ahb", "per"; 945 bus-width = <4>; 946 status = "disabled"; 947 }; 948 949 usdhc3: usdhc@30b60000 { 950 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 951 reg = <0x30b60000 0x10000>; 952 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&clks IMX7D_CLK_DUMMY>, 954 <&clks IMX7D_CLK_DUMMY>, 955 <&clks IMX7D_USDHC3_ROOT_CLK>; 956 clock-names = "ipg", "ahb", "per"; 957 bus-width = <4>; 958 status = "disabled"; 959 }; 960 961 sdma: sdma@30bd0000 { 962 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 963 reg = <0x30bd0000 0x10000>; 964 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clks IMX7D_SDMA_CORE_CLK>, 966 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 967 clock-names = "ipg", "ahb"; 968 #dma-cells = <3>; 969 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 970 }; 971 972 fec1: ethernet@30be0000 { 973 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 974 reg = <0x30be0000 0x10000>; 975 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, 979 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 980 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 981 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 982 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 983 clock-names = "ipg", "ahb", "ptp", 984 "enet_clk_ref", "enet_out"; 985 fsl,num-tx-queues=<3>; 986 fsl,num-rx-queues=<3>; 987 status = "disabled"; 988 }; 989 }; 990 }; 991}; 992