1/* 2 * Copyright 2014 Texas Instruments, Inc. 3 * 4 * Keystone 2 Lamarr SoC specific device tree 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 compatible = "ti,k2l", "ti,keystone"; 13 model = "Texas Instruments Keystone 2 Lamarr SoC"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 interrupt-parent = <&gic>; 20 21 cpu@0 { 22 compatible = "arm,cortex-a15"; 23 device_type = "cpu"; 24 reg = <0>; 25 }; 26 27 cpu@1 { 28 compatible = "arm,cortex-a15"; 29 device_type = "cpu"; 30 reg = <1>; 31 }; 32 }; 33 34 soc { 35 /include/ "keystone-k2l-clocks.dtsi" 36 37 uart2: serial@02348400 { 38 compatible = "ns16550a"; 39 current-speed = <115200>; 40 reg-shift = <2>; 41 reg-io-width = <4>; 42 reg = <0x02348400 0x100>; 43 clocks = <&clkuart2>; 44 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; 45 }; 46 47 uart3: serial@02348800 { 48 compatible = "ns16550a"; 49 current-speed = <115200>; 50 reg-shift = <2>; 51 reg-io-width = <4>; 52 reg = <0x02348800 0x100>; 53 clocks = <&clkuart3>; 54 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; 55 }; 56 57 k2l_pmx: pinmux@02620690 { 58 compatible = "pinctrl-single"; 59 reg = <0x02620690 0xc>; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 pinctrl-single,bit-per-mux; 63 pinctrl-single,register-width = <32>; 64 pinctrl-single,function-mask = <0x1>; 65 status = "disabled"; 66 67 uart3_emifa_pins: pinmux_uart3_emifa_pins { 68 pinctrl-single,bits = < 69 /* UART3_EMIFA_SEL */ 70 0x0 0x0 0xc0 71 >; 72 }; 73 74 uart2_emifa_pins: pinmux_uart2_emifa_pins { 75 pinctrl-single,bits = < 76 /* UART2_EMIFA_SEL */ 77 0x0 0x0 0x30 78 >; 79 }; 80 81 uart01_spi2_pins: pinmux_uart01_spi2_pins { 82 pinctrl-single,bits = < 83 /* UART01_SPI2_SEL */ 84 0x0 0x0 0x4 85 >; 86 }; 87 88 dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ 89 pinctrl-single,bits = < 90 /* DFESYNC_RP1_SEL */ 91 0x0 0x0 0x2 92 >; 93 }; 94 95 avsif_pins: pinmux_avsif_pins { 96 pinctrl-single,bits = < 97 /* AVSIF_SEL */ 98 0x0 0x0 0x1 99 >; 100 }; 101 102 gpio_emu_pins: pinmux_gpio_emu_pins { 103 pinctrl-single,bits = < 104 /* 105 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 106 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 107 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 108 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 109 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 110 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 111 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 112 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 113 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 114 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 115 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 116 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 117 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 118 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 119 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 120 */ 121 0x4 0x0000 0xFFFE0000 122 >; 123 }; 124 125 gpio_timio_pins: pinmux_gpio_timio_pins { 126 pinctrl-single,bits = < 127 /* 128 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 129 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 130 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 131 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 132 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 133 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 134 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 135 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 136 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 137 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 138 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 139 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 140 */ 141 0x4 0x0 0xFFF0 142 >; 143 }; 144 145 gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { 146 pinctrl-single,bits = < 147 /* 148 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 149 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 150 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 151 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 152 */ 153 0x4 0x0 0xF 154 >; 155 }; 156 157 gpio_dfeio_pins: pinmux_gpio_dfeio_pins { 158 pinctrl-single,bits = < 159 /* 160 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 161 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 162 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 163 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 164 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 165 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 166 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 167 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 168 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 169 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 170 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 171 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 172 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 173 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 174 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 175 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 176 */ 177 0x8 0x0 0xFFFF0000 178 >; 179 }; 180 181 gpio_emifa_pins: pinmux_gpio_emifa_pins { 182 pinctrl-single,bits = < 183 /* 184 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 185 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 186 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 187 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 188 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 189 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 190 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 191 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 192 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 193 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 194 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 195 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 196 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 197 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 198 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 199 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 200 */ 201 0x8 0x0 0xFFFF 202 >; 203 }; 204 }; 205 206 dspgpio0: keystone_dsp_gpio@02620240 { 207 compatible = "ti,keystone-dsp-gpio"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 gpio,syscon-dev = <&devctrl 0x240>; 211 }; 212 213 dspgpio1: keystone_dsp_gpio@2620244 { 214 compatible = "ti,keystone-dsp-gpio"; 215 gpio-controller; 216 #gpio-cells = <2>; 217 gpio,syscon-dev = <&devctrl 0x244>; 218 }; 219 220 dspgpio2: keystone_dsp_gpio@2620248 { 221 compatible = "ti,keystone-dsp-gpio"; 222 gpio-controller; 223 #gpio-cells = <2>; 224 gpio,syscon-dev = <&devctrl 0x248>; 225 }; 226 227 dspgpio3: keystone_dsp_gpio@262024c { 228 compatible = "ti,keystone-dsp-gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 gpio,syscon-dev = <&devctrl 0x24c>; 232 }; 233 234 mdio: mdio@26200f00 { 235 compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x26200f00 0x100>; 239 status = "disabled"; 240 clocks = <&clkcpgmac>; 241 clock-names = "fck"; 242 bus_freq = <2500000>; 243 }; 244 /include/ "keystone-k2l-netcp.dtsi" 245 }; 246}; 247 248&spi0 { 249 ti,davinci-spi-num-cs = <5>; 250}; 251 252&spi1 { 253 ti,davinci-spi-num-cs = <3>; 254}; 255 256&spi2 { 257 ti,davinci-spi-num-cs = <5>; 258 /* Pin muxed. Enabled and configured by Bootloader */ 259 status = "disabled"; 260}; 261