1/* 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC 4 * 5 * Copyright (C) 2013 Atmel, 6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 7 * 8 * Licensed under GPLv2 or later. 9 */ 10 11#include "skeleton.dtsi" 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/clock/at91.h> 17 18/ { 19 model = "Atmel SAMA5D3 family SoC"; 20 compatible = "atmel,sama5d3", "atmel,sama5"; 21 interrupt-parent = <&aic>; 22 23 aliases { 24 serial0 = &dbgu; 25 serial1 = &usart0; 26 serial2 = &usart1; 27 serial3 = &usart2; 28 serial4 = &usart3; 29 serial5 = &uart0; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 tcb0 = &tcb0; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 ssc0 = &ssc0; 40 ssc1 = &ssc1; 41 pwm0 = &pwm0; 42 }; 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a5"; 49 reg = <0x0>; 50 }; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a5-pmu"; 55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; 56 }; 57 58 memory { 59 reg = <0x20000000 0x8000000>; 60 }; 61 62 clocks { 63 slow_xtal: slow_xtal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 main_xtal: main_xtal { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <0>; 73 }; 74 75 adc_op_clk: adc_op_clk{ 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <1000000>; 79 }; 80 }; 81 82 sram: sram@00300000 { 83 compatible = "mmio-sram"; 84 reg = <0x00300000 0x20000>; 85 }; 86 87 ahb { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 93 apb { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 mmc0: mmc@f0000000 { 100 compatible = "atmel,hsmci"; 101 reg = <0xf0000000 0x600>; 102 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 103 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; 104 dma-names = "rxtx"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; 107 status = "disabled"; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 clocks = <&mci0_clk>; 111 clock-names = "mci_clk"; 112 }; 113 114 spi0: spi@f0004000 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 compatible = "atmel,at91rm9200-spi"; 118 reg = <0xf0004000 0x100>; 119 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 120 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, 121 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; 122 dma-names = "tx", "rx"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_spi0>; 125 clocks = <&spi0_clk>; 126 clock-names = "spi_clk"; 127 status = "disabled"; 128 }; 129 130 ssc0: ssc@f0008000 { 131 compatible = "atmel,at91sam9g45-ssc"; 132 reg = <0xf0008000 0x4000>; 133 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, 135 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; 136 dma-names = "tx", "rx"; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 139 clocks = <&ssc0_clk>; 140 clock-names = "pclk"; 141 status = "disabled"; 142 }; 143 144 tcb0: timer@f0010000 { 145 compatible = "atmel,at91sam9x5-tcb"; 146 reg = <0xf0010000 0x100>; 147 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 148 clocks = <&tcb0_clk>, <&clk32k>; 149 clock-names = "t0_clk", "slow_clk"; 150 }; 151 152 i2c0: i2c@f0014000 { 153 compatible = "atmel,at91sam9x5-i2c"; 154 reg = <0xf0014000 0x4000>; 155 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; 156 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, 157 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; 158 dma-names = "tx", "rx"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c0>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&twi0_clk>; 164 status = "disabled"; 165 }; 166 167 i2c1: i2c@f0018000 { 168 compatible = "atmel,at91sam9x5-i2c"; 169 reg = <0xf0018000 0x4000>; 170 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; 171 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, 172 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; 173 dma-names = "tx", "rx"; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_i2c1>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 clocks = <&twi1_clk>; 179 status = "disabled"; 180 }; 181 182 usart0: serial@f001c000 { 183 compatible = "atmel,at91sam9260-usart"; 184 reg = <0xf001c000 0x100>; 185 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 186 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, 187 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 188 dma-names = "tx", "rx"; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_usart0>; 191 clocks = <&usart0_clk>; 192 clock-names = "usart"; 193 status = "disabled"; 194 }; 195 196 usart1: serial@f0020000 { 197 compatible = "atmel,at91sam9260-usart"; 198 reg = <0xf0020000 0x100>; 199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 200 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, 201 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 202 dma-names = "tx", "rx"; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_usart1>; 205 clocks = <&usart1_clk>; 206 clock-names = "usart"; 207 status = "disabled"; 208 }; 209 210 uart0: serial@f0024000 { 211 compatible = "atmel,at91sam9260-usart"; 212 reg = <0xf0024000 0x100>; 213 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_uart0>; 216 clocks = <&uart0_clk>; 217 clock-names = "usart"; 218 status = "disabled"; 219 }; 220 221 pwm0: pwm@f002c000 { 222 compatible = "atmel,sama5d3-pwm"; 223 reg = <0xf002c000 0x300>; 224 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; 225 #pwm-cells = <3>; 226 clocks = <&pwm_clk>; 227 status = "disabled"; 228 }; 229 230 isi: isi@f0034000 { 231 compatible = "atmel,at91sam9g45-isi"; 232 reg = <0xf0034000 0x4000>; 233 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_isi_data_0_7>; 236 clocks = <&isi_clk>; 237 clock-names = "isi_clk"; 238 status = "disabled"; 239 port { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 }; 243 }; 244 245 sfr: sfr@f0038000 { 246 compatible = "atmel,sama5d3-sfr", "syscon"; 247 reg = <0xf0038000 0x60>; 248 }; 249 250 mmc1: mmc@f8000000 { 251 compatible = "atmel,hsmci"; 252 reg = <0xf8000000 0x600>; 253 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; 254 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; 255 dma-names = "rxtx"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 258 status = "disabled"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 clocks = <&mci1_clk>; 262 clock-names = "mci_clk"; 263 }; 264 265 spi1: spi@f8008000 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "atmel,at91rm9200-spi"; 269 reg = <0xf8008000 0x100>; 270 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 271 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, 272 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; 273 dma-names = "tx", "rx"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_spi1>; 276 clocks = <&spi1_clk>; 277 clock-names = "spi_clk"; 278 status = "disabled"; 279 }; 280 281 ssc1: ssc@f800c000 { 282 compatible = "atmel,at91sam9g45-ssc"; 283 reg = <0xf800c000 0x4000>; 284 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 285 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, 286 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; 287 dma-names = "tx", "rx"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 290 clocks = <&ssc1_clk>; 291 clock-names = "pclk"; 292 status = "disabled"; 293 }; 294 295 adc0: adc@f8018000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "atmel,at91sam9x5-adc"; 299 reg = <0xf8018000 0x100>; 300 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 301 pinctrl-names = "default"; 302 pinctrl-0 = < 303 &pinctrl_adc0_adtrg 304 &pinctrl_adc0_ad0 305 &pinctrl_adc0_ad1 306 &pinctrl_adc0_ad2 307 &pinctrl_adc0_ad3 308 &pinctrl_adc0_ad4 309 &pinctrl_adc0_ad5 310 &pinctrl_adc0_ad6 311 &pinctrl_adc0_ad7 312 &pinctrl_adc0_ad8 313 &pinctrl_adc0_ad9 314 &pinctrl_adc0_ad10 315 &pinctrl_adc0_ad11 316 >; 317 clocks = <&adc_clk>, 318 <&adc_op_clk>; 319 clock-names = "adc_clk", "adc_op_clk"; 320 atmel,adc-channels-used = <0xfff>; 321 atmel,adc-startup-time = <40>; 322 atmel,adc-use-external-triggers; 323 atmel,adc-vref = <3000>; 324 atmel,adc-res = <10 12>; 325 atmel,adc-sample-hold-time = <11>; 326 atmel,adc-res-names = "lowres", "highres"; 327 status = "disabled"; 328 329 trigger0 { 330 trigger-name = "external-rising"; 331 trigger-value = <0x1>; 332 trigger-external; 333 }; 334 trigger1 { 335 trigger-name = "external-falling"; 336 trigger-value = <0x2>; 337 trigger-external; 338 }; 339 trigger2 { 340 trigger-name = "external-any"; 341 trigger-value = <0x3>; 342 trigger-external; 343 }; 344 trigger3 { 345 trigger-name = "continuous"; 346 trigger-value = <0x6>; 347 }; 348 }; 349 350 i2c2: i2c@f801c000 { 351 compatible = "atmel,at91sam9x5-i2c"; 352 reg = <0xf801c000 0x4000>; 353 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; 354 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 355 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 356 dma-names = "tx", "rx"; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_i2c2>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&twi2_clk>; 362 status = "disabled"; 363 }; 364 365 usart2: serial@f8020000 { 366 compatible = "atmel,at91sam9260-usart"; 367 reg = <0xf8020000 0x100>; 368 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 369 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, 370 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_usart2>; 374 clocks = <&usart2_clk>; 375 clock-names = "usart"; 376 status = "disabled"; 377 }; 378 379 usart3: serial@f8024000 { 380 compatible = "atmel,at91sam9260-usart"; 381 reg = <0xf8024000 0x100>; 382 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 383 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, 384 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_usart3>; 388 clocks = <&usart3_clk>; 389 clock-names = "usart"; 390 status = "disabled"; 391 }; 392 393 sha@f8034000 { 394 compatible = "atmel,at91sam9g46-sha"; 395 reg = <0xf8034000 0x100>; 396 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 397 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; 398 dma-names = "tx"; 399 clocks = <&sha_clk>; 400 clock-names = "sha_clk"; 401 }; 402 403 aes@f8038000 { 404 compatible = "atmel,at91sam9g46-aes"; 405 reg = <0xf8038000 0x100>; 406 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; 407 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, 408 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; 409 dma-names = "tx", "rx"; 410 clocks = <&aes_clk>; 411 clock-names = "aes_clk"; 412 }; 413 414 tdes@f803c000 { 415 compatible = "atmel,at91sam9g46-tdes"; 416 reg = <0xf803c000 0x100>; 417 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 418 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, 419 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; 420 dma-names = "tx", "rx"; 421 clocks = <&tdes_clk>; 422 clock-names = "tdes_clk"; 423 }; 424 425 trng@f8040000 { 426 compatible = "atmel,at91sam9g45-trng"; 427 reg = <0xf8040000 0x100>; 428 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 429 clocks = <&trng_clk>; 430 }; 431 432 dma0: dma-controller@ffffe600 { 433 compatible = "atmel,at91sam9g45-dma"; 434 reg = <0xffffe600 0x200>; 435 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 436 #dma-cells = <2>; 437 clocks = <&dma0_clk>; 438 clock-names = "dma_clk"; 439 }; 440 441 dma1: dma-controller@ffffe800 { 442 compatible = "atmel,at91sam9g45-dma"; 443 reg = <0xffffe800 0x200>; 444 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 445 #dma-cells = <2>; 446 clocks = <&dma1_clk>; 447 clock-names = "dma_clk"; 448 }; 449 450 ramc0: ramc@ffffea00 { 451 compatible = "atmel,sama5d3-ddramc"; 452 reg = <0xffffea00 0x200>; 453 clocks = <&ddrck>, <&mpddr_clk>; 454 clock-names = "ddrck", "mpddr"; 455 }; 456 457 dbgu: serial@ffffee00 { 458 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 459 reg = <0xffffee00 0x200>; 460 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 461 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, 462 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 463 dma-names = "tx", "rx"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_dbgu>; 466 clocks = <&dbgu_clk>; 467 clock-names = "usart"; 468 status = "disabled"; 469 }; 470 471 aic: interrupt-controller@fffff000 { 472 #interrupt-cells = <3>; 473 compatible = "atmel,sama5d3-aic"; 474 interrupt-controller; 475 reg = <0xfffff000 0x200>; 476 atmel,external-irqs = <47>; 477 }; 478 479 pinctrl@fffff200 { 480 #address-cells = <1>; 481 #size-cells = <1>; 482 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; 483 ranges = <0xfffff200 0xfffff200 0xa00>; 484 atmel,mux-mask = < 485 /* A B C */ 486 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ 487 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ 488 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ 489 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 490 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ 491 >; 492 493 /* shared pinctrl settings */ 494 adc0 { 495 pinctrl_adc0_adtrg: adc0_adtrg { 496 atmel,pins = 497 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ 498 }; 499 pinctrl_adc0_ad0: adc0_ad0 { 500 atmel,pins = 501 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ 502 }; 503 pinctrl_adc0_ad1: adc0_ad1 { 504 atmel,pins = 505 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ 506 }; 507 pinctrl_adc0_ad2: adc0_ad2 { 508 atmel,pins = 509 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ 510 }; 511 pinctrl_adc0_ad3: adc0_ad3 { 512 atmel,pins = 513 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ 514 }; 515 pinctrl_adc0_ad4: adc0_ad4 { 516 atmel,pins = 517 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ 518 }; 519 pinctrl_adc0_ad5: adc0_ad5 { 520 atmel,pins = 521 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ 522 }; 523 pinctrl_adc0_ad6: adc0_ad6 { 524 atmel,pins = 525 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ 526 }; 527 pinctrl_adc0_ad7: adc0_ad7 { 528 atmel,pins = 529 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ 530 }; 531 pinctrl_adc0_ad8: adc0_ad8 { 532 atmel,pins = 533 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ 534 }; 535 pinctrl_adc0_ad9: adc0_ad9 { 536 atmel,pins = 537 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ 538 }; 539 pinctrl_adc0_ad10: adc0_ad10 { 540 atmel,pins = 541 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ 542 }; 543 pinctrl_adc0_ad11: adc0_ad11 { 544 atmel,pins = 545 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ 546 }; 547 }; 548 549 dbgu { 550 pinctrl_dbgu: dbgu-0 { 551 atmel,pins = 552 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ 553 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ 554 }; 555 }; 556 557 i2c0 { 558 pinctrl_i2c0: i2c0-0 { 559 atmel,pins = 560 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ 561 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ 562 }; 563 }; 564 565 i2c1 { 566 pinctrl_i2c1: i2c1-0 { 567 atmel,pins = 568 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ 569 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ 570 }; 571 }; 572 573 i2c2 { 574 pinctrl_i2c2: i2c2-0 { 575 atmel,pins = 576 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ 577 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ 578 }; 579 }; 580 581 isi { 582 pinctrl_isi_data_0_7: isi-0-data-0-7 { 583 atmel,pins = 584 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 585 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 586 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ 587 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ 588 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ 589 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ 590 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ 591 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 592 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 593 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 594 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 595 }; 596 597 pinctrl_isi_data_8_9: isi-0-data-8-9 { 598 atmel,pins = 599 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 600 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 601 }; 602 603 pinctrl_isi_data_10_11: isi-0-data-10-11 { 604 atmel,pins = 605 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */ 606 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ 607 }; 608 }; 609 610 mmc0 { 611 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 612 atmel,pins = 613 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ 614 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ 615 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ 616 }; 617 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 618 atmel,pins = 619 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ 620 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ 621 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ 622 }; 623 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 624 atmel,pins = 625 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ 626 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ 627 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ 628 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ 629 }; 630 }; 631 632 mmc1 { 633 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 634 atmel,pins = 635 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ 636 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ 637 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ 638 }; 639 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 640 atmel,pins = 641 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 642 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 643 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 644 }; 645 }; 646 647 nand0 { 648 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 649 atmel,pins = 650 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ 651 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ 652 }; 653 }; 654 655 pwm0 { 656 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { 657 atmel,pins = 658 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ 659 }; 660 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { 661 atmel,pins = 662 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ 663 }; 664 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { 665 atmel,pins = 666 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ 667 }; 668 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { 669 atmel,pins = 670 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ 671 }; 672 673 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { 674 atmel,pins = 675 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ 676 }; 677 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { 678 atmel,pins = 679 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ 680 }; 681 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { 682 atmel,pins = 683 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ 684 }; 685 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { 686 atmel,pins = 687 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ 688 }; 689 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { 690 atmel,pins = 691 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ 692 }; 693 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { 694 atmel,pins = 695 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ 696 }; 697 698 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { 699 atmel,pins = 700 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ 701 }; 702 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { 703 atmel,pins = 704 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ 705 }; 706 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { 707 atmel,pins = 708 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ 709 }; 710 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { 711 atmel,pins = 712 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ 713 }; 714 715 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { 716 atmel,pins = 717 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ 718 }; 719 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { 720 atmel,pins = 721 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ 722 }; 723 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { 724 atmel,pins = 725 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ 726 }; 727 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { 728 atmel,pins = 729 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ 730 }; 731 }; 732 733 spi0 { 734 pinctrl_spi0: spi0-0 { 735 atmel,pins = 736 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ 737 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ 738 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ 739 }; 740 }; 741 742 spi1 { 743 pinctrl_spi1: spi1-0 { 744 atmel,pins = 745 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ 746 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ 747 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ 748 }; 749 }; 750 751 ssc0 { 752 pinctrl_ssc0_tx: ssc0_tx { 753 atmel,pins = 754 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ 755 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ 756 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ 757 }; 758 759 pinctrl_ssc0_rx: ssc0_rx { 760 atmel,pins = 761 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ 762 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ 763 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ 764 }; 765 }; 766 767 ssc1 { 768 pinctrl_ssc1_tx: ssc1_tx { 769 atmel,pins = 770 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ 771 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ 772 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ 773 }; 774 775 pinctrl_ssc1_rx: ssc1_rx { 776 atmel,pins = 777 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ 778 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ 779 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ 780 }; 781 }; 782 783 uart0 { 784 pinctrl_uart0: uart0-0 { 785 atmel,pins = 786 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */ 787 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */ 788 }; 789 }; 790 791 uart1 { 792 pinctrl_uart1: uart1-0 { 793 atmel,pins = 794 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */ 795 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */ 796 }; 797 }; 798 799 usart0 { 800 pinctrl_usart0: usart0-0 { 801 atmel,pins = 802 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ 803 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ 804 }; 805 806 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 807 atmel,pins = 808 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ 809 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ 810 }; 811 }; 812 813 usart1 { 814 pinctrl_usart1: usart1-0 { 815 atmel,pins = 816 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ 817 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ 818 }; 819 820 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 821 atmel,pins = 822 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ 823 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ 824 }; 825 }; 826 827 usart2 { 828 pinctrl_usart2: usart2-0 { 829 atmel,pins = 830 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ 831 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ 832 }; 833 834 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 835 atmel,pins = 836 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ 837 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ 838 }; 839 }; 840 841 usart3 { 842 pinctrl_usart3: usart3-0 { 843 atmel,pins = 844 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ 845 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ 846 }; 847 848 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 849 atmel,pins = 850 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ 851 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ 852 }; 853 }; 854 855 856 pioA: gpio@fffff200 { 857 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 858 reg = <0xfffff200 0x100>; 859 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; 860 #gpio-cells = <2>; 861 gpio-controller; 862 interrupt-controller; 863 #interrupt-cells = <2>; 864 clocks = <&pioA_clk>; 865 }; 866 867 pioB: gpio@fffff400 { 868 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 869 reg = <0xfffff400 0x100>; 870 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; 871 #gpio-cells = <2>; 872 gpio-controller; 873 interrupt-controller; 874 #interrupt-cells = <2>; 875 clocks = <&pioB_clk>; 876 }; 877 878 pioC: gpio@fffff600 { 879 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 880 reg = <0xfffff600 0x100>; 881 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; 882 #gpio-cells = <2>; 883 gpio-controller; 884 interrupt-controller; 885 #interrupt-cells = <2>; 886 clocks = <&pioC_clk>; 887 }; 888 889 pioD: gpio@fffff800 { 890 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 891 reg = <0xfffff800 0x100>; 892 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; 893 #gpio-cells = <2>; 894 gpio-controller; 895 interrupt-controller; 896 #interrupt-cells = <2>; 897 clocks = <&pioD_clk>; 898 }; 899 900 pioE: gpio@fffffa00 { 901 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 902 reg = <0xfffffa00 0x100>; 903 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; 904 #gpio-cells = <2>; 905 gpio-controller; 906 interrupt-controller; 907 #interrupt-cells = <2>; 908 clocks = <&pioE_clk>; 909 }; 910 }; 911 912 pmc: pmc@fffffc00 { 913 compatible = "atmel,sama5d3-pmc", "syscon"; 914 reg = <0xfffffc00 0x120>; 915 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 916 interrupt-controller; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 #interrupt-cells = <1>; 920 921 main_rc_osc: main_rc_osc { 922 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 923 #clock-cells = <0>; 924 interrupt-parent = <&pmc>; 925 interrupts = <AT91_PMC_MOSCRCS>; 926 clock-frequency = <12000000>; 927 clock-accuracy = <50000000>; 928 }; 929 930 main_osc: main_osc { 931 compatible = "atmel,at91rm9200-clk-main-osc"; 932 #clock-cells = <0>; 933 interrupt-parent = <&pmc>; 934 interrupts = <AT91_PMC_MOSCS>; 935 clocks = <&main_xtal>; 936 }; 937 938 main: mainck { 939 compatible = "atmel,at91sam9x5-clk-main"; 940 #clock-cells = <0>; 941 interrupt-parent = <&pmc>; 942 interrupts = <AT91_PMC_MOSCSELS>; 943 clocks = <&main_rc_osc &main_osc>; 944 }; 945 946 plla: pllack { 947 compatible = "atmel,sama5d3-clk-pll"; 948 #clock-cells = <0>; 949 interrupt-parent = <&pmc>; 950 interrupts = <AT91_PMC_LOCKA>; 951 clocks = <&main>; 952 reg = <0>; 953 atmel,clk-input-range = <8000000 50000000>; 954 #atmel,pll-clk-output-range-cells = <4>; 955 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; 956 }; 957 958 plladiv: plladivck { 959 compatible = "atmel,at91sam9x5-clk-plldiv"; 960 #clock-cells = <0>; 961 clocks = <&plla>; 962 }; 963 964 utmi: utmick { 965 compatible = "atmel,at91sam9x5-clk-utmi"; 966 #clock-cells = <0>; 967 interrupt-parent = <&pmc>; 968 interrupts = <AT91_PMC_LOCKU>; 969 clocks = <&main>; 970 }; 971 972 mck: masterck { 973 compatible = "atmel,at91sam9x5-clk-master"; 974 #clock-cells = <0>; 975 interrupt-parent = <&pmc>; 976 interrupts = <AT91_PMC_MCKRDY>; 977 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 978 atmel,clk-output-range = <0 166000000>; 979 atmel,clk-divisors = <1 2 4 3>; 980 }; 981 982 usb: usbck { 983 compatible = "atmel,at91sam9x5-clk-usb"; 984 #clock-cells = <0>; 985 clocks = <&plladiv>, <&utmi>; 986 }; 987 988 prog: progck { 989 compatible = "atmel,at91sam9x5-clk-programmable"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 interrupt-parent = <&pmc>; 993 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 994 995 prog0: prog0 { 996 #clock-cells = <0>; 997 reg = <0>; 998 interrupts = <AT91_PMC_PCKRDY(0)>; 999 }; 1000 1001 prog1: prog1 { 1002 #clock-cells = <0>; 1003 reg = <1>; 1004 interrupts = <AT91_PMC_PCKRDY(1)>; 1005 }; 1006 1007 prog2: prog2 { 1008 #clock-cells = <0>; 1009 reg = <2>; 1010 interrupts = <AT91_PMC_PCKRDY(2)>; 1011 }; 1012 }; 1013 1014 smd: smdclk { 1015 compatible = "atmel,at91sam9x5-clk-smd"; 1016 #clock-cells = <0>; 1017 clocks = <&plladiv>, <&utmi>; 1018 }; 1019 1020 systemck { 1021 compatible = "atmel,at91rm9200-clk-system"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 1025 ddrck: ddrck { 1026 #clock-cells = <0>; 1027 reg = <2>; 1028 clocks = <&mck>; 1029 }; 1030 1031 smdck: smdck { 1032 #clock-cells = <0>; 1033 reg = <4>; 1034 clocks = <&smd>; 1035 }; 1036 1037 uhpck: uhpck { 1038 #clock-cells = <0>; 1039 reg = <6>; 1040 clocks = <&usb>; 1041 }; 1042 1043 udpck: udpck { 1044 #clock-cells = <0>; 1045 reg = <7>; 1046 clocks = <&usb>; 1047 }; 1048 1049 pck0: pck0 { 1050 #clock-cells = <0>; 1051 reg = <8>; 1052 clocks = <&prog0>; 1053 }; 1054 1055 pck1: pck1 { 1056 #clock-cells = <0>; 1057 reg = <9>; 1058 clocks = <&prog1>; 1059 }; 1060 1061 pck2: pck2 { 1062 #clock-cells = <0>; 1063 reg = <10>; 1064 clocks = <&prog2>; 1065 }; 1066 }; 1067 1068 periphck { 1069 compatible = "atmel,at91sam9x5-clk-peripheral"; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clocks = <&mck>; 1073 1074 dbgu_clk: dbgu_clk { 1075 #clock-cells = <0>; 1076 reg = <2>; 1077 }; 1078 1079 hsmc_clk: hsmc_clk { 1080 #clock-cells = <0>; 1081 reg = <5>; 1082 }; 1083 1084 pioA_clk: pioA_clk { 1085 #clock-cells = <0>; 1086 reg = <6>; 1087 }; 1088 1089 pioB_clk: pioB_clk { 1090 #clock-cells = <0>; 1091 reg = <7>; 1092 }; 1093 1094 pioC_clk: pioC_clk { 1095 #clock-cells = <0>; 1096 reg = <8>; 1097 }; 1098 1099 pioD_clk: pioD_clk { 1100 #clock-cells = <0>; 1101 reg = <9>; 1102 }; 1103 1104 pioE_clk: pioE_clk { 1105 #clock-cells = <0>; 1106 reg = <10>; 1107 }; 1108 1109 usart0_clk: usart0_clk { 1110 #clock-cells = <0>; 1111 reg = <12>; 1112 atmel,clk-output-range = <0 66000000>; 1113 }; 1114 1115 usart1_clk: usart1_clk { 1116 #clock-cells = <0>; 1117 reg = <13>; 1118 atmel,clk-output-range = <0 66000000>; 1119 }; 1120 1121 usart2_clk: usart2_clk { 1122 #clock-cells = <0>; 1123 reg = <14>; 1124 atmel,clk-output-range = <0 66000000>; 1125 }; 1126 1127 usart3_clk: usart3_clk { 1128 #clock-cells = <0>; 1129 reg = <15>; 1130 atmel,clk-output-range = <0 66000000>; 1131 }; 1132 1133 uart0_clk: uart0_clk { 1134 #clock-cells = <0>; 1135 reg = <16>; 1136 atmel,clk-output-range = <0 66000000>; 1137 }; 1138 1139 twi0_clk: twi0_clk { 1140 reg = <18>; 1141 #clock-cells = <0>; 1142 atmel,clk-output-range = <0 16625000>; 1143 }; 1144 1145 twi1_clk: twi1_clk { 1146 #clock-cells = <0>; 1147 reg = <19>; 1148 atmel,clk-output-range = <0 16625000>; 1149 }; 1150 1151 twi2_clk: twi2_clk { 1152 #clock-cells = <0>; 1153 reg = <20>; 1154 atmel,clk-output-range = <0 16625000>; 1155 }; 1156 1157 mci0_clk: mci0_clk { 1158 #clock-cells = <0>; 1159 reg = <21>; 1160 }; 1161 1162 mci1_clk: mci1_clk { 1163 #clock-cells = <0>; 1164 reg = <22>; 1165 }; 1166 1167 spi0_clk: spi0_clk { 1168 #clock-cells = <0>; 1169 reg = <24>; 1170 atmel,clk-output-range = <0 133000000>; 1171 }; 1172 1173 spi1_clk: spi1_clk { 1174 #clock-cells = <0>; 1175 reg = <25>; 1176 atmel,clk-output-range = <0 133000000>; 1177 }; 1178 1179 tcb0_clk: tcb0_clk { 1180 #clock-cells = <0>; 1181 reg = <26>; 1182 atmel,clk-output-range = <0 133000000>; 1183 }; 1184 1185 pwm_clk: pwm_clk { 1186 #clock-cells = <0>; 1187 reg = <28>; 1188 }; 1189 1190 adc_clk: adc_clk { 1191 #clock-cells = <0>; 1192 reg = <29>; 1193 atmel,clk-output-range = <0 66000000>; 1194 }; 1195 1196 dma0_clk: dma0_clk { 1197 #clock-cells = <0>; 1198 reg = <30>; 1199 }; 1200 1201 dma1_clk: dma1_clk { 1202 #clock-cells = <0>; 1203 reg = <31>; 1204 }; 1205 1206 uhphs_clk: uhphs_clk { 1207 #clock-cells = <0>; 1208 reg = <32>; 1209 }; 1210 1211 udphs_clk: udphs_clk { 1212 #clock-cells = <0>; 1213 reg = <33>; 1214 }; 1215 1216 isi_clk: isi_clk { 1217 #clock-cells = <0>; 1218 reg = <37>; 1219 }; 1220 1221 ssc0_clk: ssc0_clk { 1222 #clock-cells = <0>; 1223 reg = <38>; 1224 atmel,clk-output-range = <0 66000000>; 1225 }; 1226 1227 ssc1_clk: ssc1_clk { 1228 #clock-cells = <0>; 1229 reg = <39>; 1230 atmel,clk-output-range = <0 66000000>; 1231 }; 1232 1233 sha_clk: sha_clk { 1234 #clock-cells = <0>; 1235 reg = <42>; 1236 }; 1237 1238 aes_clk: aes_clk { 1239 #clock-cells = <0>; 1240 reg = <43>; 1241 }; 1242 1243 tdes_clk: tdes_clk { 1244 #clock-cells = <0>; 1245 reg = <44>; 1246 }; 1247 1248 trng_clk: trng_clk { 1249 #clock-cells = <0>; 1250 reg = <45>; 1251 }; 1252 1253 fuse_clk: fuse_clk { 1254 #clock-cells = <0>; 1255 reg = <48>; 1256 }; 1257 1258 mpddr_clk: mpddr_clk { 1259 #clock-cells = <0>; 1260 reg = <49>; 1261 }; 1262 }; 1263 }; 1264 1265 rstc@fffffe00 { 1266 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 1267 reg = <0xfffffe00 0x10>; 1268 clocks = <&clk32k>; 1269 }; 1270 1271 shutdown-controller@fffffe10 { 1272 compatible = "atmel,at91sam9x5-shdwc"; 1273 reg = <0xfffffe10 0x10>; 1274 clocks = <&clk32k>; 1275 }; 1276 1277 pit: timer@fffffe30 { 1278 compatible = "atmel,at91sam9260-pit"; 1279 reg = <0xfffffe30 0xf>; 1280 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1281 clocks = <&mck>; 1282 }; 1283 1284 watchdog@fffffe40 { 1285 compatible = "atmel,at91sam9260-wdt"; 1286 reg = <0xfffffe40 0x10>; 1287 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 1288 clocks = <&clk32k>; 1289 atmel,watchdog-type = "hardware"; 1290 atmel,reset-type = "all"; 1291 atmel,dbg-halt; 1292 status = "disabled"; 1293 }; 1294 1295 sckc@fffffe50 { 1296 compatible = "atmel,at91sam9x5-sckc"; 1297 reg = <0xfffffe50 0x4>; 1298 1299 slow_rc_osc: slow_rc_osc { 1300 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1301 #clock-cells = <0>; 1302 clock-frequency = <32768>; 1303 clock-accuracy = <50000000>; 1304 atmel,startup-time-usec = <75>; 1305 }; 1306 1307 slow_osc: slow_osc { 1308 compatible = "atmel,at91sam9x5-clk-slow-osc"; 1309 #clock-cells = <0>; 1310 clocks = <&slow_xtal>; 1311 atmel,startup-time-usec = <1200000>; 1312 }; 1313 1314 clk32k: slowck { 1315 compatible = "atmel,at91sam9x5-clk-slow"; 1316 #clock-cells = <0>; 1317 clocks = <&slow_rc_osc &slow_osc>; 1318 }; 1319 }; 1320 1321 rtc@fffffeb0 { 1322 compatible = "atmel,at91rm9200-rtc"; 1323 reg = <0xfffffeb0 0x30>; 1324 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1325 clocks = <&clk32k>; 1326 }; 1327 }; 1328 1329 usb0: gadget@00500000 { 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 compatible = "atmel,sama5d3-udc"; 1333 reg = <0x00500000 0x100000 1334 0xf8030000 0x4000>; 1335 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1336 clocks = <&udphs_clk>, <&utmi>; 1337 clock-names = "pclk", "hclk"; 1338 status = "disabled"; 1339 1340 ep@0 { 1341 reg = <0>; 1342 atmel,fifo-size = <64>; 1343 atmel,nb-banks = <1>; 1344 }; 1345 1346 ep@1 { 1347 reg = <1>; 1348 atmel,fifo-size = <1024>; 1349 atmel,nb-banks = <3>; 1350 atmel,can-dma; 1351 atmel,can-isoc; 1352 }; 1353 1354 ep@2 { 1355 reg = <2>; 1356 atmel,fifo-size = <1024>; 1357 atmel,nb-banks = <3>; 1358 atmel,can-dma; 1359 atmel,can-isoc; 1360 }; 1361 1362 ep@3 { 1363 reg = <3>; 1364 atmel,fifo-size = <1024>; 1365 atmel,nb-banks = <2>; 1366 atmel,can-dma; 1367 }; 1368 1369 ep@4 { 1370 reg = <4>; 1371 atmel,fifo-size = <1024>; 1372 atmel,nb-banks = <2>; 1373 atmel,can-dma; 1374 }; 1375 1376 ep@5 { 1377 reg = <5>; 1378 atmel,fifo-size = <1024>; 1379 atmel,nb-banks = <2>; 1380 atmel,can-dma; 1381 }; 1382 1383 ep@6 { 1384 reg = <6>; 1385 atmel,fifo-size = <1024>; 1386 atmel,nb-banks = <2>; 1387 atmel,can-dma; 1388 }; 1389 1390 ep@7 { 1391 reg = <7>; 1392 atmel,fifo-size = <1024>; 1393 atmel,nb-banks = <2>; 1394 atmel,can-dma; 1395 }; 1396 1397 ep@8 { 1398 reg = <8>; 1399 atmel,fifo-size = <1024>; 1400 atmel,nb-banks = <2>; 1401 }; 1402 1403 ep@9 { 1404 reg = <9>; 1405 atmel,fifo-size = <1024>; 1406 atmel,nb-banks = <2>; 1407 }; 1408 1409 ep@10 { 1410 reg = <10>; 1411 atmel,fifo-size = <1024>; 1412 atmel,nb-banks = <2>; 1413 }; 1414 1415 ep@11 { 1416 reg = <11>; 1417 atmel,fifo-size = <1024>; 1418 atmel,nb-banks = <2>; 1419 }; 1420 1421 ep@12 { 1422 reg = <12>; 1423 atmel,fifo-size = <1024>; 1424 atmel,nb-banks = <2>; 1425 }; 1426 1427 ep@13 { 1428 reg = <13>; 1429 atmel,fifo-size = <1024>; 1430 atmel,nb-banks = <2>; 1431 }; 1432 1433 ep@14 { 1434 reg = <14>; 1435 atmel,fifo-size = <1024>; 1436 atmel,nb-banks = <2>; 1437 }; 1438 1439 ep@15 { 1440 reg = <15>; 1441 atmel,fifo-size = <1024>; 1442 atmel,nb-banks = <2>; 1443 }; 1444 }; 1445 1446 usb1: ohci@00600000 { 1447 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1448 reg = <0x00600000 0x100000>; 1449 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1450 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1451 clock-names = "ohci_clk", "hclk", "uhpck"; 1452 status = "disabled"; 1453 }; 1454 1455 usb2: ehci@00700000 { 1456 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1457 reg = <0x00700000 0x100000>; 1458 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1459 clocks = <&utmi>, <&uhphs_clk>; 1460 clock-names = "usb_clk", "ehci_clk"; 1461 status = "disabled"; 1462 }; 1463 1464 nand0: nand@60000000 { 1465 compatible = "atmel,at91rm9200-nand"; 1466 #address-cells = <1>; 1467 #size-cells = <1>; 1468 ranges; 1469 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1470 0xffffc070 0x00000490 /* SMC PMECC regs */ 1471 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1472 0x00110000 0x00018000 /* ROM code */ 1473 >; 1474 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1475 atmel,nand-addr-offset = <21>; 1476 atmel,nand-cmd-offset = <22>; 1477 atmel,nand-has-dma; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1480 atmel,pmecc-lookup-table-offset = <0x0 0x8000>; 1481 status = "disabled"; 1482 1483 nfc@70000000 { 1484 compatible = "atmel,sama5d3-nfc"; 1485 #address-cells = <1>; 1486 #size-cells = <1>; 1487 reg = < 1488 0x70000000 0x08000000 /* NFC Command Registers */ 1489 0xffffc000 0x00000070 /* NFC HSMC regs */ 1490 0x00200000 0x00100000 /* NFC SRAM banks */ 1491 >; 1492 clocks = <&hsmc_clk>; 1493 }; 1494 }; 1495 }; 1496}; 1497