1/* 2 * linux/arch/x86_64/entry.S 3 * 4 * Copyright (C) 1991, 1992 Linus Torvalds 5 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * 8 * entry.S contains the system-call and fault low-level handling routines. 9 * 10 * Some of this is documented in Documentation/x86/entry_64.txt 11 * 12 * A note on terminology: 13 * - iret frame: Architecture defined interrupt frame from SS to RIP 14 * at the top of the kernel process stack. 15 * 16 * Some macro usage: 17 * - ENTRY/END: Define functions in the symbol table. 18 * - TRACE_IRQ_*: Trace hardirq state for lock debugging. 19 * - idtentry: Define exception entry points. 20 */ 21#include <linux/linkage.h> 22#include <asm/segment.h> 23#include <asm/cache.h> 24#include <asm/errno.h> 25#include "calling.h" 26#include <asm/asm-offsets.h> 27#include <asm/msr.h> 28#include <asm/unistd.h> 29#include <asm/thread_info.h> 30#include <asm/hw_irq.h> 31#include <asm/page_types.h> 32#include <asm/irqflags.h> 33#include <asm/paravirt.h> 34#include <asm/percpu.h> 35#include <asm/asm.h> 36#include <asm/smap.h> 37#include <asm/pgtable_types.h> 38#include <asm/export.h> 39#include <asm/kaiser.h> 40#include <asm/nospec-branch.h> 41#include <linux/err.h> 42 43/* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ 44#include <linux/elf-em.h> 45#define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) 46#define __AUDIT_ARCH_64BIT 0x80000000 47#define __AUDIT_ARCH_LE 0x40000000 48 49.code64 50.section .entry.text, "ax" 51 52#ifdef CONFIG_PARAVIRT 53ENTRY(native_usergs_sysret64) 54 swapgs 55 sysretq 56ENDPROC(native_usergs_sysret64) 57#endif /* CONFIG_PARAVIRT */ 58 59.macro TRACE_IRQS_IRETQ 60#ifdef CONFIG_TRACE_IRQFLAGS 61 bt $9, EFLAGS(%rsp) /* interrupts off? */ 62 jnc 1f 63 TRACE_IRQS_ON 641: 65#endif 66.endm 67 68/* 69 * When dynamic function tracer is enabled it will add a breakpoint 70 * to all locations that it is about to modify, sync CPUs, update 71 * all the code, sync CPUs, then remove the breakpoints. In this time 72 * if lockdep is enabled, it might jump back into the debug handler 73 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). 74 * 75 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to 76 * make sure the stack pointer does not get reset back to the top 77 * of the debug stack, and instead just reuses the current stack. 78 */ 79#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) 80 81.macro TRACE_IRQS_OFF_DEBUG 82 call debug_stack_set_zero 83 TRACE_IRQS_OFF 84 call debug_stack_reset 85.endm 86 87.macro TRACE_IRQS_ON_DEBUG 88 call debug_stack_set_zero 89 TRACE_IRQS_ON 90 call debug_stack_reset 91.endm 92 93.macro TRACE_IRQS_IRETQ_DEBUG 94 bt $9, EFLAGS(%rsp) /* interrupts off? */ 95 jnc 1f 96 TRACE_IRQS_ON_DEBUG 971: 98.endm 99 100#else 101# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF 102# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON 103# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ 104#endif 105 106/* 107 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 108 * 109 * This is the only entry point used for 64-bit system calls. The 110 * hardware interface is reasonably well designed and the register to 111 * argument mapping Linux uses fits well with the registers that are 112 * available when SYSCALL is used. 113 * 114 * SYSCALL instructions can be found inlined in libc implementations as 115 * well as some other programs and libraries. There are also a handful 116 * of SYSCALL instructions in the vDSO used, for example, as a 117 * clock_gettimeofday fallback. 118 * 119 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 120 * then loads new ss, cs, and rip from previously programmed MSRs. 121 * rflags gets masked by a value from another MSR (so CLD and CLAC 122 * are not needed). SYSCALL does not save anything on the stack 123 * and does not change rsp. 124 * 125 * Registers on entry: 126 * rax system call number 127 * rcx return address 128 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 129 * rdi arg0 130 * rsi arg1 131 * rdx arg2 132 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 133 * r8 arg4 134 * r9 arg5 135 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 136 * 137 * Only called from user space. 138 * 139 * When user can change pt_regs->foo always force IRET. That is because 140 * it deals with uncanonical addresses better. SYSRET has trouble 141 * with them due to bugs in both AMD and Intel CPUs. 142 */ 143 144ENTRY(entry_SYSCALL_64) 145 /* 146 * Interrupts are off on entry. 147 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, 148 * it is too small to ever cause noticeable irq latency. 149 */ 150 SWAPGS_UNSAFE_STACK 151 SWITCH_KERNEL_CR3_NO_STACK 152 /* 153 * A hypervisor implementation might want to use a label 154 * after the swapgs, so that it can do the swapgs 155 * for the guest and jump here on syscall. 156 */ 157GLOBAL(entry_SYSCALL_64_after_swapgs) 158 159 movq %rsp, PER_CPU_VAR(rsp_scratch) 160 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 161 162 TRACE_IRQS_OFF 163 164 /* Construct struct pt_regs on stack */ 165 pushq $__USER_DS /* pt_regs->ss */ 166 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ 167 pushq %r11 /* pt_regs->flags */ 168 pushq $__USER_CS /* pt_regs->cs */ 169 pushq %rcx /* pt_regs->ip */ 170 pushq %rax /* pt_regs->orig_ax */ 171 pushq %rdi /* pt_regs->di */ 172 pushq %rsi /* pt_regs->si */ 173 pushq %rdx /* pt_regs->dx */ 174 pushq %rcx /* pt_regs->cx */ 175 pushq $-ENOSYS /* pt_regs->ax */ 176 pushq %r8 /* pt_regs->r8 */ 177 pushq %r9 /* pt_regs->r9 */ 178 pushq %r10 /* pt_regs->r10 */ 179 /* 180 * Clear extra registers that a speculation attack might 181 * otherwise want to exploit. Interleave XOR with PUSH 182 * for better uop scheduling: 183 */ 184 xorq %r10, %r10 /* nospec r10 */ 185 pushq %r11 /* pt_regs->r11 */ 186 xorq %r11, %r11 /* nospec r11 */ 187 pushq %rbx /* pt_regs->rbx */ 188 xorl %ebx, %ebx /* nospec rbx */ 189 pushq %rbp /* pt_regs->rbp */ 190 xorl %ebp, %ebp /* nospec rbp */ 191 pushq %r12 /* pt_regs->r12 */ 192 xorq %r12, %r12 /* nospec r12 */ 193 pushq %r13 /* pt_regs->r13 */ 194 xorq %r13, %r13 /* nospec r13 */ 195 pushq %r14 /* pt_regs->r14 */ 196 xorq %r14, %r14 /* nospec r14 */ 197 pushq %r15 /* pt_regs->r15 */ 198 xorq %r15, %r15 /* nospec r15 */ 199 200 /* IRQs are off. */ 201 movq %rsp, %rdi 202 call do_syscall_64 /* returns with IRQs disabled */ 203 204 RESTORE_EXTRA_REGS 205 TRACE_IRQS_IRETQ /* we're about to change IF */ 206 207 /* 208 * Try to use SYSRET instead of IRET if we're returning to 209 * a completely clean 64-bit userspace context. 210 */ 211 movq RCX(%rsp), %rcx 212 movq RIP(%rsp), %r11 213 cmpq %rcx, %r11 /* RCX == RIP */ 214 jne opportunistic_sysret_failed 215 216 /* 217 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 218 * in kernel space. This essentially lets the user take over 219 * the kernel, since userspace controls RSP. 220 * 221 * If width of "canonical tail" ever becomes variable, this will need 222 * to be updated to remain correct on both old and new CPUs. 223 */ 224 .ifne __VIRTUAL_MASK_SHIFT - 47 225 .error "virtual address width changed -- SYSRET checks need update" 226 .endif 227 228 /* Change top 16 bits to be the sign-extension of 47th bit */ 229 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 230 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 231 232 /* If this changed %rcx, it was not canonical */ 233 cmpq %rcx, %r11 234 jne opportunistic_sysret_failed 235 236 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 237 jne opportunistic_sysret_failed 238 239 movq R11(%rsp), %r11 240 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 241 jne opportunistic_sysret_failed 242 243 /* 244 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 245 * restore RF properly. If the slowpath sets it for whatever reason, we 246 * need to restore it correctly. 247 * 248 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 249 * trap from userspace immediately after SYSRET. This would cause an 250 * infinite loop whenever #DB happens with register state that satisfies 251 * the opportunistic SYSRET conditions. For example, single-stepping 252 * this user code: 253 * 254 * movq $stuck_here, %rcx 255 * pushfq 256 * popq %r11 257 * stuck_here: 258 * 259 * would never get past 'stuck_here'. 260 */ 261 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 262 jnz opportunistic_sysret_failed 263 264 /* nothing to check for RSP */ 265 266 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 267 jne opportunistic_sysret_failed 268 269 /* 270 * We win! This label is here just for ease of understanding 271 * perf profiles. Nothing jumps here. 272 */ 273syscall_return_via_sysret: 274 /* rcx and r11 are already restored (see code above) */ 275 RESTORE_C_REGS_EXCEPT_RCX_R11 276 277 /* 278 * This opens a window where we have a user CR3, but are 279 * running in the kernel. This makes using the CS 280 * register useless for telling whether or not we need to 281 * switch CR3 in NMIs. Normal interrupts are OK because 282 * they are off here. 283 */ 284 SWITCH_USER_CR3 285 movq RSP(%rsp), %rsp 286 USERGS_SYSRET64 287 288opportunistic_sysret_failed: 289 /* 290 * This opens a window where we have a user CR3, but are 291 * running in the kernel. This makes using the CS 292 * register useless for telling whether or not we need to 293 * switch CR3 in NMIs. Normal interrupts are OK because 294 * they are off here. 295 */ 296 SWITCH_USER_CR3 297 SWAPGS 298 jmp restore_c_regs_and_iret 299END(entry_SYSCALL_64) 300 301/* 302 * %rdi: prev task 303 * %rsi: next task 304 */ 305ENTRY(__switch_to_asm) 306 /* 307 * Save callee-saved registers 308 * This must match the order in inactive_task_frame 309 */ 310 pushq %rbp 311 pushq %rbx 312 pushq %r12 313 pushq %r13 314 pushq %r14 315 pushq %r15 316 317 /* switch stack */ 318 movq %rsp, TASK_threadsp(%rdi) 319 movq TASK_threadsp(%rsi), %rsp 320 321#ifdef CONFIG_CC_STACKPROTECTOR 322 movq TASK_stack_canary(%rsi), %rbx 323 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset 324#endif 325 326#ifdef CONFIG_RETPOLINE 327 /* 328 * When switching from a shallower to a deeper call stack 329 * the RSB may either underflow or use entries populated 330 * with userspace addresses. On CPUs where those concerns 331 * exist, overwrite the RSB with entries which capture 332 * speculative execution to prevent attack. 333 */ 334 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 335#endif 336 337 /* restore callee-saved registers */ 338 popq %r15 339 popq %r14 340 popq %r13 341 popq %r12 342 popq %rbx 343 popq %rbp 344 345 jmp __switch_to 346END(__switch_to_asm) 347 348/* 349 * A newly forked process directly context switches into this address. 350 * 351 * rax: prev task we switched from 352 * rbx: kernel thread func (NULL for user thread) 353 * r12: kernel thread arg 354 */ 355ENTRY(ret_from_fork) 356 movq %rax, %rdi 357 call schedule_tail /* rdi: 'prev' task parameter */ 358 359 testq %rbx, %rbx /* from kernel_thread? */ 360 jnz 1f /* kernel threads are uncommon */ 361 3622: 363 movq %rsp, %rdi 364 call syscall_return_slowpath /* returns with IRQs disabled */ 365 TRACE_IRQS_ON /* user mode is traced as IRQS on */ 366 SWITCH_USER_CR3 367 SWAPGS 368 jmp restore_regs_and_iret 369 3701: 371 /* kernel thread */ 372 movq %r12, %rdi 373 CALL_NOSPEC %rbx 374 /* 375 * A kernel thread is allowed to return here after successfully 376 * calling do_execve(). Exit to userspace to complete the execve() 377 * syscall. 378 */ 379 movq $0, RAX(%rsp) 380 jmp 2b 381END(ret_from_fork) 382 383/* 384 * Build the entry stubs with some assembler magic. 385 * We pack 1 stub into every 8-byte block. 386 */ 387 .align 8 388ENTRY(irq_entries_start) 389 vector=FIRST_EXTERNAL_VECTOR 390 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) 391 pushq $(~vector+0x80) /* Note: always in signed byte range */ 392 vector=vector+1 393 jmp common_interrupt 394 .align 8 395 .endr 396END(irq_entries_start) 397 398/* 399 * Interrupt entry/exit. 400 * 401 * Interrupt entry points save only callee clobbered registers in fast path. 402 * 403 * Entry runs with interrupts off. 404 */ 405 406/* 0(%rsp): ~(interrupt number) */ 407 .macro interrupt func 408 cld 409 ALLOC_PT_GPREGS_ON_STACK 410 SAVE_C_REGS 411 SAVE_EXTRA_REGS 412 413 testb $3, CS(%rsp) 414 jz 1f 415 416 /* 417 * IRQ from user mode. Switch to kernel gsbase and inform context 418 * tracking that we're in kernel mode. 419 */ 420 SWAPGS 421 SWITCH_KERNEL_CR3 422 423 /* 424 * We need to tell lockdep that IRQs are off. We can't do this until 425 * we fix gsbase, and we should do it before enter_from_user_mode 426 * (which can take locks). Since TRACE_IRQS_OFF idempotent, 427 * the simplest way to handle it is to just call it twice if 428 * we enter from user mode. There's no reason to optimize this since 429 * TRACE_IRQS_OFF is a no-op if lockdep is off. 430 */ 431 TRACE_IRQS_OFF 432 433 CALL_enter_from_user_mode 434 4351: 436 /* 437 * Save previous stack pointer, optionally switch to interrupt stack. 438 * irq_count is used to check if a CPU is already on an interrupt stack 439 * or not. While this is essentially redundant with preempt_count it is 440 * a little cheaper to use a separate counter in the PDA (short of 441 * moving irq_enter into assembly, which would be too much work) 442 */ 443 movq %rsp, %rdi 444 incl PER_CPU_VAR(irq_count) 445 cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp 446 pushq %rdi 447 /* We entered an interrupt context - irqs are off: */ 448 TRACE_IRQS_OFF 449 450 call \func /* rdi points to pt_regs */ 451 .endm 452 453 /* 454 * The interrupt stubs push (~vector+0x80) onto the stack and 455 * then jump to common_interrupt. 456 */ 457 .p2align CONFIG_X86_L1_CACHE_SHIFT 458common_interrupt: 459 ASM_CLAC 460 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ 461 interrupt do_IRQ 462 /* 0(%rsp): old RSP */ 463ret_from_intr: 464 DISABLE_INTERRUPTS(CLBR_NONE) 465 TRACE_IRQS_OFF 466 decl PER_CPU_VAR(irq_count) 467 468 /* Restore saved previous stack */ 469 popq %rsp 470 471 testb $3, CS(%rsp) 472 jz retint_kernel 473 474 /* Interrupt came from user space */ 475GLOBAL(retint_user) 476 mov %rsp,%rdi 477 call prepare_exit_to_usermode 478 TRACE_IRQS_IRETQ 479 SWITCH_USER_CR3 480 SWAPGS 481 jmp restore_regs_and_iret 482 483/* Returning to kernel space */ 484retint_kernel: 485#ifdef CONFIG_PREEMPT 486 /* Interrupts are off */ 487 /* Check if we need preemption */ 488 bt $9, EFLAGS(%rsp) /* were interrupts off? */ 489 jnc 1f 4900: cmpl $0, PER_CPU_VAR(__preempt_count) 491 jnz 1f 492 call preempt_schedule_irq 493 jmp 0b 4941: 495#endif 496 /* 497 * The iretq could re-enable interrupts: 498 */ 499 TRACE_IRQS_IRETQ 500 501/* 502 * At this label, code paths which return to kernel and to user, 503 * which come from interrupts/exception and from syscalls, merge. 504 */ 505GLOBAL(restore_regs_and_iret) 506 RESTORE_EXTRA_REGS 507restore_c_regs_and_iret: 508 RESTORE_C_REGS 509 REMOVE_PT_GPREGS_FROM_STACK 8 510 INTERRUPT_RETURN 511 512ENTRY(native_iret) 513 /* 514 * Are we returning to a stack segment from the LDT? Note: in 515 * 64-bit mode SS:RSP on the exception stack is always valid. 516 */ 517#ifdef CONFIG_X86_ESPFIX64 518 testb $4, (SS-RIP)(%rsp) 519 jnz native_irq_return_ldt 520#endif 521 522.global native_irq_return_iret 523native_irq_return_iret: 524 /* 525 * This may fault. Non-paranoid faults on return to userspace are 526 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 527 * Double-faults due to espfix64 are handled in do_double_fault. 528 * Other faults here are fatal. 529 */ 530 iretq 531 532#ifdef CONFIG_X86_ESPFIX64 533native_irq_return_ldt: 534 /* 535 * We are running with user GSBASE. All GPRs contain their user 536 * values. We have a percpu ESPFIX stack that is eight slots 537 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 538 * of the ESPFIX stack. 539 * 540 * We clobber RAX and RDI in this code. We stash RDI on the 541 * normal stack and RAX on the ESPFIX stack. 542 * 543 * The ESPFIX stack layout we set up looks like this: 544 * 545 * --- top of ESPFIX stack --- 546 * SS 547 * RSP 548 * RFLAGS 549 * CS 550 * RIP <-- RSP points here when we're done 551 * RAX <-- espfix_waddr points here 552 * --- bottom of ESPFIX stack --- 553 */ 554 555 pushq %rdi /* Stash user RDI */ 556 SWAPGS 557 SWITCH_KERNEL_CR3 558 movq PER_CPU_VAR(espfix_waddr), %rdi 559 movq %rax, (0*8)(%rdi) /* user RAX */ 560 movq (1*8)(%rsp), %rax /* user RIP */ 561 movq %rax, (1*8)(%rdi) 562 movq (2*8)(%rsp), %rax /* user CS */ 563 movq %rax, (2*8)(%rdi) 564 movq (3*8)(%rsp), %rax /* user RFLAGS */ 565 movq %rax, (3*8)(%rdi) 566 movq (5*8)(%rsp), %rax /* user SS */ 567 movq %rax, (5*8)(%rdi) 568 movq (4*8)(%rsp), %rax /* user RSP */ 569 movq %rax, (4*8)(%rdi) 570 /* Now RAX == RSP. */ 571 572 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 573 popq %rdi /* Restore user RDI */ 574 575 /* 576 * espfix_stack[31:16] == 0. The page tables are set up such that 577 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 578 * espfix_waddr for any X. That is, there are 65536 RO aliases of 579 * the same page. Set up RSP so that RSP[31:16] contains the 580 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 581 * still points to an RO alias of the ESPFIX stack. 582 */ 583 orq PER_CPU_VAR(espfix_stack), %rax 584 SWITCH_USER_CR3 585 SWAPGS 586 movq %rax, %rsp 587 588 /* 589 * At this point, we cannot write to the stack any more, but we can 590 * still read. 591 */ 592 popq %rax /* Restore user RAX */ 593 594 /* 595 * RSP now points to an ordinary IRET frame, except that the page 596 * is read-only and RSP[31:16] are preloaded with the userspace 597 * values. We can now IRET back to userspace. 598 */ 599 jmp native_irq_return_iret 600#endif 601END(common_interrupt) 602 603/* 604 * APIC interrupts. 605 */ 606.macro apicinterrupt3 num sym do_sym 607ENTRY(\sym) 608 ASM_CLAC 609 pushq $~(\num) 610.Lcommon_\sym: 611 interrupt \do_sym 612 jmp ret_from_intr 613END(\sym) 614.endm 615 616#ifdef CONFIG_TRACING 617#define trace(sym) trace_##sym 618#define smp_trace(sym) smp_trace_##sym 619 620.macro trace_apicinterrupt num sym 621apicinterrupt3 \num trace(\sym) smp_trace(\sym) 622.endm 623#else 624.macro trace_apicinterrupt num sym do_sym 625.endm 626#endif 627 628/* Make sure APIC interrupt handlers end up in the irqentry section: */ 629#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" 630#define POP_SECTION_IRQENTRY .popsection 631 632.macro apicinterrupt num sym do_sym 633PUSH_SECTION_IRQENTRY 634apicinterrupt3 \num \sym \do_sym 635trace_apicinterrupt \num \sym 636POP_SECTION_IRQENTRY 637.endm 638 639#ifdef CONFIG_SMP 640apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt 641apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt 642#endif 643 644#ifdef CONFIG_X86_UV 645apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt 646#endif 647 648apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt 649apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi 650 651#ifdef CONFIG_HAVE_KVM 652apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi 653apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi 654#endif 655 656#ifdef CONFIG_X86_MCE_THRESHOLD 657apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt 658#endif 659 660#ifdef CONFIG_X86_MCE_AMD 661apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt 662#endif 663 664#ifdef CONFIG_X86_THERMAL_VECTOR 665apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt 666#endif 667 668#ifdef CONFIG_SMP 669apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt 670apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt 671apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt 672#endif 673 674apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt 675apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt 676 677#ifdef CONFIG_IRQ_WORK 678apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt 679#endif 680 681/* 682 * Exception entry points. 683 */ 684#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) 685 686.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 687ENTRY(\sym) 688 /* Sanity check */ 689 .if \shift_ist != -1 && \paranoid == 0 690 .error "using shift_ist requires paranoid=1" 691 .endif 692 693 ASM_CLAC 694 PARAVIRT_ADJUST_EXCEPTION_FRAME 695 696 .ifeq \has_error_code 697 pushq $-1 /* ORIG_RAX: no syscall to restart */ 698 .endif 699 700 ALLOC_PT_GPREGS_ON_STACK 701 702 .if \paranoid 703 .if \paranoid == 1 704 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ 705 jnz 1f 706 .endif 707 call paranoid_entry 708 .else 709 call error_entry 710 .endif 711 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ 712 713 .if \paranoid 714 .if \shift_ist != -1 715 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ 716 .else 717 TRACE_IRQS_OFF 718 .endif 719 .endif 720 721 movq %rsp, %rdi /* pt_regs pointer */ 722 723 .if \has_error_code 724 movq ORIG_RAX(%rsp), %rsi /* get error code */ 725 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 726 .else 727 xorl %esi, %esi /* no error code */ 728 .endif 729 730 .if \shift_ist != -1 731 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 732 .endif 733 734 call \do_sym 735 736 .if \shift_ist != -1 737 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) 738 .endif 739 740 /* these procedures expect "no swapgs" flag in ebx */ 741 .if \paranoid 742 jmp paranoid_exit 743 .else 744 jmp error_exit 745 .endif 746 747 .if \paranoid == 1 748 /* 749 * Paranoid entry from userspace. Switch stacks and treat it 750 * as a normal entry. This means that paranoid handlers 751 * run in real process context if user_mode(regs). 752 */ 7531: 754 call error_entry 755 756 757 movq %rsp, %rdi /* pt_regs pointer */ 758 call sync_regs 759 movq %rax, %rsp /* switch stack */ 760 761 movq %rsp, %rdi /* pt_regs pointer */ 762 763 .if \has_error_code 764 movq ORIG_RAX(%rsp), %rsi /* get error code */ 765 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 766 .else 767 xorl %esi, %esi /* no error code */ 768 .endif 769 770 call \do_sym 771 772 jmp error_exit /* %ebx: no swapgs flag */ 773 .endif 774END(\sym) 775.endm 776 777#ifdef CONFIG_TRACING 778.macro trace_idtentry sym do_sym has_error_code:req 779idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code 780idtentry \sym \do_sym has_error_code=\has_error_code 781.endm 782#else 783.macro trace_idtentry sym do_sym has_error_code:req 784idtentry \sym \do_sym has_error_code=\has_error_code 785.endm 786#endif 787 788idtentry divide_error do_divide_error has_error_code=0 789idtentry overflow do_overflow has_error_code=0 790idtentry bounds do_bounds has_error_code=0 791idtentry invalid_op do_invalid_op has_error_code=0 792idtentry device_not_available do_device_not_available has_error_code=0 793idtentry double_fault do_double_fault has_error_code=1 paranoid=2 794idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 795idtentry invalid_TSS do_invalid_TSS has_error_code=1 796idtentry segment_not_present do_segment_not_present has_error_code=1 797idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 798idtentry coprocessor_error do_coprocessor_error has_error_code=0 799idtentry alignment_check do_alignment_check has_error_code=1 800idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 801 802 803 /* 804 * Reload gs selector with exception handling 805 * edi: new selector 806 */ 807ENTRY(native_load_gs_index) 808 pushfq 809 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) 810 SWAPGS 811.Lgs_change: 812 movl %edi, %gs 8132: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 814 SWAPGS 815 popfq 816 ret 817END(native_load_gs_index) 818EXPORT_SYMBOL(native_load_gs_index) 819 820 _ASM_EXTABLE(.Lgs_change, bad_gs) 821 .section .fixup, "ax" 822 /* running with kernelgs */ 823bad_gs: 824 SWAPGS /* switch back to user gs */ 825.macro ZAP_GS 826 /* This can't be a string because the preprocessor needs to see it. */ 827 movl $__USER_DS, %eax 828 movl %eax, %gs 829.endm 830 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 831 xorl %eax, %eax 832 movl %eax, %gs 833 jmp 2b 834 .previous 835 836/* Call softirq on interrupt stack. Interrupts are off. */ 837ENTRY(do_softirq_own_stack) 838 pushq %rbp 839 mov %rsp, %rbp 840 incl PER_CPU_VAR(irq_count) 841 cmove PER_CPU_VAR(irq_stack_ptr), %rsp 842 push %rbp /* frame pointer backlink */ 843 call __do_softirq 844 leaveq 845 decl PER_CPU_VAR(irq_count) 846 ret 847END(do_softirq_own_stack) 848 849#ifdef CONFIG_XEN 850idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 851 852/* 853 * A note on the "critical region" in our callback handler. 854 * We want to avoid stacking callback handlers due to events occurring 855 * during handling of the last event. To do this, we keep events disabled 856 * until we've done all processing. HOWEVER, we must enable events before 857 * popping the stack frame (can't be done atomically) and so it would still 858 * be possible to get enough handler activations to overflow the stack. 859 * Although unlikely, bugs of that kind are hard to track down, so we'd 860 * like to avoid the possibility. 861 * So, on entry to the handler we detect whether we interrupted an 862 * existing activation in its critical region -- if so, we pop the current 863 * activation and restart the handler using the previous one. 864 */ 865ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ 866 867/* 868 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 869 * see the correct pointer to the pt_regs 870 */ 871 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 87211: incl PER_CPU_VAR(irq_count) 873 movq %rsp, %rbp 874 cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp 875 pushq %rbp /* frame pointer backlink */ 876 call xen_evtchn_do_upcall 877 popq %rsp 878 decl PER_CPU_VAR(irq_count) 879#ifndef CONFIG_PREEMPT 880 call xen_maybe_preempt_hcall 881#endif 882 jmp error_exit 883END(xen_do_hypervisor_callback) 884 885/* 886 * Hypervisor uses this for application faults while it executes. 887 * We get here for two reasons: 888 * 1. Fault while reloading DS, ES, FS or GS 889 * 2. Fault while executing IRET 890 * Category 1 we do not need to fix up as Xen has already reloaded all segment 891 * registers that could be reloaded and zeroed the others. 892 * Category 2 we fix up by killing the current process. We cannot use the 893 * normal Linux return path in this case because if we use the IRET hypercall 894 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 895 * We distinguish between categories by comparing each saved segment register 896 * with its current contents: any discrepancy means we in category 1. 897 */ 898ENTRY(xen_failsafe_callback) 899 movl %ds, %ecx 900 cmpw %cx, 0x10(%rsp) 901 jne 1f 902 movl %es, %ecx 903 cmpw %cx, 0x18(%rsp) 904 jne 1f 905 movl %fs, %ecx 906 cmpw %cx, 0x20(%rsp) 907 jne 1f 908 movl %gs, %ecx 909 cmpw %cx, 0x28(%rsp) 910 jne 1f 911 /* All segments match their saved values => Category 2 (Bad IRET). */ 912 movq (%rsp), %rcx 913 movq 8(%rsp), %r11 914 addq $0x30, %rsp 915 pushq $0 /* RIP */ 916 pushq %r11 917 pushq %rcx 918 jmp general_protection 9191: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 920 movq (%rsp), %rcx 921 movq 8(%rsp), %r11 922 addq $0x30, %rsp 923 pushq $-1 /* orig_ax = -1 => not a system call */ 924 ALLOC_PT_GPREGS_ON_STACK 925 SAVE_C_REGS 926 SAVE_EXTRA_REGS 927 jmp error_exit 928END(xen_failsafe_callback) 929 930apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 931 xen_hvm_callback_vector xen_evtchn_do_upcall 932 933#endif /* CONFIG_XEN */ 934 935#if IS_ENABLED(CONFIG_HYPERV) 936apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ 937 hyperv_callback_vector hyperv_vector_handler 938#endif /* CONFIG_HYPERV */ 939 940idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK 941idtentry int3 do_int3 has_error_code=0 942idtentry stack_segment do_stack_segment has_error_code=1 943 944#ifdef CONFIG_XEN 945idtentry xen_debug do_debug has_error_code=0 946idtentry xen_int3 do_int3 has_error_code=0 947idtentry xen_stack_segment do_stack_segment has_error_code=1 948#endif 949 950idtentry general_protection do_general_protection has_error_code=1 951trace_idtentry page_fault do_page_fault has_error_code=1 952 953#ifdef CONFIG_KVM_GUEST 954idtentry async_page_fault do_async_page_fault has_error_code=1 955#endif 956 957#ifdef CONFIG_X86_MCE 958idtentry machine_check do_mce has_error_code=0 paranoid=1 959#endif 960 961/* 962 * Save all registers in pt_regs, and switch gs if needed. 963 * Use slow, but surefire "are we in kernel?" check. 964 * 965 * Return: ebx=0: needs swapgs but not SWITCH_USER_CR3 in paranoid_exit 966 * ebx=1: needs neither swapgs nor SWITCH_USER_CR3 in paranoid_exit 967 * ebx=2: needs both swapgs and SWITCH_USER_CR3 in paranoid_exit 968 * ebx=3: needs SWITCH_USER_CR3 but not swapgs in paranoid_exit 969 */ 970ENTRY(paranoid_entry) 971 cld 972 SAVE_C_REGS 8 973 SAVE_EXTRA_REGS 8 974 movl $1, %ebx 975 movl $MSR_GS_BASE, %ecx 976 rdmsr 977 testl %edx, %edx 978 js 1f /* negative -> in kernel */ 979 SWAPGS 980 xorl %ebx, %ebx 9811: 982#ifdef CONFIG_PAGE_TABLE_ISOLATION 983 /* 984 * We might have come in between a swapgs and a SWITCH_KERNEL_CR3 985 * on entry, or between a SWITCH_USER_CR3 and a swapgs on exit. 986 * Do a conditional SWITCH_KERNEL_CR3: this could safely be done 987 * unconditionally, but we need to find out whether the reverse 988 * should be done on return (conveyed to paranoid_exit in %ebx). 989 */ 990 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER 991 testl $KAISER_SHADOW_PGD_OFFSET, %eax 992 jz 2f 993 orl $2, %ebx 994 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax 995 /* If PCID enabled, set X86_CR3_PCID_NOFLUSH_BIT */ 996 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID 997 movq %rax, %cr3 9982: 999#endif 1000 ret 1001END(paranoid_entry) 1002 1003/* 1004 * "Paranoid" exit path from exception stack. This is invoked 1005 * only on return from non-NMI IST interrupts that came 1006 * from kernel space. 1007 * 1008 * We may be returning to very strange contexts (e.g. very early 1009 * in syscall entry), so checking for preemption here would 1010 * be complicated. Fortunately, we there's no good reason 1011 * to try to handle preemption here. 1012 * 1013 * On entry: ebx=0: needs swapgs but not SWITCH_USER_CR3 1014 * ebx=1: needs neither swapgs nor SWITCH_USER_CR3 1015 * ebx=2: needs both swapgs and SWITCH_USER_CR3 1016 * ebx=3: needs SWITCH_USER_CR3 but not swapgs 1017 */ 1018ENTRY(paranoid_exit) 1019 DISABLE_INTERRUPTS(CLBR_NONE) 1020 TRACE_IRQS_OFF_DEBUG 1021 TRACE_IRQS_IRETQ_DEBUG 1022#ifdef CONFIG_PAGE_TABLE_ISOLATION 1023 /* No ALTERNATIVE for X86_FEATURE_KAISER: paranoid_entry sets %ebx */ 1024 testl $2, %ebx /* SWITCH_USER_CR3 needed? */ 1025 jz paranoid_exit_no_switch 1026 SWITCH_USER_CR3 1027paranoid_exit_no_switch: 1028#endif 1029 testl $1, %ebx /* swapgs needed? */ 1030 jnz paranoid_exit_no_swapgs 1031 SWAPGS_UNSAFE_STACK 1032paranoid_exit_no_swapgs: 1033 RESTORE_EXTRA_REGS 1034 RESTORE_C_REGS 1035 REMOVE_PT_GPREGS_FROM_STACK 8 1036 INTERRUPT_RETURN 1037END(paranoid_exit) 1038 1039/* 1040 * Save all registers in pt_regs, and switch gs if needed. 1041 * Return: EBX=0: came from user mode; EBX=1: otherwise 1042 */ 1043ENTRY(error_entry) 1044 cld 1045 SAVE_C_REGS 8 1046 SAVE_EXTRA_REGS 8 1047 /* 1048 * error_entry() always returns with a kernel gsbase and 1049 * CR3. We must also have a kernel CR3/gsbase before 1050 * calling TRACE_IRQS_*. Just unconditionally switch to 1051 * the kernel CR3 here. 1052 */ 1053 SWITCH_KERNEL_CR3 1054 xorl %ebx, %ebx 1055 testb $3, CS+8(%rsp) 1056 jz .Lerror_kernelspace 1057 1058 /* 1059 * We entered from user mode or we're pretending to have entered 1060 * from user mode due to an IRET fault. 1061 */ 1062 SWAPGS 1063 1064.Lerror_entry_from_usermode_after_swapgs: 1065 /* 1066 * We need to tell lockdep that IRQs are off. We can't do this until 1067 * we fix gsbase, and we should do it before enter_from_user_mode 1068 * (which can take locks). 1069 */ 1070 TRACE_IRQS_OFF 1071 CALL_enter_from_user_mode 1072 ret 1073 1074.Lerror_entry_done: 1075 TRACE_IRQS_OFF 1076 ret 1077 1078 /* 1079 * There are two places in the kernel that can potentially fault with 1080 * usergs. Handle them here. B stepping K8s sometimes report a 1081 * truncated RIP for IRET exceptions returning to compat mode. Check 1082 * for these here too. 1083 */ 1084.Lerror_kernelspace: 1085 incl %ebx 1086 leaq native_irq_return_iret(%rip), %rcx 1087 cmpq %rcx, RIP+8(%rsp) 1088 je .Lerror_bad_iret 1089 movl %ecx, %eax /* zero extend */ 1090 cmpq %rax, RIP+8(%rsp) 1091 je .Lbstep_iret 1092 cmpq $.Lgs_change, RIP+8(%rsp) 1093 jne .Lerror_entry_done 1094 1095 /* 1096 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1097 * gsbase and proceed. We'll fix up the exception and land in 1098 * .Lgs_change's error handler with kernel gsbase. 1099 */ 1100 SWAPGS 1101 jmp .Lerror_entry_done 1102 1103.Lbstep_iret: 1104 /* Fix truncated RIP */ 1105 movq %rcx, RIP+8(%rsp) 1106 /* fall through */ 1107 1108.Lerror_bad_iret: 1109 /* 1110 * We came from an IRET to user mode, so we have user gsbase. 1111 * Switch to kernel gsbase: 1112 */ 1113 SWAPGS 1114 1115 /* 1116 * Pretend that the exception came from user mode: set up pt_regs 1117 * as if we faulted immediately after IRET and clear EBX so that 1118 * error_exit knows that we will be returning to user mode. 1119 */ 1120 mov %rsp, %rdi 1121 call fixup_bad_iret 1122 mov %rax, %rsp 1123 decl %ebx 1124 jmp .Lerror_entry_from_usermode_after_swapgs 1125END(error_entry) 1126 1127 1128/* 1129 * On entry, EBX is a "return to kernel mode" flag: 1130 * 1: already in kernel mode, don't need SWAPGS 1131 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode 1132 */ 1133ENTRY(error_exit) 1134 movl %ebx, %eax 1135 DISABLE_INTERRUPTS(CLBR_NONE) 1136 TRACE_IRQS_OFF 1137 testl %eax, %eax 1138 jnz retint_kernel 1139 jmp retint_user 1140END(error_exit) 1141 1142/* Runs on exception stack */ 1143ENTRY(nmi) 1144 /* 1145 * Fix up the exception frame if we're on Xen. 1146 * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most 1147 * one value to the stack on native, so it may clobber the rdx 1148 * scratch slot, but it won't clobber any of the important 1149 * slots past it. 1150 * 1151 * Xen is a different story, because the Xen frame itself overlaps 1152 * the "NMI executing" variable. 1153 */ 1154 PARAVIRT_ADJUST_EXCEPTION_FRAME 1155 1156 /* 1157 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1158 * the iretq it performs will take us out of NMI context. 1159 * This means that we can have nested NMIs where the next 1160 * NMI is using the top of the stack of the previous NMI. We 1161 * can't let it execute because the nested NMI will corrupt the 1162 * stack of the previous NMI. NMI handlers are not re-entrant 1163 * anyway. 1164 * 1165 * To handle this case we do the following: 1166 * Check the a special location on the stack that contains 1167 * a variable that is set when NMIs are executing. 1168 * The interrupted task's stack is also checked to see if it 1169 * is an NMI stack. 1170 * If the variable is not set and the stack is not the NMI 1171 * stack then: 1172 * o Set the special variable on the stack 1173 * o Copy the interrupt frame into an "outermost" location on the 1174 * stack 1175 * o Copy the interrupt frame into an "iret" location on the stack 1176 * o Continue processing the NMI 1177 * If the variable is set or the previous stack is the NMI stack: 1178 * o Modify the "iret" location to jump to the repeat_nmi 1179 * o return back to the first NMI 1180 * 1181 * Now on exit of the first NMI, we first clear the stack variable 1182 * The NMI stack will tell any nested NMIs at that point that it is 1183 * nested. Then we pop the stack normally with iret, and if there was 1184 * a nested NMI that updated the copy interrupt stack frame, a 1185 * jump will be made to the repeat_nmi code that will handle the second 1186 * NMI. 1187 * 1188 * However, espfix prevents us from directly returning to userspace 1189 * with a single IRET instruction. Similarly, IRET to user mode 1190 * can fault. We therefore handle NMIs from user space like 1191 * other IST entries. 1192 */ 1193 1194 ASM_CLAC 1195 1196 /* Use %rdx as our temp variable throughout */ 1197 pushq %rdx 1198 1199 testb $3, CS-RIP+8(%rsp) 1200 jz .Lnmi_from_kernel 1201 1202 /* 1203 * NMI from user mode. We need to run on the thread stack, but we 1204 * can't go through the normal entry paths: NMIs are masked, and 1205 * we don't want to enable interrupts, because then we'll end 1206 * up in an awkward situation in which IRQs are on but NMIs 1207 * are off. 1208 * 1209 * We also must not push anything to the stack before switching 1210 * stacks lest we corrupt the "NMI executing" variable. 1211 */ 1212 1213 SWAPGS_UNSAFE_STACK 1214 /* 1215 * percpu variables are mapped with user CR3, so no need 1216 * to switch CR3 here. 1217 */ 1218 cld 1219 movq %rsp, %rdx 1220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1221 pushq 5*8(%rdx) /* pt_regs->ss */ 1222 pushq 4*8(%rdx) /* pt_regs->rsp */ 1223 pushq 3*8(%rdx) /* pt_regs->flags */ 1224 pushq 2*8(%rdx) /* pt_regs->cs */ 1225 pushq 1*8(%rdx) /* pt_regs->rip */ 1226 pushq $-1 /* pt_regs->orig_ax */ 1227 pushq %rdi /* pt_regs->di */ 1228 pushq %rsi /* pt_regs->si */ 1229 pushq (%rdx) /* pt_regs->dx */ 1230 pushq %rcx /* pt_regs->cx */ 1231 pushq %rax /* pt_regs->ax */ 1232 pushq %r8 /* pt_regs->r8 */ 1233 pushq %r9 /* pt_regs->r9 */ 1234 pushq %r10 /* pt_regs->r10 */ 1235 pushq %r11 /* pt_regs->r11 */ 1236 pushq %rbx /* pt_regs->rbx */ 1237 pushq %rbp /* pt_regs->rbp */ 1238 pushq %r12 /* pt_regs->r12 */ 1239 pushq %r13 /* pt_regs->r13 */ 1240 pushq %r14 /* pt_regs->r14 */ 1241 pushq %r15 /* pt_regs->r15 */ 1242 1243 /* 1244 * At this point we no longer need to worry about stack damage 1245 * due to nesting -- we're on the normal thread stack and we're 1246 * done with the NMI stack. 1247 */ 1248 1249 movq %rsp, %rdi 1250 movq $-1, %rsi 1251#ifdef CONFIG_PAGE_TABLE_ISOLATION 1252 /* Unconditionally use kernel CR3 for do_nmi() */ 1253 /* %rax is saved above, so OK to clobber here */ 1254 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER 1255 /* If PCID enabled, NOFLUSH now and NOFLUSH on return */ 1256 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID 1257 pushq %rax 1258 /* mask off "user" bit of pgd address and 12 PCID bits: */ 1259 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax 1260 movq %rax, %cr3 12612: 1262#endif 1263 call do_nmi 1264 1265#ifdef CONFIG_PAGE_TABLE_ISOLATION 1266 /* 1267 * Unconditionally restore CR3. I know we return to 1268 * kernel code that needs user CR3, but do we ever return 1269 * to "user mode" where we need the kernel CR3? 1270 */ 1271 ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER 1272#endif 1273 1274 /* 1275 * Return back to user mode. We must *not* do the normal exit 1276 * work, because we don't want to enable interrupts. Do not 1277 * switch to user CR3: we might be going back to kernel code 1278 * that had a user CR3 set. 1279 */ 1280 SWAPGS 1281 jmp restore_c_regs_and_iret 1282 1283.Lnmi_from_kernel: 1284 /* 1285 * Here's what our stack frame will look like: 1286 * +---------------------------------------------------------+ 1287 * | original SS | 1288 * | original Return RSP | 1289 * | original RFLAGS | 1290 * | original CS | 1291 * | original RIP | 1292 * +---------------------------------------------------------+ 1293 * | temp storage for rdx | 1294 * +---------------------------------------------------------+ 1295 * | "NMI executing" variable | 1296 * +---------------------------------------------------------+ 1297 * | iret SS } Copied from "outermost" frame | 1298 * | iret Return RSP } on each loop iteration; overwritten | 1299 * | iret RFLAGS } by a nested NMI to force another | 1300 * | iret CS } iteration if needed. | 1301 * | iret RIP } | 1302 * +---------------------------------------------------------+ 1303 * | outermost SS } initialized in first_nmi; | 1304 * | outermost Return RSP } will not be changed before | 1305 * | outermost RFLAGS } NMI processing is done. | 1306 * | outermost CS } Copied to "iret" frame on each | 1307 * | outermost RIP } iteration. | 1308 * +---------------------------------------------------------+ 1309 * | pt_regs | 1310 * +---------------------------------------------------------+ 1311 * 1312 * The "original" frame is used by hardware. Before re-enabling 1313 * NMIs, we need to be done with it, and we need to leave enough 1314 * space for the asm code here. 1315 * 1316 * We return by executing IRET while RSP points to the "iret" frame. 1317 * That will either return for real or it will loop back into NMI 1318 * processing. 1319 * 1320 * The "outermost" frame is copied to the "iret" frame on each 1321 * iteration of the loop, so each iteration starts with the "iret" 1322 * frame pointing to the final return target. 1323 */ 1324 1325 /* 1326 * Determine whether we're a nested NMI. 1327 * 1328 * If we interrupted kernel code between repeat_nmi and 1329 * end_repeat_nmi, then we are a nested NMI. We must not 1330 * modify the "iret" frame because it's being written by 1331 * the outer NMI. That's okay; the outer NMI handler is 1332 * about to about to call do_nmi anyway, so we can just 1333 * resume the outer NMI. 1334 */ 1335 1336 movq $repeat_nmi, %rdx 1337 cmpq 8(%rsp), %rdx 1338 ja 1f 1339 movq $end_repeat_nmi, %rdx 1340 cmpq 8(%rsp), %rdx 1341 ja nested_nmi_out 13421: 1343 1344 /* 1345 * Now check "NMI executing". If it's set, then we're nested. 1346 * This will not detect if we interrupted an outer NMI just 1347 * before IRET. 1348 */ 1349 cmpl $1, -8(%rsp) 1350 je nested_nmi 1351 1352 /* 1353 * Now test if the previous stack was an NMI stack. This covers 1354 * the case where we interrupt an outer NMI after it clears 1355 * "NMI executing" but before IRET. We need to be careful, though: 1356 * there is one case in which RSP could point to the NMI stack 1357 * despite there being no NMI active: naughty userspace controls 1358 * RSP at the very beginning of the SYSCALL targets. We can 1359 * pull a fast one on naughty userspace, though: we program 1360 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1361 * if it controls the kernel's RSP. We set DF before we clear 1362 * "NMI executing". 1363 */ 1364 lea 6*8(%rsp), %rdx 1365 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1366 cmpq %rdx, 4*8(%rsp) 1367 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1368 ja first_nmi 1369 1370 subq $EXCEPTION_STKSZ, %rdx 1371 cmpq %rdx, 4*8(%rsp) 1372 /* If it is below the NMI stack, it is a normal NMI */ 1373 jb first_nmi 1374 1375 /* Ah, it is within the NMI stack. */ 1376 1377 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1378 jz first_nmi /* RSP was user controlled. */ 1379 1380 /* This is a nested NMI. */ 1381 1382nested_nmi: 1383 /* 1384 * Modify the "iret" frame to point to repeat_nmi, forcing another 1385 * iteration of NMI handling. 1386 */ 1387 subq $8, %rsp 1388 leaq -10*8(%rsp), %rdx 1389 pushq $__KERNEL_DS 1390 pushq %rdx 1391 pushfq 1392 pushq $__KERNEL_CS 1393 pushq $repeat_nmi 1394 1395 /* Put stack back */ 1396 addq $(6*8), %rsp 1397 1398nested_nmi_out: 1399 popq %rdx 1400 1401 /* We are returning to kernel mode, so this cannot result in a fault. */ 1402 INTERRUPT_RETURN 1403 1404first_nmi: 1405 /* Restore rdx. */ 1406 movq (%rsp), %rdx 1407 1408 /* Make room for "NMI executing". */ 1409 pushq $0 1410 1411 /* Leave room for the "iret" frame */ 1412 subq $(5*8), %rsp 1413 1414 /* Copy the "original" frame to the "outermost" frame */ 1415 .rept 5 1416 pushq 11*8(%rsp) 1417 .endr 1418 1419 /* Everything up to here is safe from nested NMIs */ 1420 1421#ifdef CONFIG_DEBUG_ENTRY 1422 /* 1423 * For ease of testing, unmask NMIs right away. Disabled by 1424 * default because IRET is very expensive. 1425 */ 1426 pushq $0 /* SS */ 1427 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1428 addq $8, (%rsp) /* Fix up RSP */ 1429 pushfq /* RFLAGS */ 1430 pushq $__KERNEL_CS /* CS */ 1431 pushq $1f /* RIP */ 1432 INTERRUPT_RETURN /* continues at repeat_nmi below */ 14331: 1434#endif 1435 1436repeat_nmi: 1437 /* 1438 * If there was a nested NMI, the first NMI's iret will return 1439 * here. But NMIs are still enabled and we can take another 1440 * nested NMI. The nested NMI checks the interrupted RIP to see 1441 * if it is between repeat_nmi and end_repeat_nmi, and if so 1442 * it will just return, as we are about to repeat an NMI anyway. 1443 * This makes it safe to copy to the stack frame that a nested 1444 * NMI will update. 1445 * 1446 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1447 * we're repeating an NMI, gsbase has the same value that it had on 1448 * the first iteration. paranoid_entry will load the kernel 1449 * gsbase if needed before we call do_nmi. "NMI executing" 1450 * is zero. 1451 */ 1452 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1453 1454 /* 1455 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1456 * here must not modify the "iret" frame while we're writing to 1457 * it or it will end up containing garbage. 1458 */ 1459 addq $(10*8), %rsp 1460 .rept 5 1461 pushq -6*8(%rsp) 1462 .endr 1463 subq $(5*8), %rsp 1464end_repeat_nmi: 1465 1466 /* 1467 * Everything below this point can be preempted by a nested NMI. 1468 * If this happens, then the inner NMI will change the "iret" 1469 * frame to point back to repeat_nmi. 1470 */ 1471 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1472 ALLOC_PT_GPREGS_ON_STACK 1473 1474 /* 1475 * Use the same approach as paranoid_entry to handle SWAPGS, but 1476 * without CR3 handling since we do that differently in NMIs. No 1477 * need to use paranoid_exit as we should not be calling schedule 1478 * in NMI context. Even with normal interrupts enabled. An NMI 1479 * should not be setting NEED_RESCHED or anything that normal 1480 * interrupts and exceptions might do. 1481 */ 1482 cld 1483 SAVE_C_REGS 1484 SAVE_EXTRA_REGS 1485 movl $1, %ebx 1486 movl $MSR_GS_BASE, %ecx 1487 rdmsr 1488 testl %edx, %edx 1489 js 1f /* negative -> in kernel */ 1490 SWAPGS 1491 xorl %ebx, %ebx 14921: 1493 movq %rsp, %rdi 1494 movq $-1, %rsi 1495#ifdef CONFIG_PAGE_TABLE_ISOLATION 1496 /* Unconditionally use kernel CR3 for do_nmi() */ 1497 /* %rax is saved above, so OK to clobber here */ 1498 ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER 1499 /* If PCID enabled, NOFLUSH now and NOFLUSH on return */ 1500 ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID 1501 pushq %rax 1502 /* mask off "user" bit of pgd address and 12 PCID bits: */ 1503 andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax 1504 movq %rax, %cr3 15052: 1506#endif 1507 1508 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ 1509 call do_nmi 1510 1511#ifdef CONFIG_PAGE_TABLE_ISOLATION 1512 /* 1513 * Unconditionally restore CR3. We might be returning to 1514 * kernel code that needs user CR3, like just just before 1515 * a sysret. 1516 */ 1517 ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER 1518#endif 1519 1520 testl %ebx, %ebx /* swapgs needed? */ 1521 jnz nmi_restore 1522nmi_swapgs: 1523 /* We fixed up CR3 above, so no need to switch it here */ 1524 SWAPGS_UNSAFE_STACK 1525nmi_restore: 1526 RESTORE_EXTRA_REGS 1527 RESTORE_C_REGS 1528 1529 /* Point RSP at the "iret" frame. */ 1530 REMOVE_PT_GPREGS_FROM_STACK 6*8 1531 1532 /* 1533 * Clear "NMI executing". Set DF first so that we can easily 1534 * distinguish the remaining code between here and IRET from 1535 * the SYSCALL entry and exit paths. On a native kernel, we 1536 * could just inspect RIP, but, on paravirt kernels, 1537 * INTERRUPT_RETURN can translate into a jump into a 1538 * hypercall page. 1539 */ 1540 std 1541 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1542 1543 /* 1544 * INTERRUPT_RETURN reads the "iret" frame and exits the NMI 1545 * stack in a single instruction. We are returning to kernel 1546 * mode, so this cannot result in a fault. 1547 */ 1548 INTERRUPT_RETURN 1549END(nmi) 1550 1551ENTRY(ignore_sysret) 1552 mov $-ENOSYS, %eax 1553 sysret 1554END(ignore_sysret) 1555 1556ENTRY(rewind_stack_do_exit) 1557 /* Prevent any naive code from trying to unwind to our caller. */ 1558 xorl %ebp, %ebp 1559 1560 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1561 leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp 1562 1563 call do_exit 15641: jmp 1b 1565END(rewind_stack_do_exit) 1566