1 #ifndef _RRUNNER_H_
2 #define _RRUNNER_H_
3
4 #include <linux/interrupt.h>
5
6 #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64))
7 #error "BITS_PER_LONG not defined or not valid"
8 #endif
9
10
11 struct rr_regs {
12
13 u32 pad0[16];
14
15 u32 HostCtrl;
16 u32 LocalCtrl;
17 u32 Pc;
18 u32 BrkPt;
19
20 /* Timer increments every 0.97 micro-seconds (unsigned int) */
21 u32 Timer_Hi;
22 u32 Timer;
23 u32 TimerRef;
24 u32 PciState;
25
26 u32 Event;
27 u32 MbEvent;
28
29 u32 WinBase;
30 u32 WinData;
31 u32 RX_state;
32 u32 TX_state;
33
34 u32 Overhead;
35 u32 ExtIo;
36
37 u32 DmaWriteHostHi;
38 u32 DmaWriteHostLo;
39
40 u32 pad1[2];
41
42 u32 DmaReadHostHi;
43 u32 DmaReadHostLo;
44
45 u32 pad2;
46
47 u32 DmaReadLen;
48 u32 DmaWriteState;
49
50 u32 DmaWriteLcl;
51 u32 DmaWriteIPchecksum;
52 u32 DmaWriteLen;
53 u32 DmaReadState;
54 u32 DmaReadLcl;
55 u32 DmaReadIPchecksum;
56 u32 pad3;
57
58 u32 RxBase;
59 u32 RxPrd;
60 u32 RxCon;
61
62 u32 pad4;
63
64 u32 TxBase;
65 u32 TxPrd;
66 u32 TxCon;
67
68 u32 pad5;
69
70 u32 RxIndPro;
71 u32 RxIndCon;
72 u32 RxIndRef;
73
74 u32 pad6;
75
76 u32 TxIndPro;
77 u32 TxIndCon;
78 u32 TxIndRef;
79
80 u32 pad7[17];
81
82 u32 DrCmndPro;
83 u32 DrCmndCon;
84 u32 DrCmndRef;
85
86 u32 pad8;
87
88 u32 DwCmndPro;
89 u32 DwCmndCon;
90 u32 DwCmndRef;
91
92 u32 AssistState;
93
94 u32 DrDataPro;
95 u32 DrDataCon;
96 u32 DrDataRef;
97
98 u32 pad9;
99
100 u32 DwDataPro;
101 u32 DwDataCon;
102 u32 DwDataRef;
103
104 u32 pad10[33];
105
106 u32 EvtCon;
107
108 u32 pad11[5];
109
110 u32 TxPi;
111 u32 IpRxPi;
112
113 u32 pad11a[8];
114
115 u32 CmdRing[16];
116
117 /* The ULA is in two registers the high order two bytes of the first
118 * word contain the RunCode features.
119 * ula0 res res byte0 byte1
120 * ula1 byte2 byte3 byte4 byte5
121 */
122 u32 Ula0;
123 u32 Ula1;
124
125 u32 RxRingHi;
126 u32 RxRingLo;
127
128 u32 InfoPtrHi;
129 u32 InfoPtrLo;
130
131 u32 Mode;
132
133 u32 ConRetry;
134 u32 ConRetryTmr;
135
136 u32 ConTmout;
137 u32 CtatTmr;
138
139 u32 MaxRxRng;
140
141 u32 IntrTmr;
142 u32 TxDataMvTimeout;
143 u32 RxDataMvTimeout;
144
145 u32 EvtPrd;
146 u32 TraceIdx;
147
148 u32 Fail1;
149 u32 Fail2;
150
151 u32 DrvPrm;
152
153 u32 FilterLA;
154
155 u32 FwRev;
156 u32 FwRes1;
157 u32 FwRes2;
158 u32 FwRes3;
159
160 u32 WriteDmaThresh;
161 u32 ReadDmaThresh;
162
163 u32 pad12[325];
164 u32 Window[512];
165 };
166
167 /*
168 * Host control register bits.
169 */
170
171 #define RR_INT 0x01
172 #define RR_CLEAR_INT 0x02
173 #define NO_SWAP 0x04000004
174 #define NO_SWAP1 0x00000004
175 #define PCI_RESET_NIC 0x08
176 #define HALT_NIC 0x10
177 #define SSTEP_NIC 0x20
178 #define MEM_READ_MULTI 0x40
179 #define NIC_HALTED 0x100
180 #define HALT_INST 0x200
181 #define PARITY_ERR 0x400
182 #define INVALID_INST_B 0x800
183 #define RR_REV_2 0x20000000
184 #define RR_REV_MASK 0xf0000000
185
186 /*
187 * Local control register bits.
188 */
189
190 #define INTA_STATE 0x01
191 #define CLEAR_INTA 0x02
192 #define FAST_EEPROM_ACCESS 0x08
193 #define ENABLE_EXTRA_SRAM 0x100
194 #define ENABLE_EXTRA_DESC 0x200
195 #define ENABLE_PARITY 0x400
196 #define FORCE_DMA_PARITY_ERROR 0x800
197 #define ENABLE_EEPROM_WRITE 0x1000
198 #define ENABLE_DATA_CACHE 0x2000
199 #define SRAM_LO_PARITY_ERR 0x4000
200 #define SRAM_HI_PARITY_ERR 0x8000
201
202 /*
203 * PCI state bits.
204 */
205
206 #define FORCE_PCI_RESET 0x01
207 #define PROVIDE_LENGTH 0x02
208 #define MASK_DMA_READ_MAX 0x1C
209 #define RBURST_DISABLE 0x00
210 #define RBURST_4 0x04
211 #define RBURST_16 0x08
212 #define RBURST_32 0x0C
213 #define RBURST_64 0x10
214 #define RBURST_128 0x14
215 #define RBURST_256 0x18
216 #define RBURST_1024 0x1C
217 #define MASK_DMA_WRITE_MAX 0xE0
218 #define WBURST_DISABLE 0x00
219 #define WBURST_4 0x20
220 #define WBURST_16 0x40
221 #define WBURST_32 0x60
222 #define WBURST_64 0x80
223 #define WBURST_128 0xa0
224 #define WBURST_256 0xc0
225 #define WBURST_1024 0xe0
226 #define MASK_MIN_DMA 0xFF00
227 #define FIFO_RETRY_ENABLE 0x10000
228
229 /*
230 * Event register
231 */
232
233 #define DMA_WRITE_DONE 0x10000
234 #define DMA_READ_DONE 0x20000
235 #define DMA_WRITE_ERR 0x40000
236 #define DMA_READ_ERR 0x80000
237
238 /*
239 * Receive state
240 *
241 * RoadRunner HIPPI Receive State Register controls and monitors the
242 * HIPPI receive interface in the NIC. Look at err bits when a HIPPI
243 * receive Error Event occurs.
244 */
245
246 #define ENABLE_NEW_CON 0x01
247 #define RESET_RECV 0x02
248 #define RECV_ALL 0x00
249 #define RECV_1K 0x20
250 #define RECV_2K 0x40
251 #define RECV_4K 0x60
252 #define RECV_8K 0x80
253 #define RECV_16K 0xa0
254 #define RECV_32K 0xc0
255 #define RECV_64K 0xe0
256
257 /*
258 * Transmit status.
259 */
260
261 #define ENA_XMIT 0x01
262 #define PERM_CON 0x02
263
264 /*
265 * DMA write state
266 */
267
268 #define RESET_DMA 0x01
269 #define NO_SWAP_DMA 0x02
270 #define DMA_ACTIVE 0x04
271 #define THRESH_MASK 0x1F
272 #define DMA_ERROR_MASK 0xff000000
273
274 /*
275 * Gooddies stored in the ULA registers.
276 */
277
278 #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */
279 #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */
280 #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */
281 #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */
282 #define LONG_TX_WHAT_BIT 0x00400000
283 #define LONG_RX_WHAT_BIT 0x00800000
284 #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */
285
286 /*
287 * Mode status
288 */
289
290 #define EVENT_OVFL 0x80000000
291 #define FATAL_ERR 0x40000000
292 #define LOOP_BACK 0x01
293 #define MODE_PH 0x02
294 #define MODE_FP 0x00
295 #define PTR64BIT 0x04
296 #define PTR32BIT 0x00
297 #define PTR_WD_SWAP 0x08
298 #define PTR_WD_NOSWAP 0x00
299 #define POST_WARN_EVENT 0x10
300 #define ERR_TERM 0x20
301 #define DIRECT_CONN 0x40
302 #define NO_NIC_WATCHDOG 0x80
303 #define SWAP_DATA 0x100
304 #define SWAP_CONTROL 0x200
305 #define NIC_HALT_ON_ERR 0x400
306 #define NIC_NO_RESTART 0x800
307 #define HALF_DUP_TX 0x1000
308 #define HALF_DUP_RX 0x2000
309
310
311 /*
312 * Error codes
313 */
314
315 /* Host Error Codes - values of fail1 */
316 #define ERR_UNKNOWN_MBOX 0x1001
317 #define ERR_UNKNOWN_CMD 0x1002
318 #define ERR_MAX_RING 0x1003
319 #define ERR_RING_CLOSED 0x1004
320 #define ERR_RING_OPEN 0x1005
321 /* Firmware internal errors */
322 #define ERR_EVENT_RING_FULL 0x01
323 #define ERR_DW_PEND_CMND_FULL 0x02
324 #define ERR_DR_PEND_CMND_FULL 0x03
325 #define ERR_DW_PEND_DATA_FULL 0x04
326 #define ERR_DR_PEND_DATA_FULL 0x05
327 #define ERR_ILLEGAL_JUMP 0x06
328 #define ERR_UNIMPLEMENTED 0x07
329 #define ERR_TX_INFO_FULL 0x08
330 #define ERR_RX_INFO_FULL 0x09
331 #define ERR_ILLEGAL_MODE 0x0A
332 #define ERR_MAIN_TIMEOUT 0x0B
333 #define ERR_EVENT_BITS 0x0C
334 #define ERR_UNPEND_FULL 0x0D
335 #define ERR_TIMER_QUEUE_FULL 0x0E
336 #define ERR_TIMER_QUEUE_EMPTY 0x0F
337 #define ERR_TIMER_NO_FREE 0x10
338 #define ERR_INTR_START 0x11
339 #define ERR_BAD_STARTUP 0x12
340 #define ERR_NO_PKT_END 0x13
341 #define ERR_HALTED_ON_ERR 0x14
342 /* Hardware NIC Errors */
343 #define ERR_WRITE_DMA 0x0101
344 #define ERR_READ_DMA 0x0102
345 #define ERR_EXT_SERIAL 0x0103
346 #define ERR_TX_INT_PARITY 0x0104
347
348
349 /*
350 * Event definitions
351 */
352
353 #define EVT_RING_ENTRIES 64
354 #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
355
356 struct event {
357 #ifdef __LITTLE_ENDIAN
358 u16 index;
359 u8 ring;
360 u8 code;
361 #else
362 u8 code;
363 u8 ring;
364 u16 index;
365 #endif
366 u32 timestamp;
367 };
368
369 /*
370 * General Events
371 */
372
373 #define E_NIC_UP 0x01
374 #define E_WATCHDOG 0x02
375
376 #define E_STAT_UPD 0x04
377 #define E_INVAL_CMD 0x05
378 #define E_SET_CMD_CONS 0x06
379 #define E_LINK_ON 0x07
380 #define E_LINK_OFF 0x08
381 #define E_INTERN_ERR 0x09
382 #define E_HOST_ERR 0x0A
383 #define E_STATS_UPDATE 0x0B
384 #define E_REJECTING 0x0C
385
386 /*
387 * Send Events
388 */
389 #define E_CON_REJ 0x13
390 #define E_CON_TMOUT 0x14
391 #define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */
392 #define E_DISC_ERR 0x16
393 #define E_INT_PRTY 0x17
394 #define E_TX_IDLE 0x18
395 #define E_TX_LINK_DROP 0x19
396 #define E_TX_INV_RNG 0x1A
397 #define E_TX_INV_BUF 0x1B
398 #define E_TX_INV_DSC 0x1C
399
400 /*
401 * Destination Events
402 */
403 /*
404 * General Receive events
405 */
406 #define E_VAL_RNG 0x20
407 #define E_RX_RNG_ENER 0x21
408 #define E_INV_RNG 0x22
409 #define E_RX_RNG_SPC 0x23
410 #define E_RX_RNG_OUT 0x24
411 #define E_PKT_DISCARD 0x25
412 #define E_INFO_EVT 0x27
413
414 /*
415 * Data corrupted events
416 */
417 #define E_RX_PAR_ERR 0x2B
418 #define E_RX_LLRC_ERR 0x2C
419 #define E_IP_CKSM_ERR 0x2D
420 #define E_DTA_CKSM_ERR 0x2E
421 #define E_SHT_BST 0x2F
422
423 /*
424 * Data lost events
425 */
426 #define E_LST_LNK_ERR 0x30
427 #define E_FLG_SYN_ERR 0x31
428 #define E_FRM_ERR 0x32
429 #define E_RX_IDLE 0x33
430 #define E_PKT_LN_ERR 0x34
431 #define E_STATE_ERR 0x35
432 #define E_UNEXP_DATA 0x3C
433
434 /*
435 * Fatal events
436 */
437 #define E_RX_INV_BUF 0x36
438 #define E_RX_INV_DSC 0x37
439 #define E_RNG_BLK 0x38
440
441 /*
442 * Warning events
443 */
444 #define E_RX_TO 0x39
445 #define E_BFR_SPC 0x3A
446 #define E_INV_ULP 0x3B
447
448 #define E_NOT_IMPLEMENTED 0x40
449
450
451 /*
452 * Commands
453 */
454
455 #define CMD_RING_ENTRIES 16
456
457 struct cmd {
458 #ifdef __LITTLE_ENDIAN
459 u16 index;
460 u8 ring;
461 u8 code;
462 #else
463 u8 code;
464 u8 ring;
465 u16 index;
466 #endif
467 };
468
469 #define C_START_FW 0x01
470 #define C_UPD_STAT 0x02
471 #define C_WATCHDOG 0x05
472 #define C_DEL_RNG 0x09
473 #define C_NEW_RNG 0x0A
474 #define C_CONN 0x0D
475
476
477 /*
478 * Mode bits
479 */
480
481 #define PACKET_BAD 0x01 /* Packet had link-layer error */
482 #define INTERRUPT 0x02
483 #define TX_IP_CKSUM 0x04
484 #define PACKET_END 0x08
485 #define PACKET_START 0x10
486 #define SAME_IFIELD 0x80
487
488
489 typedef struct {
490 #if (BITS_PER_LONG == 64)
491 u64 addrlo;
492 #else
493 u32 addrhi;
494 u32 addrlo;
495 #endif
496 } rraddr;
497
498
set_rraddr(rraddr * ra,dma_addr_t addr)499 static inline void set_rraddr(rraddr *ra, dma_addr_t addr)
500 {
501 unsigned long baddr = addr;
502 #if (BITS_PER_LONG == 64)
503 ra->addrlo = baddr;
504 #else
505 /* Don't bother setting zero every time */
506 ra->addrlo = baddr;
507 #endif
508 mb();
509 }
510
511
set_rxaddr(struct rr_regs __iomem * regs,volatile dma_addr_t addr)512 static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
513 {
514 unsigned long baddr = addr;
515 #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
516 writel(baddr & 0xffffffff, ®s->RxRingHi);
517 writel(baddr >> 32, ®s->RxRingLo);
518 #elif (BITS_PER_LONG == 64)
519 writel(baddr >> 32, ®s->RxRingHi);
520 writel(baddr & 0xffffffff, ®s->RxRingLo);
521 #else
522 writel(0, ®s->RxRingHi);
523 writel(baddr, ®s->RxRingLo);
524 #endif
525 mb();
526 }
527
528
set_infoaddr(struct rr_regs __iomem * regs,volatile dma_addr_t addr)529 static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
530 {
531 unsigned long baddr = addr;
532 #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
533 writel(baddr & 0xffffffff, ®s->InfoPtrHi);
534 writel(baddr >> 32, ®s->InfoPtrLo);
535 #elif (BITS_PER_LONG == 64)
536 writel(baddr >> 32, ®s->InfoPtrHi);
537 writel(baddr & 0xffffffff, ®s->InfoPtrLo);
538 #else
539 writel(0, ®s->InfoPtrHi);
540 writel(baddr, ®s->InfoPtrLo);
541 #endif
542 mb();
543 }
544
545
546 /*
547 * TX ring
548 */
549
550 #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
551 #define TX_RING_ENTRIES 32
552 #else
553 #define TX_RING_ENTRIES 16
554 #endif
555 #define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
556
557 struct tx_desc{
558 rraddr addr;
559 u32 res;
560 #ifdef __LITTLE_ENDIAN
561 u16 size;
562 u8 pad;
563 u8 mode;
564 #else
565 u8 mode;
566 u8 pad;
567 u16 size;
568 #endif
569 };
570
571
572 #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
573 #define RX_RING_ENTRIES 32
574 #else
575 #define RX_RING_ENTRIES 16
576 #endif
577 #define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc))
578
579 struct rx_desc{
580 rraddr addr;
581 u32 res;
582 #ifdef __LITTLE_ENDIAN
583 u16 size;
584 u8 pad;
585 u8 mode;
586 #else
587 u8 mode;
588 u8 pad;
589 u16 size;
590 #endif
591 };
592
593
594 /*
595 * ioctl's
596 */
597
598 #define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */
599 #define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */
600 #define SIOCRRID SIOCDEVPRIVATE+2 /* identify */
601
602
603 struct seg_hdr {
604 u32 seg_start;
605 u32 seg_len;
606 u32 seg_eestart;
607 };
608
609
610 #define EEPROM_BASE 0x80000000
611 #define EEPROM_WORDS 8192
612 #define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32))
613
614 struct eeprom_boot {
615 u32 key1;
616 u32 key2;
617 u32 sram_size;
618 struct seg_hdr loader;
619 u32 init_chksum;
620 u32 reserved1;
621 };
622
623 struct eeprom_manf {
624 u32 HeaderFmt;
625 u32 Firmware;
626 u32 BoardRevision;
627 u32 RoadrunnerRev;
628 char OpticsPart[8];
629 u32 OpticsRev;
630 u32 pad1;
631 char SramPart[8];
632 u32 SramRev;
633 u32 pad2;
634 char EepromPart[8];
635 u32 EepromRev;
636 u32 EepromSize;
637 char PalPart[8];
638 u32 PalRev;
639 u32 pad3;
640 char PalCodeFile[12];
641 u32 PalCodeRev;
642 char BoardULA[8];
643 char SerialNo[8];
644 char MfgDate[8];
645 char MfgTime[8];
646 char ModifyDate[8];
647 u32 ModCount;
648 u32 pad4[13];
649 };
650
651
652 struct eeprom_phase_info {
653 char phase1File[12];
654 u32 phase1Rev;
655 char phase1Date[8];
656 char phase2File[12];
657 u32 phase2Rev;
658 char phase2Date[8];
659 u32 reserved7[4];
660 };
661
662 struct eeprom_rncd_info {
663 u32 FwStart;
664 u32 FwRev;
665 char FwDate[8];
666 u32 AddrRunCodeSegs;
667 u32 FileNames;
668 char File[13][8];
669 };
670
671
672 /* Phase 1 region (starts are word offset 0x80) */
673 struct phase1_hdr{
674 u32 jump;
675 u32 noop;
676 struct seg_hdr phase2Seg;
677 };
678
679 struct eeprom {
680 struct eeprom_boot boot;
681 u32 pad1[8];
682 struct eeprom_manf manf;
683 struct eeprom_phase_info phase_info;
684 struct eeprom_rncd_info rncd_info;
685 u32 pad2[15];
686 u32 hdr_checksum;
687 struct phase1_hdr phase1;
688 };
689
690
691 struct rr_stats {
692 u32 NicTimeStamp;
693 u32 RngCreated;
694 u32 RngDeleted;
695 u32 IntrGen;
696 u32 NEvtOvfl;
697 u32 InvCmd;
698 u32 DmaReadErrs;
699 u32 DmaWriteErrs;
700 u32 StatUpdtT;
701 u32 StatUpdtC;
702 u32 WatchDog;
703 u32 Trace;
704
705 /* Serial HIPPI */
706 u32 LnkRdyEst;
707 u32 GLinkErr;
708 u32 AltFlgErr;
709 u32 OvhdBit8Sync;
710 u32 RmtSerPrtyErr;
711 u32 RmtParPrtyErr;
712 u32 RmtLoopBk;
713 u32 pad1;
714
715 /* HIPPI tx */
716 u32 ConEst;
717 u32 ConRejS;
718 u32 ConRetry;
719 u32 ConTmOut;
720 u32 SndConDiscon;
721 u32 SndParErr;
722 u32 PktSnt;
723 u32 pad2[2];
724 u32 ShFBstSnt;
725 u64 BytSent;
726 u32 TxTimeout;
727 u32 pad3[3];
728
729 /* HIPPI rx */
730 u32 ConAcc;
731 u32 ConRejdiPrty;
732 u32 ConRejd64b;
733 u32 ConRejdBuf;
734 u32 RxConDiscon;
735 u32 RxConNoData;
736 u32 PktRx;
737 u32 pad4[2];
738 u32 ShFBstRx;
739 u64 BytRx;
740 u32 RxParErr;
741 u32 RxLLRCerr;
742 u32 RxBstSZerr;
743 u32 RxStateErr;
744 u32 RxRdyErr;
745 u32 RxInvULP;
746 u32 RxSpcBuf;
747 u32 RxSpcDesc;
748 u32 RxRngSpc;
749 u32 RxRngFull;
750 u32 RxPktLenErr;
751 u32 RxCksmErr;
752 u32 RxPktDrp;
753 u32 RngLowSpc;
754 u32 RngDataClose;
755 u32 RxTimeout;
756 u32 RxIdle;
757 };
758
759
760 /*
761 * This struct is shared with the NIC firmware.
762 */
763 struct ring_ctrl {
764 rraddr rngptr;
765 #ifdef __LITTLE_ENDIAN
766 u16 entries;
767 u8 pad;
768 u8 entry_size;
769 u16 pi;
770 u16 mode;
771 #else
772 u8 entry_size;
773 u8 pad;
774 u16 entries;
775 u16 mode;
776 u16 pi;
777 #endif
778 };
779
780 struct rr_info {
781 union {
782 struct rr_stats stats;
783 u32 stati[128];
784 } s;
785 struct ring_ctrl evt_ctrl;
786 struct ring_ctrl cmd_ctrl;
787 struct ring_ctrl tx_ctrl;
788 u8 pad[464];
789 u8 trace[3072];
790 };
791
792 /*
793 * The linux structure for the RoadRunner.
794 *
795 * RX/TX descriptors are put first to make sure they are properly
796 * aligned and do not cross cache-line boundaries.
797 */
798
799 struct rr_private
800 {
801 struct rx_desc *rx_ring;
802 struct tx_desc *tx_ring;
803 struct event *evt_ring;
804 dma_addr_t tx_ring_dma;
805 dma_addr_t rx_ring_dma;
806 dma_addr_t evt_ring_dma;
807 /* Alignment ok ? */
808 struct sk_buff *rx_skbuff[RX_RING_ENTRIES];
809 struct sk_buff *tx_skbuff[TX_RING_ENTRIES];
810 struct rr_regs __iomem *regs; /* Register base */
811 struct ring_ctrl *rx_ctrl; /* Receive ring control */
812 struct rr_info *info; /* Shared info page */
813 dma_addr_t rx_ctrl_dma;
814 dma_addr_t info_dma;
815 spinlock_t lock;
816 struct timer_list timer;
817 u32 cur_rx, cur_cmd, cur_evt;
818 u32 dirty_rx, dirty_tx;
819 u32 tx_full;
820 u32 fw_rev;
821 volatile short fw_running;
822 struct pci_dev *pci_dev;
823 };
824
825
826 /*
827 * Prototypes
828 */
829 static int rr_init(struct net_device *dev);
830 static int rr_init1(struct net_device *dev);
831 static irqreturn_t rr_interrupt(int irq, void *dev_id);
832
833 static int rr_open(struct net_device *dev);
834 static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
835 struct net_device *dev);
836 static int rr_close(struct net_device *dev);
837 static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
838 static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
839 unsigned long offset,
840 unsigned char *buf,
841 unsigned long length);
842 static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset);
843 static int rr_load_firmware(struct net_device *dev);
844 static inline void rr_raz_tx(struct rr_private *, struct net_device *);
845 static inline void rr_raz_rx(struct rr_private *, struct net_device *);
846 #endif /* _RRUNNER_H_ */
847