1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL_WIFI_H__
27 #define __RTL_WIFI_H__
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sched.h>
32 #include <linux/firmware.h>
33 #include <linux/etherdevice.h>
34 #include <linux/vmalloc.h>
35 #include <linux/usb.h>
36 #include <net/mac80211.h>
37 #include <linux/completion.h>
38 #include "debug.h"
39
40 #define MASKBYTE0 0xff
41 #define MASKBYTE1 0xff00
42 #define MASKBYTE2 0xff0000
43 #define MASKBYTE3 0xff000000
44 #define MASKHWORD 0xffff0000
45 #define MASKLWORD 0x0000ffff
46 #define MASKDWORD 0xffffffff
47 #define MASK12BITS 0xfff
48 #define MASKH4BITS 0xf0000000
49 #define MASKOFDM_D 0xffc00000
50 #define MASKCCK 0x3f3f3f3f
51
52 #define MASK4BITS 0x0f
53 #define MASK20BITS 0xfffff
54 #define RFREG_OFFSET_MASK 0xfffff
55
56 #define MASKBYTE0 0xff
57 #define MASKBYTE1 0xff00
58 #define MASKBYTE2 0xff0000
59 #define MASKBYTE3 0xff000000
60 #define MASKHWORD 0xffff0000
61 #define MASKLWORD 0x0000ffff
62 #define MASKDWORD 0xffffffff
63 #define MASK12BITS 0xfff
64 #define MASKH4BITS 0xf0000000
65 #define MASKOFDM_D 0xffc00000
66 #define MASKCCK 0x3f3f3f3f
67
68 #define MASK4BITS 0x0f
69 #define MASK20BITS 0xfffff
70 #define RFREG_OFFSET_MASK 0xfffff
71
72 #define RF_CHANGE_BY_INIT 0
73 #define RF_CHANGE_BY_IPS BIT(28)
74 #define RF_CHANGE_BY_PS BIT(29)
75 #define RF_CHANGE_BY_HW BIT(30)
76 #define RF_CHANGE_BY_SW BIT(31)
77
78 #define IQK_ADDA_REG_NUM 16
79 #define IQK_MAC_REG_NUM 4
80 #define IQK_THRESHOLD 8
81
82 #define MAX_KEY_LEN 61
83 #define KEY_BUF_SIZE 5
84
85 /* QoS related. */
86 /*aci: 0x00 Best Effort*/
87 /*aci: 0x01 Background*/
88 /*aci: 0x10 Video*/
89 /*aci: 0x11 Voice*/
90 /*Max: define total number.*/
91 #define AC0_BE 0
92 #define AC1_BK 1
93 #define AC2_VI 2
94 #define AC3_VO 3
95 #define AC_MAX 4
96 #define QOS_QUEUE_NUM 4
97 #define RTL_MAC80211_NUM_QUEUE 5
98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
99 #define RTL_USB_MAX_RX_COUNT 100
100 #define QBSS_LOAD_SIZE 5
101 #define MAX_WMMELE_LENGTH 64
102 #define ASPM_L1_LATENCY 7
103
104 #define TOTAL_CAM_ENTRY 32
105
106 /*slot time for 11g. */
107 #define RTL_SLOT_TIME_9 9
108 #define RTL_SLOT_TIME_20 20
109
110 /*related to tcp/ip. */
111 #define SNAP_SIZE 6
112 #define PROTOC_TYPE_SIZE 2
113
114 /*related with 802.11 frame*/
115 #define MAC80211_3ADDR_LEN 24
116 #define MAC80211_4ADDR_LEN 30
117
118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
119 #define CHANNEL_MAX_NUMBER_2G 14
120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
121 *"phy_GetChnlGroup8812A" and
122 * "Hal_ReadTxPowerInfo8812A"
123 */
124 #define CHANNEL_MAX_NUMBER_5G_80M 7
125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
126 #define MAX_PG_GROUP 13
127 #define CHANNEL_GROUP_MAX_2G 3
128 #define CHANNEL_GROUP_IDX_5GL 3
129 #define CHANNEL_GROUP_IDX_5GM 6
130 #define CHANNEL_GROUP_IDX_5GH 9
131 #define CHANNEL_GROUP_MAX_5G 9
132 #define CHANNEL_MAX_NUMBER_2G 14
133 #define AVG_THERMAL_NUM 8
134 #define AVG_THERMAL_NUM_88E 4
135 #define AVG_THERMAL_NUM_8723BE 4
136 #define MAX_TID_COUNT 9
137
138 /* for early mode */
139 #define FCS_LEN 4
140 #define EM_HDR_LEN 8
141
142 enum rtl8192c_h2c_cmd {
143 H2C_AP_OFFLOAD = 0,
144 H2C_SETPWRMODE = 1,
145 H2C_JOINBSSRPT = 2,
146 H2C_RSVDPAGE = 3,
147 H2C_RSSI_REPORT = 5,
148 H2C_RA_MASK = 6,
149 H2C_MACID_PS_MODE = 7,
150 H2C_P2P_PS_OFFLOAD = 8,
151 H2C_MAC_MODE_SEL = 9,
152 H2C_PWRM = 15,
153 H2C_P2P_PS_CTW_CMD = 24,
154 MAX_H2CCMD
155 };
156
157 #define MAX_TX_COUNT 4
158 #define MAX_REGULATION_NUM 4
159 #define MAX_RF_PATH_NUM 4
160 #define MAX_RATE_SECTION_NUM 6
161 #define MAX_2_4G_BANDWITH_NUM 4
162 #define MAX_5G_BANDWITH_NUM 4
163 #define MAX_RF_PATH 4
164 #define MAX_CHNL_GROUP_24G 6
165 #define MAX_CHNL_GROUP_5G 14
166
167 #define TX_PWR_BY_RATE_NUM_BAND 2
168 #define TX_PWR_BY_RATE_NUM_RF 4
169 #define TX_PWR_BY_RATE_NUM_SECTION 12
170 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
171 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
172
173 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
174
175 #define DEL_SW_IDX_SZ 30
176 #define BAND_NUM 3
177
178 /* For now, it's just for 8192ee
179 * but not OK yet, keep it 0
180 */
181 #define DMA_IS_64BIT 0
182 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
183
184 enum rf_tx_num {
185 RF_1TX = 0,
186 RF_2TX,
187 RF_MAX_TX_NUM,
188 RF_TX_NUM_NONIMPLEMENT,
189 };
190
191 #define PACKET_NORMAL 0
192 #define PACKET_DHCP 1
193 #define PACKET_ARP 2
194 #define PACKET_EAPOL 3
195
196 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
197 #define RSVD_WOL_PATTERN_NUM 1
198 #define WKFMCAM_ADDR_NUM 6
199 #define WKFMCAM_SIZE 24
200
201 #define MAX_WOL_BIT_MASK_SIZE 16
202 /* MIN LEN keeps 13 here */
203 #define MIN_WOL_PATTERN_SIZE 13
204 #define MAX_WOL_PATTERN_SIZE 128
205
206 #define WAKE_ON_MAGIC_PACKET BIT(0)
207 #define WAKE_ON_PATTERN_MATCH BIT(1)
208
209 #define WOL_REASON_PTK_UPDATE BIT(0)
210 #define WOL_REASON_GTK_UPDATE BIT(1)
211 #define WOL_REASON_DISASSOC BIT(2)
212 #define WOL_REASON_DEAUTH BIT(3)
213 #define WOL_REASON_AP_LOST BIT(4)
214 #define WOL_REASON_MAGIC_PKT BIT(5)
215 #define WOL_REASON_UNICAST_PKT BIT(6)
216 #define WOL_REASON_PATTERN_PKT BIT(7)
217 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
218 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
219 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
220
221 struct rtlwifi_firmware_header {
222 __le16 signature;
223 u8 category;
224 u8 function;
225 __le16 version;
226 u8 subversion;
227 u8 rsvd1;
228 u8 month;
229 u8 date;
230 u8 hour;
231 u8 minute;
232 __le16 ramcodeSize;
233 __le16 rsvd2;
234 __le32 svnindex;
235 __le32 rsvd3;
236 __le32 rsvd4;
237 __le32 rsvd5;
238 };
239
240 struct txpower_info_2g {
241 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
242 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
243 /*If only one tx, only BW20 and OFDM are used.*/
244 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
245 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
250 };
251
252 struct txpower_info_5g {
253 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
254 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
255 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
256 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 };
261
262 enum rate_section {
263 CCK = 0,
264 OFDM,
265 HT_MCS0_MCS7,
266 HT_MCS8_MCS15,
267 VHT_1SSMCS0_1SSMCS9,
268 VHT_2SSMCS0_2SSMCS9,
269 };
270
271 enum intf_type {
272 INTF_PCI = 0,
273 INTF_USB = 1,
274 };
275
276 enum radio_path {
277 RF90_PATH_A = 0,
278 RF90_PATH_B = 1,
279 RF90_PATH_C = 2,
280 RF90_PATH_D = 3,
281 };
282
283 enum regulation_txpwr_lmt {
284 TXPWR_LMT_FCC = 0,
285 TXPWR_LMT_MKK = 1,
286 TXPWR_LMT_ETSI = 2,
287 TXPWR_LMT_WW = 3,
288
289 TXPWR_LMT_MAX_REGULATION_NUM = 4
290 };
291
292 enum rt_eeprom_type {
293 EEPROM_93C46,
294 EEPROM_93C56,
295 EEPROM_BOOT_EFUSE,
296 };
297
298 enum ttl_status {
299 RTL_STATUS_INTERFACE_START = 0,
300 };
301
302 enum hardware_type {
303 HARDWARE_TYPE_RTL8192E,
304 HARDWARE_TYPE_RTL8192U,
305 HARDWARE_TYPE_RTL8192SE,
306 HARDWARE_TYPE_RTL8192SU,
307 HARDWARE_TYPE_RTL8192CE,
308 HARDWARE_TYPE_RTL8192CU,
309 HARDWARE_TYPE_RTL8192DE,
310 HARDWARE_TYPE_RTL8192DU,
311 HARDWARE_TYPE_RTL8723AE,
312 HARDWARE_TYPE_RTL8723U,
313 HARDWARE_TYPE_RTL8188EE,
314 HARDWARE_TYPE_RTL8723BE,
315 HARDWARE_TYPE_RTL8192EE,
316 HARDWARE_TYPE_RTL8821AE,
317 HARDWARE_TYPE_RTL8812AE,
318
319 /* keep it last */
320 HARDWARE_TYPE_NUM
321 };
322
323 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
324 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
325 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
326 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
327 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
328 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
329 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
330 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
331 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
332 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
333 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
334 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
335 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
336 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
337 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
338 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
339 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
340 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
341 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
342 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
343 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
344 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
345 #define IS_HARDWARE_TYPE_8723(rtlhal) \
346 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
347
348 #define RX_HAL_IS_CCK_RATE(rxmcs) \
349 ((rxmcs) == DESC_RATE1M || \
350 (rxmcs) == DESC_RATE2M || \
351 (rxmcs) == DESC_RATE5_5M || \
352 (rxmcs) == DESC_RATE11M)
353
354 enum scan_operation_backup_opt {
355 SCAN_OPT_BACKUP = 0,
356 SCAN_OPT_BACKUP_BAND0 = 0,
357 SCAN_OPT_BACKUP_BAND1,
358 SCAN_OPT_RESTORE,
359 SCAN_OPT_MAX
360 };
361
362 /*RF state.*/
363 enum rf_pwrstate {
364 ERFON,
365 ERFSLEEP,
366 ERFOFF
367 };
368
369 struct bb_reg_def {
370 u32 rfintfs;
371 u32 rfintfi;
372 u32 rfintfo;
373 u32 rfintfe;
374 u32 rf3wire_offset;
375 u32 rflssi_select;
376 u32 rftxgain_stage;
377 u32 rfhssi_para1;
378 u32 rfhssi_para2;
379 u32 rfsw_ctrl;
380 u32 rfagc_control1;
381 u32 rfagc_control2;
382 u32 rfrxiq_imbal;
383 u32 rfrx_afe;
384 u32 rftxiq_imbal;
385 u32 rftx_afe;
386 u32 rf_rb; /* rflssi_readback */
387 u32 rf_rbpi; /* rflssi_readbackpi */
388 };
389
390 enum io_type {
391 IO_CMD_PAUSE_DM_BY_SCAN = 0,
392 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
393 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
394 IO_CMD_RESUME_DM_BY_SCAN = 2,
395 };
396
397 enum hw_variables {
398 HW_VAR_ETHER_ADDR = 0x0,
399 HW_VAR_MULTICAST_REG = 0x1,
400 HW_VAR_BASIC_RATE = 0x2,
401 HW_VAR_BSSID = 0x3,
402 HW_VAR_MEDIA_STATUS= 0x4,
403 HW_VAR_SECURITY_CONF= 0x5,
404 HW_VAR_BEACON_INTERVAL = 0x6,
405 HW_VAR_ATIM_WINDOW = 0x7,
406 HW_VAR_LISTEN_INTERVAL = 0x8,
407 HW_VAR_CS_COUNTER = 0x9,
408 HW_VAR_DEFAULTKEY0 = 0xa,
409 HW_VAR_DEFAULTKEY1 = 0xb,
410 HW_VAR_DEFAULTKEY2 = 0xc,
411 HW_VAR_DEFAULTKEY3 = 0xd,
412 HW_VAR_SIFS = 0xe,
413 HW_VAR_R2T_SIFS = 0xf,
414 HW_VAR_DIFS = 0x10,
415 HW_VAR_EIFS = 0x11,
416 HW_VAR_SLOT_TIME = 0x12,
417 HW_VAR_ACK_PREAMBLE = 0x13,
418 HW_VAR_CW_CONFIG = 0x14,
419 HW_VAR_CW_VALUES = 0x15,
420 HW_VAR_RATE_FALLBACK_CONTROL= 0x16,
421 HW_VAR_CONTENTION_WINDOW = 0x17,
422 HW_VAR_RETRY_COUNT = 0x18,
423 HW_VAR_TR_SWITCH = 0x19,
424 HW_VAR_COMMAND = 0x1a,
425 HW_VAR_WPA_CONFIG = 0x1b,
426 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
427 HW_VAR_SHORTGI_DENSITY = 0x1d,
428 HW_VAR_AMPDU_FACTOR = 0x1e,
429 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
430 HW_VAR_AC_PARAM = 0x20,
431 HW_VAR_ACM_CTRL = 0x21,
432 HW_VAR_DIS_Req_Qsize = 0x22,
433 HW_VAR_CCX_CHNL_LOAD = 0x23,
434 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
435 HW_VAR_CCX_CLM_NHM = 0x25,
436 HW_VAR_TxOPLimit = 0x26,
437 HW_VAR_TURBO_MODE = 0x27,
438 HW_VAR_RF_STATE = 0x28,
439 HW_VAR_RF_OFF_BY_HW = 0x29,
440 HW_VAR_BUS_SPEED = 0x2a,
441 HW_VAR_SET_DEV_POWER = 0x2b,
442
443 HW_VAR_RCR = 0x2c,
444 HW_VAR_RATR_0 = 0x2d,
445 HW_VAR_RRSR = 0x2e,
446 HW_VAR_CPU_RST = 0x2f,
447 HW_VAR_CHECK_BSSID = 0x30,
448 HW_VAR_LBK_MODE = 0x31,
449 HW_VAR_AES_11N_FIX = 0x32,
450 HW_VAR_USB_RX_AGGR = 0x33,
451 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
452 HW_VAR_RETRY_LIMIT = 0x35,
453 HW_VAR_INIT_TX_RATE = 0x36,
454 HW_VAR_TX_RATE_REG = 0x37,
455 HW_VAR_EFUSE_USAGE = 0x38,
456 HW_VAR_EFUSE_BYTES = 0x39,
457 HW_VAR_AUTOLOAD_STATUS = 0x3a,
458 HW_VAR_RF_2R_DISABLE = 0x3b,
459 HW_VAR_SET_RPWM = 0x3c,
460 HW_VAR_H2C_FW_PWRMODE = 0x3d,
461 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
462 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
463 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
464 HW_VAR_FW_PSMODE_STATUS = 0x41,
465 HW_VAR_INIT_RTS_RATE = 0x42,
466 HW_VAR_RESUME_CLK_ON = 0x43,
467 HW_VAR_FW_LPS_ACTION = 0x44,
468 HW_VAR_1X1_RECV_COMBINE = 0x45,
469 HW_VAR_STOP_SEND_BEACON = 0x46,
470 HW_VAR_TSF_TIMER = 0x47,
471 HW_VAR_IO_CMD = 0x48,
472
473 HW_VAR_RF_RECOVERY = 0x49,
474 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
475 HW_VAR_WF_MASK = 0x4b,
476 HW_VAR_WF_CRC = 0x4c,
477 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
478 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
479 HW_VAR_RESET_WFCRC = 0x4f,
480
481 HW_VAR_HANDLE_FW_C2H = 0x50,
482 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
483 HW_VAR_AID = 0x52,
484 HW_VAR_HW_SEQ_ENABLE = 0x53,
485 HW_VAR_CORRECT_TSF = 0x54,
486 HW_VAR_BCN_VALID = 0x55,
487 HW_VAR_FWLPS_RF_ON = 0x56,
488 HW_VAR_DUAL_TSF_RST = 0x57,
489 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58,
490 HW_VAR_INT_MIGRATION = 0x59,
491 HW_VAR_INT_AC = 0x5a,
492 HW_VAR_RF_TIMING = 0x5b,
493
494 HAL_DEF_WOWLAN = 0x5c,
495 HW_VAR_MRC = 0x5d,
496 HW_VAR_KEEP_ALIVE = 0x5e,
497 HW_VAR_NAV_UPPER = 0x5f,
498
499 HW_VAR_MGT_FILTER = 0x60,
500 HW_VAR_CTRL_FILTER = 0x61,
501 HW_VAR_DATA_FILTER = 0x62,
502 };
503
504 enum rt_media_status {
505 RT_MEDIA_DISCONNECT = 0,
506 RT_MEDIA_CONNECT = 1
507 };
508
509 enum rt_oem_id {
510 RT_CID_DEFAULT = 0,
511 RT_CID_8187_ALPHA0 = 1,
512 RT_CID_8187_SERCOMM_PS = 2,
513 RT_CID_8187_HW_LED = 3,
514 RT_CID_8187_NETGEAR = 4,
515 RT_CID_WHQL = 5,
516 RT_CID_819X_CAMEO = 6,
517 RT_CID_819X_RUNTOP = 7,
518 RT_CID_819X_SENAO = 8,
519 RT_CID_TOSHIBA = 9,
520 RT_CID_819X_NETCORE = 10,
521 RT_CID_NETTRONIX = 11,
522 RT_CID_DLINK = 12,
523 RT_CID_PRONET = 13,
524 RT_CID_COREGA = 14,
525 RT_CID_819X_ALPHA = 15,
526 RT_CID_819X_SITECOM = 16,
527 RT_CID_CCX = 17,
528 RT_CID_819X_LENOVO = 18,
529 RT_CID_819X_QMI = 19,
530 RT_CID_819X_EDIMAX_BELKIN = 20,
531 RT_CID_819X_SERCOMM_BELKIN = 21,
532 RT_CID_819X_CAMEO1 = 22,
533 RT_CID_819X_MSI = 23,
534 RT_CID_819X_ACER = 24,
535 RT_CID_819X_HP = 27,
536 RT_CID_819X_CLEVO = 28,
537 RT_CID_819X_ARCADYAN_BELKIN = 29,
538 RT_CID_819X_SAMSUNG = 30,
539 RT_CID_819X_WNC_COREGA = 31,
540 RT_CID_819X_FOXCOON = 32,
541 RT_CID_819X_DELL = 33,
542 RT_CID_819X_PRONETS = 34,
543 RT_CID_819X_EDIMAX_ASUS = 35,
544 RT_CID_NETGEAR = 36,
545 RT_CID_PLANEX = 37,
546 RT_CID_CC_C = 38,
547 };
548
549 enum hw_descs {
550 HW_DESC_OWN,
551 HW_DESC_RXOWN,
552 HW_DESC_TX_NEXTDESC_ADDR,
553 HW_DESC_TXBUFF_ADDR,
554 HW_DESC_RXBUFF_ADDR,
555 HW_DESC_RXPKT_LEN,
556 HW_DESC_RXERO,
557 HW_DESC_RX_PREPARE,
558 };
559
560 enum prime_sc {
561 PRIME_CHNL_OFFSET_DONT_CARE = 0,
562 PRIME_CHNL_OFFSET_LOWER = 1,
563 PRIME_CHNL_OFFSET_UPPER = 2,
564 };
565
566 enum rf_type {
567 RF_1T1R = 0,
568 RF_1T2R = 1,
569 RF_2T2R = 2,
570 RF_2T2R_GREEN = 3,
571 };
572
573 enum ht_channel_width {
574 HT_CHANNEL_WIDTH_20 = 0,
575 HT_CHANNEL_WIDTH_20_40 = 1,
576 HT_CHANNEL_WIDTH_80 = 2,
577 };
578
579 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
580 Cipher Suites Encryption Algorithms */
581 enum rt_enc_alg {
582 NO_ENCRYPTION = 0,
583 WEP40_ENCRYPTION = 1,
584 TKIP_ENCRYPTION = 2,
585 RSERVED_ENCRYPTION = 3,
586 AESCCMP_ENCRYPTION = 4,
587 WEP104_ENCRYPTION = 5,
588 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
589 };
590
591 enum rtl_hal_state {
592 _HAL_STATE_STOP = 0,
593 _HAL_STATE_START = 1,
594 };
595
596 enum rtl_desc92_rate {
597 DESC_RATE1M = 0x00,
598 DESC_RATE2M = 0x01,
599 DESC_RATE5_5M = 0x02,
600 DESC_RATE11M = 0x03,
601
602 DESC_RATE6M = 0x04,
603 DESC_RATE9M = 0x05,
604 DESC_RATE12M = 0x06,
605 DESC_RATE18M = 0x07,
606 DESC_RATE24M = 0x08,
607 DESC_RATE36M = 0x09,
608 DESC_RATE48M = 0x0a,
609 DESC_RATE54M = 0x0b,
610
611 DESC_RATEMCS0 = 0x0c,
612 DESC_RATEMCS1 = 0x0d,
613 DESC_RATEMCS2 = 0x0e,
614 DESC_RATEMCS3 = 0x0f,
615 DESC_RATEMCS4 = 0x10,
616 DESC_RATEMCS5 = 0x11,
617 DESC_RATEMCS6 = 0x12,
618 DESC_RATEMCS7 = 0x13,
619 DESC_RATEMCS8 = 0x14,
620 DESC_RATEMCS9 = 0x15,
621 DESC_RATEMCS10 = 0x16,
622 DESC_RATEMCS11 = 0x17,
623 DESC_RATEMCS12 = 0x18,
624 DESC_RATEMCS13 = 0x19,
625 DESC_RATEMCS14 = 0x1a,
626 DESC_RATEMCS15 = 0x1b,
627 DESC_RATEMCS15_SG = 0x1c,
628 DESC_RATEMCS32 = 0x20,
629
630 DESC_RATEVHT1SS_MCS0 = 0x2c,
631 DESC_RATEVHT1SS_MCS1 = 0x2d,
632 DESC_RATEVHT1SS_MCS2 = 0x2e,
633 DESC_RATEVHT1SS_MCS3 = 0x2f,
634 DESC_RATEVHT1SS_MCS4 = 0x30,
635 DESC_RATEVHT1SS_MCS5 = 0x31,
636 DESC_RATEVHT1SS_MCS6 = 0x32,
637 DESC_RATEVHT1SS_MCS7 = 0x33,
638 DESC_RATEVHT1SS_MCS8 = 0x34,
639 DESC_RATEVHT1SS_MCS9 = 0x35,
640 DESC_RATEVHT2SS_MCS0 = 0x36,
641 DESC_RATEVHT2SS_MCS1 = 0x37,
642 DESC_RATEVHT2SS_MCS2 = 0x38,
643 DESC_RATEVHT2SS_MCS3 = 0x39,
644 DESC_RATEVHT2SS_MCS4 = 0x3a,
645 DESC_RATEVHT2SS_MCS5 = 0x3b,
646 DESC_RATEVHT2SS_MCS6 = 0x3c,
647 DESC_RATEVHT2SS_MCS7 = 0x3d,
648 DESC_RATEVHT2SS_MCS8 = 0x3e,
649 DESC_RATEVHT2SS_MCS9 = 0x3f,
650 };
651
652 enum rtl_var_map {
653 /*reg map */
654 SYS_ISO_CTRL = 0,
655 SYS_FUNC_EN,
656 SYS_CLK,
657 MAC_RCR_AM,
658 MAC_RCR_AB,
659 MAC_RCR_ACRC32,
660 MAC_RCR_ACF,
661 MAC_RCR_AAP,
662 MAC_HIMR,
663 MAC_HIMRE,
664 MAC_HSISR,
665
666 /*efuse map */
667 EFUSE_TEST,
668 EFUSE_CTRL,
669 EFUSE_CLK,
670 EFUSE_CLK_CTRL,
671 EFUSE_PWC_EV12V,
672 EFUSE_FEN_ELDR,
673 EFUSE_LOADER_CLK_EN,
674 EFUSE_ANA8M,
675 EFUSE_HWSET_MAX_SIZE,
676 EFUSE_MAX_SECTION_MAP,
677 EFUSE_REAL_CONTENT_SIZE,
678 EFUSE_OOB_PROTECT_BYTES_LEN,
679 EFUSE_ACCESS,
680
681 /*CAM map */
682 RWCAM,
683 WCAMI,
684 RCAMO,
685 CAMDBG,
686 SECR,
687 SEC_CAM_NONE,
688 SEC_CAM_WEP40,
689 SEC_CAM_TKIP,
690 SEC_CAM_AES,
691 SEC_CAM_WEP104,
692
693 /*IMR map */
694 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
695 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
696 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
697 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
698 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
699 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
700 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
701 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
702 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
703 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
704 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
705 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
706 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
707 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
708 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
709 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
710 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
711 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
712 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
713 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
714 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
715 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
716 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
717 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
718 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
719 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
720 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
721 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
722 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
723 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
724 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
725 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
726 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
727 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
728 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
729 * RTL_IMR_TBDER) */
730 RTL_IMR_C2HCMD, /*fw interrupt*/
731
732 /*CCK Rates, TxHT = 0 */
733 RTL_RC_CCK_RATE1M,
734 RTL_RC_CCK_RATE2M,
735 RTL_RC_CCK_RATE5_5M,
736 RTL_RC_CCK_RATE11M,
737
738 /*OFDM Rates, TxHT = 0 */
739 RTL_RC_OFDM_RATE6M,
740 RTL_RC_OFDM_RATE9M,
741 RTL_RC_OFDM_RATE12M,
742 RTL_RC_OFDM_RATE18M,
743 RTL_RC_OFDM_RATE24M,
744 RTL_RC_OFDM_RATE36M,
745 RTL_RC_OFDM_RATE48M,
746 RTL_RC_OFDM_RATE54M,
747
748 RTL_RC_HT_RATEMCS7,
749 RTL_RC_HT_RATEMCS15,
750
751 RTL_RC_VHT_RATE_1SS_MCS7,
752 RTL_RC_VHT_RATE_1SS_MCS8,
753 RTL_RC_VHT_RATE_1SS_MCS9,
754 RTL_RC_VHT_RATE_2SS_MCS7,
755 RTL_RC_VHT_RATE_2SS_MCS8,
756 RTL_RC_VHT_RATE_2SS_MCS9,
757
758 /*keep it last */
759 RTL_VAR_MAP_MAX,
760 };
761
762 /*Firmware PS mode for control LPS.*/
763 enum _fw_ps_mode {
764 FW_PS_ACTIVE_MODE = 0,
765 FW_PS_MIN_MODE = 1,
766 FW_PS_MAX_MODE = 2,
767 FW_PS_DTIM_MODE = 3,
768 FW_PS_VOIP_MODE = 4,
769 FW_PS_UAPSD_WMM_MODE = 5,
770 FW_PS_UAPSD_MODE = 6,
771 FW_PS_IBSS_MODE = 7,
772 FW_PS_WWLAN_MODE = 8,
773 FW_PS_PM_Radio_Off = 9,
774 FW_PS_PM_Card_Disable = 10,
775 };
776
777 enum rt_psmode {
778 EACTIVE, /*Active/Continuous access. */
779 EMAXPS, /*Max power save mode. */
780 EFASTPS, /*Fast power save mode. */
781 EAUTOPS, /*Auto power save mode. */
782 };
783
784 /*LED related.*/
785 enum led_ctl_mode {
786 LED_CTL_POWER_ON = 1,
787 LED_CTL_LINK = 2,
788 LED_CTL_NO_LINK = 3,
789 LED_CTL_TX = 4,
790 LED_CTL_RX = 5,
791 LED_CTL_SITE_SURVEY = 6,
792 LED_CTL_POWER_OFF = 7,
793 LED_CTL_START_TO_LINK = 8,
794 LED_CTL_START_WPS = 9,
795 LED_CTL_STOP_WPS = 10,
796 };
797
798 enum rtl_led_pin {
799 LED_PIN_GPIO0,
800 LED_PIN_LED0,
801 LED_PIN_LED1,
802 LED_PIN_LED2
803 };
804
805 /*QoS related.*/
806 /*acm implementation method.*/
807 enum acm_method {
808 eAcmWay0_SwAndHw = 0,
809 eAcmWay1_HW = 1,
810 EACMWAY2_SW = 2,
811 };
812
813 enum macphy_mode {
814 SINGLEMAC_SINGLEPHY = 0,
815 DUALMAC_DUALPHY,
816 DUALMAC_SINGLEPHY,
817 };
818
819 enum band_type {
820 BAND_ON_2_4G = 0,
821 BAND_ON_5G,
822 BAND_ON_BOTH,
823 BANDMAX
824 };
825
826 /*aci/aifsn Field.
827 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
828 union aci_aifsn {
829 u8 char_data;
830
831 struct {
832 u8 aifsn:4;
833 u8 acm:1;
834 u8 aci:2;
835 u8 reserved:1;
836 } f; /* Field */
837 };
838
839 /*mlme related.*/
840 enum wireless_mode {
841 WIRELESS_MODE_UNKNOWN = 0x00,
842 WIRELESS_MODE_A = 0x01,
843 WIRELESS_MODE_B = 0x02,
844 WIRELESS_MODE_G = 0x04,
845 WIRELESS_MODE_AUTO = 0x08,
846 WIRELESS_MODE_N_24G = 0x10,
847 WIRELESS_MODE_N_5G = 0x20,
848 WIRELESS_MODE_AC_5G = 0x40,
849 WIRELESS_MODE_AC_24G = 0x80,
850 WIRELESS_MODE_AC_ONLY = 0x100,
851 WIRELESS_MODE_MAX = 0x800
852 };
853
854 #define IS_WIRELESS_MODE_A(wirelessmode) \
855 (wirelessmode == WIRELESS_MODE_A)
856 #define IS_WIRELESS_MODE_B(wirelessmode) \
857 (wirelessmode == WIRELESS_MODE_B)
858 #define IS_WIRELESS_MODE_G(wirelessmode) \
859 (wirelessmode == WIRELESS_MODE_G)
860 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
861 (wirelessmode == WIRELESS_MODE_N_24G)
862 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
863 (wirelessmode == WIRELESS_MODE_N_5G)
864
865 enum ratr_table_mode {
866 RATR_INX_WIRELESS_NGB = 0,
867 RATR_INX_WIRELESS_NG = 1,
868 RATR_INX_WIRELESS_NB = 2,
869 RATR_INX_WIRELESS_N = 3,
870 RATR_INX_WIRELESS_GB = 4,
871 RATR_INX_WIRELESS_G = 5,
872 RATR_INX_WIRELESS_B = 6,
873 RATR_INX_WIRELESS_MC = 7,
874 RATR_INX_WIRELESS_A = 8,
875 RATR_INX_WIRELESS_AC_5N = 8,
876 RATR_INX_WIRELESS_AC_24N = 9,
877 };
878
879 enum rtl_link_state {
880 MAC80211_NOLINK = 0,
881 MAC80211_LINKING = 1,
882 MAC80211_LINKED = 2,
883 MAC80211_LINKED_SCANNING = 3,
884 };
885
886 enum act_category {
887 ACT_CAT_QOS = 1,
888 ACT_CAT_DLS = 2,
889 ACT_CAT_BA = 3,
890 ACT_CAT_HT = 7,
891 ACT_CAT_WMM = 17,
892 };
893
894 enum ba_action {
895 ACT_ADDBAREQ = 0,
896 ACT_ADDBARSP = 1,
897 ACT_DELBA = 2,
898 };
899
900 enum rt_polarity_ctl {
901 RT_POLARITY_LOW_ACT = 0,
902 RT_POLARITY_HIGH_ACT = 1,
903 };
904
905 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
906 enum fw_wow_reason_v2 {
907 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
908 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
909 FW_WOW_V2_DISASSOC_EVENT = 0x04,
910 FW_WOW_V2_DEAUTH_EVENT = 0x08,
911 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
912 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
913 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
914 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
915 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
916 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
917 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
918 FW_WOW_V2_REASON_MAX = 0xff,
919 };
920
921 enum wolpattern_type {
922 UNICAST_PATTERN = 0,
923 MULTICAST_PATTERN = 1,
924 BROADCAST_PATTERN = 2,
925 DONT_CARE_DA = 3,
926 UNKNOWN_TYPE = 4,
927 };
928
929 struct octet_string {
930 u8 *octet;
931 u16 length;
932 };
933
934 struct rtl_hdr_3addr {
935 __le16 frame_ctl;
936 __le16 duration_id;
937 u8 addr1[ETH_ALEN];
938 u8 addr2[ETH_ALEN];
939 u8 addr3[ETH_ALEN];
940 __le16 seq_ctl;
941 u8 payload[0];
942 } __packed;
943
944 struct rtl_info_element {
945 u8 id;
946 u8 len;
947 u8 data[0];
948 } __packed;
949
950 struct rtl_probe_rsp {
951 struct rtl_hdr_3addr header;
952 u32 time_stamp[2];
953 __le16 beacon_interval;
954 __le16 capability;
955 /*SSID, supported rates, FH params, DS params,
956 CF params, IBSS params, TIM (if beacon), RSN */
957 struct rtl_info_element info_element[0];
958 } __packed;
959
960 /*LED related.*/
961 /*ledpin Identify how to implement this SW led.*/
962 struct rtl_led {
963 void *hw;
964 enum rtl_led_pin ledpin;
965 bool ledon;
966 };
967
968 struct rtl_led_ctl {
969 bool led_opendrain;
970 struct rtl_led sw_led0;
971 struct rtl_led sw_led1;
972 };
973
974 struct rtl_qos_parameters {
975 __le16 cw_min;
976 __le16 cw_max;
977 u8 aifs;
978 u8 flag;
979 __le16 tx_op;
980 } __packed;
981
982 struct rt_smooth_data {
983 u32 elements[100]; /*array to store values */
984 u32 index; /*index to current array to store */
985 u32 total_num; /*num of valid elements */
986 u32 total_val; /*sum of valid elements */
987 };
988
989 struct false_alarm_statistics {
990 u32 cnt_parity_fail;
991 u32 cnt_rate_illegal;
992 u32 cnt_crc8_fail;
993 u32 cnt_mcs_fail;
994 u32 cnt_fast_fsync_fail;
995 u32 cnt_sb_search_fail;
996 u32 cnt_ofdm_fail;
997 u32 cnt_cck_fail;
998 u32 cnt_all;
999 u32 cnt_ofdm_cca;
1000 u32 cnt_cck_cca;
1001 u32 cnt_cca_all;
1002 u32 cnt_bw_usc;
1003 u32 cnt_bw_lsc;
1004 };
1005
1006 struct init_gain {
1007 u8 xaagccore1;
1008 u8 xbagccore1;
1009 u8 xcagccore1;
1010 u8 xdagccore1;
1011 u8 cca;
1012
1013 };
1014
1015 struct wireless_stats {
1016 unsigned long txbytesunicast;
1017 unsigned long txbytesmulticast;
1018 unsigned long txbytesbroadcast;
1019 unsigned long rxbytesunicast;
1020
1021 long rx_snr_db[4];
1022 /*Correct smoothed ss in Dbm, only used
1023 in driver to report real power now. */
1024 long recv_signal_power;
1025 long signal_quality;
1026 long last_sigstrength_inpercent;
1027
1028 u32 rssi_calculate_cnt;
1029 u32 pwdb_all_cnt;
1030
1031 /*Transformed, in dbm. Beautified signal
1032 strength for UI, not correct. */
1033 long signal_strength;
1034
1035 u8 rx_rssi_percentage[4];
1036 u8 rx_evm_dbm[4];
1037 u8 rx_evm_percentage[2];
1038
1039 u16 rx_cfo_short[4];
1040 u16 rx_cfo_tail[4];
1041
1042 struct rt_smooth_data ui_rssi;
1043 struct rt_smooth_data ui_link_quality;
1044 };
1045
1046 struct rate_adaptive {
1047 u8 rate_adaptive_disabled;
1048 u8 ratr_state;
1049 u16 reserve;
1050
1051 u32 high_rssi_thresh_for_ra;
1052 u32 high2low_rssi_thresh_for_ra;
1053 u8 low2high_rssi_thresh_for_ra40m;
1054 u32 low_rssi_thresh_for_ra40m;
1055 u8 low2high_rssi_thresh_for_ra20m;
1056 u32 low_rssi_thresh_for_ra20m;
1057 u32 upper_rssi_threshold_ratr;
1058 u32 middleupper_rssi_threshold_ratr;
1059 u32 middle_rssi_threshold_ratr;
1060 u32 middlelow_rssi_threshold_ratr;
1061 u32 low_rssi_threshold_ratr;
1062 u32 ultralow_rssi_threshold_ratr;
1063 u32 low_rssi_threshold_ratr_40m;
1064 u32 low_rssi_threshold_ratr_20m;
1065 u8 ping_rssi_enable;
1066 u32 ping_rssi_ratr;
1067 u32 ping_rssi_thresh_for_ra;
1068 u32 last_ratr;
1069 u8 pre_ratr_state;
1070 u8 ldpc_thres;
1071 bool use_ldpc;
1072 bool lower_rts_rate;
1073 bool is_special_data;
1074 };
1075
1076 struct regd_pair_mapping {
1077 u16 reg_dmnenum;
1078 u16 reg_5ghz_ctl;
1079 u16 reg_2ghz_ctl;
1080 };
1081
1082 struct dynamic_primary_cca {
1083 u8 pricca_flag;
1084 u8 intf_flag;
1085 u8 intf_type;
1086 u8 dup_rts_flag;
1087 u8 monitor_flag;
1088 u8 ch_offset;
1089 u8 mf_state;
1090 };
1091
1092 struct rtl_regulatory {
1093 s8 alpha2[2];
1094 u16 country_code;
1095 u16 max_power_level;
1096 u32 tp_scale;
1097 u16 current_rd;
1098 u16 current_rd_ext;
1099 int16_t power_limit;
1100 struct regd_pair_mapping *regpair;
1101 };
1102
1103 struct rtl_rfkill {
1104 bool rfkill_state; /*0 is off, 1 is on */
1105 };
1106
1107 /*for P2P PS**/
1108 #define P2P_MAX_NOA_NUM 2
1109
1110 enum p2p_role {
1111 P2P_ROLE_DISABLE = 0,
1112 P2P_ROLE_DEVICE = 1,
1113 P2P_ROLE_CLIENT = 2,
1114 P2P_ROLE_GO = 3
1115 };
1116
1117 enum p2p_ps_state {
1118 P2P_PS_DISABLE = 0,
1119 P2P_PS_ENABLE = 1,
1120 P2P_PS_SCAN = 2,
1121 P2P_PS_SCAN_DONE = 3,
1122 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1123 };
1124
1125 enum p2p_ps_mode {
1126 P2P_PS_NONE = 0,
1127 P2P_PS_CTWINDOW = 1,
1128 P2P_PS_NOA = 2,
1129 P2P_PS_MIX = 3, /* CTWindow and NoA */
1130 };
1131
1132 struct rtl_p2p_ps_info {
1133 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1134 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1135 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1136 /* Client traffic window. A period of time in TU after TBTT. */
1137 u8 ctwindow;
1138 u8 opp_ps; /* opportunistic power save. */
1139 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1140 /* Count for owner, Type of client. */
1141 u8 noa_count_type[P2P_MAX_NOA_NUM];
1142 /* Max duration for owner, preferred or min acceptable duration
1143 * for client.
1144 */
1145 u32 noa_duration[P2P_MAX_NOA_NUM];
1146 /* Length of interval for owner, preferred or max acceptable intervali
1147 * of client.
1148 */
1149 u32 noa_interval[P2P_MAX_NOA_NUM];
1150 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1151 u32 noa_start_time[P2P_MAX_NOA_NUM];
1152 };
1153
1154 struct p2p_ps_offload_t {
1155 u8 offload_en:1;
1156 u8 role:1; /* 1: Owner, 0: Client */
1157 u8 ctwindow_en:1;
1158 u8 noa0_en:1;
1159 u8 noa1_en:1;
1160 u8 allstasleep:1;
1161 u8 discovery:1;
1162 u8 reserved:1;
1163 };
1164
1165 #define IQK_MATRIX_REG_NUM 8
1166 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1167
1168 struct iqk_matrix_regs {
1169 bool iqk_done;
1170 long value[1][IQK_MATRIX_REG_NUM];
1171 };
1172
1173 struct phy_parameters {
1174 u16 length;
1175 u32 *pdata;
1176 };
1177
1178 enum hw_param_tab_index {
1179 PHY_REG_2T,
1180 PHY_REG_1T,
1181 PHY_REG_PG,
1182 RADIOA_2T,
1183 RADIOB_2T,
1184 RADIOA_1T,
1185 RADIOB_1T,
1186 MAC_REG,
1187 AGCTAB_2T,
1188 AGCTAB_1T,
1189 MAX_TAB
1190 };
1191
1192 struct rtl_phy {
1193 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1194 struct init_gain initgain_backup;
1195 enum io_type current_io_type;
1196
1197 u8 rf_mode;
1198 u8 rf_type;
1199 u8 current_chan_bw;
1200 u8 set_bwmode_inprogress;
1201 u8 sw_chnl_inprogress;
1202 u8 sw_chnl_stage;
1203 u8 sw_chnl_step;
1204 u8 current_channel;
1205 u8 h2c_box_num;
1206 u8 set_io_inprogress;
1207 u8 lck_inprogress;
1208
1209 /* record for power tracking */
1210 s32 reg_e94;
1211 s32 reg_e9c;
1212 s32 reg_ea4;
1213 s32 reg_eac;
1214 s32 reg_eb4;
1215 s32 reg_ebc;
1216 s32 reg_ec4;
1217 s32 reg_ecc;
1218 u8 rfpienable;
1219 u8 reserve_0;
1220 u16 reserve_1;
1221 u32 reg_c04, reg_c08, reg_874;
1222 u32 adda_backup[16];
1223 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1224 u32 iqk_bb_backup[10];
1225 bool iqk_initialized;
1226
1227 bool rfpath_rx_enable[MAX_RF_PATH];
1228 u8 reg_837;
1229 /* Dual mac */
1230 bool need_iqk;
1231 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1232
1233 bool rfpi_enable;
1234 bool iqk_in_progress;
1235
1236 u8 pwrgroup_cnt;
1237 u8 cck_high_power;
1238 /* this is for 88E & 8723A */
1239 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1240 /* MAX_PG_GROUP groups of pwr diff by rates */
1241 u32 mcs_offset[MAX_PG_GROUP][16];
1242 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1243 [TX_PWR_BY_RATE_NUM_RF]
1244 [TX_PWR_BY_RATE_NUM_RF]
1245 [TX_PWR_BY_RATE_NUM_SECTION];
1246 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1247 [TX_PWR_BY_RATE_NUM_RF]
1248 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1249 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1250 [TX_PWR_BY_RATE_NUM_RF]
1251 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1252 u8 default_initialgain[4];
1253
1254 /* the current Tx power level */
1255 u8 cur_cck_txpwridx;
1256 u8 cur_ofdm24g_txpwridx;
1257 u8 cur_bw20_txpwridx;
1258 u8 cur_bw40_txpwridx;
1259
1260 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1261 [MAX_2_4G_BANDWITH_NUM]
1262 [MAX_RATE_SECTION_NUM]
1263 [CHANNEL_MAX_NUMBER_2G]
1264 [MAX_RF_PATH_NUM];
1265 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1266 [MAX_5G_BANDWITH_NUM]
1267 [MAX_RATE_SECTION_NUM]
1268 [CHANNEL_MAX_NUMBER_5G]
1269 [MAX_RF_PATH_NUM];
1270
1271 u32 rfreg_chnlval[2];
1272 bool apk_done;
1273 u32 reg_rf3c[2]; /* pathA / pathB */
1274
1275 u32 backup_rf_0x1a;/*92ee*/
1276 /* bfsync */
1277 u8 framesync;
1278 u32 framesync_c34;
1279
1280 u8 num_total_rfpath;
1281 struct phy_parameters hwparam_tables[MAX_TAB];
1282 u16 rf_pathmap;
1283
1284 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1285 enum rt_polarity_ctl polarity_ctl;
1286 };
1287
1288 #define MAX_TID_COUNT 9
1289 #define RTL_AGG_STOP 0
1290 #define RTL_AGG_PROGRESS 1
1291 #define RTL_AGG_START 2
1292 #define RTL_AGG_OPERATIONAL 3
1293 #define RTL_AGG_OFF 0
1294 #define RTL_AGG_ON 1
1295 #define RTL_RX_AGG_START 1
1296 #define RTL_RX_AGG_STOP 0
1297 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1298 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1299
1300 struct rtl_ht_agg {
1301 u16 txq_id;
1302 u16 wait_for_ba;
1303 u16 start_idx;
1304 u64 bitmap;
1305 u32 rate_n_flags;
1306 u8 agg_state;
1307 u8 rx_agg_state;
1308 };
1309
1310 struct rssi_sta {
1311 long undec_sm_pwdb;
1312 long undec_sm_cck;
1313 };
1314
1315 struct rtl_tid_data {
1316 u16 seq_number;
1317 struct rtl_ht_agg agg;
1318 };
1319
1320 struct rtl_sta_info {
1321 struct list_head list;
1322 struct rtl_tid_data tids[MAX_TID_COUNT];
1323 /* just used for ap adhoc or mesh*/
1324 struct rssi_sta rssi_stat;
1325 u16 wireless_mode;
1326 u8 ratr_index;
1327 u8 mimo_ps;
1328 u8 mac_addr[ETH_ALEN];
1329 } __packed;
1330
1331 struct rtl_priv;
1332 struct rtl_io {
1333 struct device *dev;
1334 struct mutex bb_mutex;
1335
1336 /*PCI MEM map */
1337 unsigned long pci_mem_end; /*shared mem end */
1338 unsigned long pci_mem_start; /*shared mem start */
1339
1340 /*PCI IO map */
1341 unsigned long pci_base_addr; /*device I/O address */
1342
1343 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1344 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1345 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1346 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1347 u16 len);
1348
1349 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1350 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1351 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1352
1353 };
1354
1355 struct rtl_mac {
1356 u8 mac_addr[ETH_ALEN];
1357 u8 mac80211_registered;
1358 u8 beacon_enabled;
1359
1360 u32 tx_ss_num;
1361 u32 rx_ss_num;
1362
1363 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1364 struct ieee80211_hw *hw;
1365 struct ieee80211_vif *vif;
1366 enum nl80211_iftype opmode;
1367
1368 /*Probe Beacon management */
1369 struct rtl_tid_data tids[MAX_TID_COUNT];
1370 enum rtl_link_state link_state;
1371
1372 int n_channels;
1373 int n_bitrates;
1374
1375 bool offchan_delay;
1376 u8 p2p; /*using p2p role*/
1377 bool p2p_in_use;
1378
1379 /*filters */
1380 u32 rx_conf;
1381 u16 rx_mgt_filter;
1382 u16 rx_ctrl_filter;
1383 u16 rx_data_filter;
1384
1385 bool act_scanning;
1386 u8 cnt_after_linked;
1387 bool skip_scan;
1388
1389 /* early mode */
1390 /* skb wait queue */
1391 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1392
1393 u8 ht_stbc_cap;
1394 u8 ht_cur_stbc;
1395
1396 /*vht support*/
1397 u8 vht_enable;
1398 u8 bw_80;
1399 u8 vht_cur_ldpc;
1400 u8 vht_cur_stbc;
1401 u8 vht_stbc_cap;
1402 u8 vht_ldpc_cap;
1403
1404 /*RDG*/
1405 bool rdg_en;
1406
1407 /*AP*/
1408 u8 bssid[ETH_ALEN] __aligned(2);
1409 u32 vendor;
1410 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1411 u32 basic_rates; /* b/g rates */
1412 u8 ht_enable;
1413 u8 sgi_40;
1414 u8 sgi_20;
1415 u8 bw_40;
1416 u16 mode; /* wireless mode */
1417 u8 slot_time;
1418 u8 short_preamble;
1419 u8 use_cts_protect;
1420 u8 cur_40_prime_sc;
1421 u8 cur_40_prime_sc_bk;
1422 u8 cur_80_prime_sc;
1423 u64 tsf;
1424 u8 retry_short;
1425 u8 retry_long;
1426 u16 assoc_id;
1427 bool hiddenssid;
1428
1429 /*IBSS*/
1430 int beacon_interval;
1431
1432 /*AMPDU*/
1433 u8 min_space_cfg; /*For Min spacing configurations */
1434 u8 max_mss_density;
1435 u8 current_ampdu_factor;
1436 u8 current_ampdu_density;
1437
1438 /*QOS & EDCA */
1439 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1440 struct rtl_qos_parameters ac[AC_MAX];
1441
1442 /* counters */
1443 u64 last_txok_cnt;
1444 u64 last_rxok_cnt;
1445 u32 last_bt_edca_ul;
1446 u32 last_bt_edca_dl;
1447 };
1448
1449 struct btdm_8723 {
1450 bool all_off;
1451 bool agc_table_en;
1452 bool adc_back_off_on;
1453 bool b2_ant_hid_en;
1454 bool low_penalty_rate_adaptive;
1455 bool rf_rx_lpf_shrink;
1456 bool reject_aggre_pkt;
1457 bool tra_tdma_on;
1458 u8 tra_tdma_nav;
1459 u8 tra_tdma_ant;
1460 bool tdma_on;
1461 u8 tdma_ant;
1462 u8 tdma_nav;
1463 u8 tdma_dac_swing;
1464 u8 fw_dac_swing_lvl;
1465 bool ps_tdma_on;
1466 u8 ps_tdma_byte[5];
1467 bool pta_on;
1468 u32 val_0x6c0;
1469 u32 val_0x6c8;
1470 u32 val_0x6cc;
1471 bool sw_dac_swing_on;
1472 u32 sw_dac_swing_lvl;
1473 u32 wlan_act_hi;
1474 u32 wlan_act_lo;
1475 u32 bt_retry_index;
1476 bool dec_bt_pwr;
1477 bool ignore_wlan_act;
1478 };
1479
1480 struct bt_coexist_8723 {
1481 u32 high_priority_tx;
1482 u32 high_priority_rx;
1483 u32 low_priority_tx;
1484 u32 low_priority_rx;
1485 u8 c2h_bt_info;
1486 bool c2h_bt_info_req_sent;
1487 bool c2h_bt_inquiry_page;
1488 u32 bt_inq_page_start_time;
1489 u8 bt_retry_cnt;
1490 u8 c2h_bt_info_original;
1491 u8 bt_inquiry_page_cnt;
1492 struct btdm_8723 btdm;
1493 };
1494
1495 struct rtl_hal {
1496 struct ieee80211_hw *hw;
1497 bool driver_is_goingto_unload;
1498 bool up_first_time;
1499 bool first_init;
1500 bool being_init_adapter;
1501 bool bbrf_ready;
1502 bool mac_func_enable;
1503 bool pre_edcca_enable;
1504 struct bt_coexist_8723 hal_coex_8723;
1505
1506 enum intf_type interface;
1507 u16 hw_type; /*92c or 92d or 92s and so on */
1508 u8 ic_class;
1509 u8 oem_id;
1510 u32 version; /*version of chip */
1511 u8 state; /*stop 0, start 1 */
1512 u8 board_type;
1513 u8 external_pa;
1514
1515 u8 pa_mode;
1516 u8 pa_type_2g;
1517 u8 pa_type_5g;
1518 u8 lna_type_2g;
1519 u8 lna_type_5g;
1520 u8 external_pa_2g;
1521 u8 external_lna_2g;
1522 u8 external_pa_5g;
1523 u8 external_lna_5g;
1524 u8 rfe_type;
1525
1526 /*firmware */
1527 u32 fwsize;
1528 u8 *pfirmware;
1529 u16 fw_version;
1530 u16 fw_subversion;
1531 bool h2c_setinprogress;
1532 u8 last_hmeboxnum;
1533 bool fw_ready;
1534 /*Reserve page start offset except beacon in TxQ. */
1535 u8 fw_rsvdpage_startoffset;
1536 u8 h2c_txcmd_seq;
1537 u8 current_ra_rate;
1538
1539 /* FW Cmd IO related */
1540 u16 fwcmd_iomap;
1541 u32 fwcmd_ioparam;
1542 bool set_fwcmd_inprogress;
1543 u8 current_fwcmd_io;
1544
1545 struct p2p_ps_offload_t p2p_ps_offload;
1546 bool fw_clk_change_in_progress;
1547 bool allow_sw_to_change_hwclc;
1548 u8 fw_ps_state;
1549 /**/
1550 bool driver_going2unload;
1551
1552 /*AMPDU init min space*/
1553 u8 minspace_cfg; /*For Min spacing configurations */
1554
1555 /* Dual mac */
1556 enum macphy_mode macphymode;
1557 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1558 enum band_type current_bandtypebackup;
1559 enum band_type bandset;
1560 /* dual MAC 0--Mac0 1--Mac1 */
1561 u32 interfaceindex;
1562 /* just for DualMac S3S4 */
1563 u8 macphyctl_reg;
1564 bool earlymode_enable;
1565 u8 max_earlymode_num;
1566 /* Dual mac*/
1567 bool during_mac0init_radiob;
1568 bool during_mac1init_radioa;
1569 bool reloadtxpowerindex;
1570 /* True if IMR or IQK have done
1571 for 2.4G in scan progress */
1572 bool load_imrandiqk_setting_for2g;
1573
1574 bool disable_amsdu_8k;
1575 bool master_of_dmsp;
1576 bool slave_of_dmsp;
1577
1578 u16 rx_tag;/*for 92ee*/
1579 u8 rts_en;
1580
1581 /*for wowlan*/
1582 bool wow_enable;
1583 bool enter_pnp_sleep;
1584 bool wake_from_pnp_sleep;
1585 bool wow_enabled;
1586 __kernel_time_t last_suspend_sec;
1587 u32 wowlan_fwsize;
1588 u8 *wowlan_firmware;
1589
1590 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1591
1592 bool real_wow_v2_enable;
1593 bool re_init_llt_table;
1594 };
1595
1596 struct rtl_security {
1597 /*default 0 */
1598 bool use_sw_sec;
1599
1600 bool being_setkey;
1601 bool use_defaultkey;
1602 /*Encryption Algorithm for Unicast Packet */
1603 enum rt_enc_alg pairwise_enc_algorithm;
1604 /*Encryption Algorithm for Brocast/Multicast */
1605 enum rt_enc_alg group_enc_algorithm;
1606 /*Cam Entry Bitmap */
1607 u32 hwsec_cam_bitmap;
1608 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1609 /*local Key buffer, indx 0 is for
1610 pairwise key 1-4 is for agoup key. */
1611 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1612 u8 key_len[KEY_BUF_SIZE];
1613
1614 /*The pointer of Pairwise Key,
1615 it always points to KeyBuf[4] */
1616 u8 *pairwise_key;
1617 };
1618
1619 #define ASSOCIATE_ENTRY_NUM 33
1620
1621 struct fast_ant_training {
1622 u8 bssid[6];
1623 u8 antsel_rx_keep_0;
1624 u8 antsel_rx_keep_1;
1625 u8 antsel_rx_keep_2;
1626 u32 ant_sum[7];
1627 u32 ant_cnt[7];
1628 u32 ant_ave[7];
1629 u8 fat_state;
1630 u32 train_idx;
1631 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1632 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1633 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1634 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1635 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1636 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1637 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1638 u8 rx_idle_ant;
1639 bool becomelinked;
1640 };
1641
1642 struct dm_phy_dbg_info {
1643 s8 rx_snrdb[4];
1644 u64 num_qry_phy_status;
1645 u64 num_qry_phy_status_cck;
1646 u64 num_qry_phy_status_ofdm;
1647 u16 num_qry_beacon_pkt;
1648 u16 num_non_be_pkt;
1649 s32 rx_evm[4];
1650 };
1651
1652 struct rtl_dm {
1653 /*PHY status for Dynamic Management */
1654 long entry_min_undec_sm_pwdb;
1655 long undec_sm_cck;
1656 long undec_sm_pwdb; /*out dm */
1657 long entry_max_undec_sm_pwdb;
1658 s32 ofdm_pkt_cnt;
1659 bool dm_initialgain_enable;
1660 bool dynamic_txpower_enable;
1661 bool current_turbo_edca;
1662 bool is_any_nonbepkts; /*out dm */
1663 bool is_cur_rdlstate;
1664 bool txpower_trackinginit;
1665 bool disable_framebursting;
1666 bool cck_inch14;
1667 bool txpower_tracking;
1668 bool useramask;
1669 bool rfpath_rxenable[4];
1670 bool inform_fw_driverctrldm;
1671 bool current_mrc_switch;
1672 u8 txpowercount;
1673 u8 powerindex_backup[6];
1674
1675 u8 thermalvalue_rxgain;
1676 u8 thermalvalue_iqk;
1677 u8 thermalvalue_lck;
1678 u8 thermalvalue;
1679 u8 last_dtp_lvl;
1680 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1681 u8 thermalvalue_avg_index;
1682 u8 tm_trigger;
1683 bool done_txpower;
1684 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1685 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1686 u8 dm_flag_tmp;
1687 u8 dm_type;
1688 u8 dm_rssi_sel;
1689 u8 txpower_track_control;
1690 bool interrupt_migration;
1691 bool disable_tx_int;
1692 s8 ofdm_index[MAX_RF_PATH];
1693 u8 default_ofdm_index;
1694 u8 default_cck_index;
1695 s8 cck_index;
1696 s8 delta_power_index[MAX_RF_PATH];
1697 s8 delta_power_index_last[MAX_RF_PATH];
1698 s8 power_index_offset[MAX_RF_PATH];
1699 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1700 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1701 s8 remnant_cck_idx;
1702 bool modify_txagc_flag_path_a;
1703 bool modify_txagc_flag_path_b;
1704
1705 bool one_entry_only;
1706 struct dm_phy_dbg_info dbginfo;
1707
1708 /* Dynamic ATC switch */
1709 bool atc_status;
1710 bool large_cfo_hit;
1711 bool is_freeze;
1712 int cfo_tail[2];
1713 int cfo_ave_pre;
1714 int crystal_cap;
1715 u8 cfo_threshold;
1716 u32 packet_count;
1717 u32 packet_count_pre;
1718 u8 tx_rate;
1719
1720 /*88e tx power tracking*/
1721 u8 swing_idx_ofdm[MAX_RF_PATH];
1722 u8 swing_idx_ofdm_cur;
1723 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1724 bool swing_flag_ofdm;
1725 u8 swing_idx_cck;
1726 u8 swing_idx_cck_cur;
1727 u8 swing_idx_cck_base;
1728 bool swing_flag_cck;
1729
1730 s8 swing_diff_2g;
1731 s8 swing_diff_5g;
1732
1733 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1734 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1735 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1736 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1737 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1738 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1739 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1740 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1741 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1742 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1743 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1744 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1745 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1746 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1747
1748 /* DMSP */
1749 bool supp_phymode_switch;
1750
1751 /* DulMac */
1752 struct fast_ant_training fat_table;
1753
1754 u8 resp_tx_path;
1755 u8 path_sel;
1756 u32 patha_sum;
1757 u32 pathb_sum;
1758 u32 patha_cnt;
1759 u32 pathb_cnt;
1760
1761 u8 pre_channel;
1762 u8 *p_channel;
1763 u8 linked_interval;
1764
1765 u64 last_tx_ok_cnt;
1766 u64 last_rx_ok_cnt;
1767 };
1768
1769 #define EFUSE_MAX_LOGICAL_SIZE 512
1770
1771 struct rtl_efuse {
1772 bool autoLoad_ok;
1773 bool bootfromefuse;
1774 u16 max_physical_size;
1775
1776 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1777 u16 efuse_usedbytes;
1778 u8 efuse_usedpercentage;
1779 #ifdef EFUSE_REPG_WORKAROUND
1780 bool efuse_re_pg_sec1flag;
1781 u8 efuse_re_pg_data[8];
1782 #endif
1783
1784 u8 autoload_failflag;
1785 u8 autoload_status;
1786
1787 short epromtype;
1788 u16 eeprom_vid;
1789 u16 eeprom_did;
1790 u16 eeprom_svid;
1791 u16 eeprom_smid;
1792 u8 eeprom_oemid;
1793 u16 eeprom_channelplan;
1794 u8 eeprom_version;
1795 u8 board_type;
1796 u8 external_pa;
1797
1798 u8 dev_addr[6];
1799 u8 wowlan_enable;
1800 u8 antenna_div_cfg;
1801 u8 antenna_div_type;
1802
1803 bool txpwr_fromeprom;
1804 u8 eeprom_crystalcap;
1805 u8 eeprom_tssi[2];
1806 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1807 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1808 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1809 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1810 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1811 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1812
1813 u8 internal_pa_5g[2]; /* pathA / pathB */
1814 u8 eeprom_c9;
1815 u8 eeprom_cc;
1816
1817 /*For power group */
1818 u8 eeprom_pwrgroup[2][3];
1819 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1820 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1821
1822 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1823 /*For HT 40MHZ pwr */
1824 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1825 /*For HT 40MHZ pwr */
1826 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1827
1828 /*--------------------------------------------------------*
1829 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1830 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1831 * define new arrays in Windows code.
1832 * BUT, in linux code, we use the same array for all ICs.
1833 *
1834 * The Correspondance relation between two arrays is:
1835 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1836 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1837 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1838 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1839 *
1840 * Sizes of these arrays are decided by the larger ones.
1841 */
1842 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1843 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1844 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1845 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1846
1847 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1848 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1849 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1850 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1851 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1852 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1853
1854 u8 txpwr_safetyflag; /* Band edge enable flag */
1855 u16 eeprom_txpowerdiff;
1856 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1857 u8 antenna_txpwdiff[3];
1858
1859 u8 eeprom_regulatory;
1860 u8 eeprom_thermalmeter;
1861 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1862 u16 tssi_13dbm;
1863 u8 crystalcap; /* CrystalCap. */
1864 u8 delta_iqk;
1865 u8 delta_lck;
1866
1867 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1868 bool apk_thermalmeterignore;
1869
1870 bool b1x1_recvcombine;
1871 bool b1ss_support;
1872
1873 /*channel plan */
1874 u8 channel_plan;
1875 };
1876
1877 struct rtl_ps_ctl {
1878 bool pwrdomain_protect;
1879 bool in_powersavemode;
1880 bool rfchange_inprogress;
1881 bool swrf_processing;
1882 bool hwradiooff;
1883 /*
1884 * just for PCIE ASPM
1885 * If it supports ASPM, Offset[560h] = 0x40,
1886 * otherwise Offset[560h] = 0x00.
1887 * */
1888 bool support_aspm;
1889 bool support_backdoor;
1890
1891 /*for LPS */
1892 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1893 bool swctrl_lps;
1894 bool leisure_ps;
1895 bool fwctrl_lps;
1896 u8 fwctrl_psmode;
1897 /*For Fw control LPS mode */
1898 u8 reg_fwctrl_lps;
1899 /*Record Fw PS mode status. */
1900 bool fw_current_inpsmode;
1901 u8 reg_max_lps_awakeintvl;
1902 bool report_linked;
1903 bool low_power_enable;/*for 32k*/
1904
1905 /*for IPS */
1906 bool inactiveps;
1907
1908 u32 rfoff_reason;
1909
1910 /*RF OFF Level */
1911 u32 cur_ps_level;
1912 u32 reg_rfps_level;
1913
1914 /*just for PCIE ASPM */
1915 u8 const_amdpci_aspm;
1916 bool pwrdown_mode;
1917
1918 enum rf_pwrstate inactive_pwrstate;
1919 enum rf_pwrstate rfpwr_state; /*cur power state */
1920
1921 /* for SW LPS*/
1922 bool sw_ps_enabled;
1923 bool state;
1924 bool state_inap;
1925 bool multi_buffered;
1926 u16 nullfunc_seq;
1927 unsigned int dtim_counter;
1928 unsigned int sleep_ms;
1929 unsigned long last_sleep_jiffies;
1930 unsigned long last_awake_jiffies;
1931 unsigned long last_delaylps_stamp_jiffies;
1932 unsigned long last_dtim;
1933 unsigned long last_beacon;
1934 unsigned long last_action;
1935 unsigned long last_slept;
1936
1937 /*For P2P PS */
1938 struct rtl_p2p_ps_info p2p_ps_info;
1939 u8 pwr_mode;
1940 u8 smart_ps;
1941
1942 /* wake up on line */
1943 u8 wo_wlan_mode;
1944 u8 arp_offload_enable;
1945 u8 gtk_offload_enable;
1946 /* Used for WOL, indicates the reason for waking event.*/
1947 u32 wakeup_reason;
1948 /* Record the last waking time for comparison with setting key. */
1949 u64 last_wakeup_time;
1950 };
1951
1952 struct rtl_stats {
1953 u8 psaddr[ETH_ALEN];
1954 u32 mac_time[2];
1955 s8 rssi;
1956 u8 signal;
1957 u8 noise;
1958 u8 rate; /* hw desc rate */
1959 u8 received_channel;
1960 u8 control;
1961 u8 mask;
1962 u8 freq;
1963 u16 len;
1964 u64 tsf;
1965 u32 beacon_time;
1966 u8 nic_type;
1967 u16 length;
1968 u8 signalquality; /*in 0-100 index. */
1969 /*
1970 * Real power in dBm for this packet,
1971 * no beautification and aggregation.
1972 * */
1973 s32 recvsignalpower;
1974 s8 rxpower; /*in dBm Translate from PWdB */
1975 u8 signalstrength; /*in 0-100 index. */
1976 u16 hwerror:1;
1977 u16 crc:1;
1978 u16 icv:1;
1979 u16 shortpreamble:1;
1980 u16 antenna:1;
1981 u16 decrypted:1;
1982 u16 wakeup:1;
1983 u32 timestamp_low;
1984 u32 timestamp_high;
1985 bool shift;
1986
1987 u8 rx_drvinfo_size;
1988 u8 rx_bufshift;
1989 bool isampdu;
1990 bool isfirst_ampdu;
1991 bool rx_is40Mhzpacket;
1992 u8 rx_packet_bw;
1993 u32 rx_pwdb_all;
1994 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1995 s8 rx_mimo_signalquality[4];
1996 u8 rx_mimo_evm_dbm[4];
1997 u16 cfo_short[4]; /* per-path's Cfo_short */
1998 u16 cfo_tail[4];
1999
2000 s8 rx_mimo_sig_qual[4];
2001 u8 rx_pwr[4]; /* per-path's pwdb */
2002 u8 rx_snr[4]; /* per-path's SNR */
2003 u8 bandwidth;
2004 u8 bt_coex_pwr_adjust;
2005 bool packet_matchbssid;
2006 bool is_cck;
2007 bool is_ht;
2008 bool packet_toself;
2009 bool packet_beacon; /*for rssi */
2010 s8 cck_adc_pwdb[4]; /*for rx path selection */
2011
2012 bool is_vht;
2013 bool is_short_gi;
2014 u8 vht_nss;
2015
2016 u8 packet_report_type;
2017
2018 u32 macid;
2019 u8 wake_match;
2020 u32 bt_rx_rssi_percentage;
2021 u32 macid_valid_entry[2];
2022 };
2023
2024
2025 struct rt_link_detect {
2026 /* count for roaming */
2027 u32 bcn_rx_inperiod;
2028 u32 roam_times;
2029
2030 u32 num_tx_in4period[4];
2031 u32 num_rx_in4period[4];
2032
2033 u32 num_tx_inperiod;
2034 u32 num_rx_inperiod;
2035
2036 bool busytraffic;
2037 bool tx_busy_traffic;
2038 bool rx_busy_traffic;
2039 bool higher_busytraffic;
2040 bool higher_busyrxtraffic;
2041
2042 u32 tidtx_in4period[MAX_TID_COUNT][4];
2043 u32 tidtx_inperiod[MAX_TID_COUNT];
2044 bool higher_busytxtraffic[MAX_TID_COUNT];
2045 };
2046
2047 struct rtl_tcb_desc {
2048 u8 packet_bw:2;
2049 u8 multicast:1;
2050 u8 broadcast:1;
2051
2052 u8 rts_stbc:1;
2053 u8 rts_enable:1;
2054 u8 cts_enable:1;
2055 u8 rts_use_shortpreamble:1;
2056 u8 rts_use_shortgi:1;
2057 u8 rts_sc:1;
2058 u8 rts_bw:1;
2059 u8 rts_rate;
2060
2061 u8 use_shortgi:1;
2062 u8 use_shortpreamble:1;
2063 u8 use_driver_rate:1;
2064 u8 disable_ratefallback:1;
2065
2066 u8 ratr_index;
2067 u8 mac_id;
2068 u8 hw_rate;
2069
2070 u8 last_inipkt:1;
2071 u8 cmd_or_init:1;
2072 u8 queue_index;
2073
2074 /* early mode */
2075 u8 empkt_num;
2076 /* The max value by HW */
2077 u32 empkt_len[10];
2078 bool tx_enable_sw_calc_duration;
2079 };
2080
2081 struct rtl_wow_pattern {
2082 u8 type;
2083 u16 crc;
2084 u32 mask[4];
2085 };
2086
2087 struct rtl_hal_ops {
2088 int (*init_sw_vars) (struct ieee80211_hw *hw);
2089 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
2090 void (*read_chip_version)(struct ieee80211_hw *hw);
2091 void (*read_eeprom_info) (struct ieee80211_hw *hw);
2092 void (*interrupt_recognized) (struct ieee80211_hw *hw,
2093 u32 *p_inta, u32 *p_intb);
2094 int (*hw_init) (struct ieee80211_hw *hw);
2095 void (*hw_disable) (struct ieee80211_hw *hw);
2096 void (*hw_suspend) (struct ieee80211_hw *hw);
2097 void (*hw_resume) (struct ieee80211_hw *hw);
2098 void (*enable_interrupt) (struct ieee80211_hw *hw);
2099 void (*disable_interrupt) (struct ieee80211_hw *hw);
2100 int (*set_network_type) (struct ieee80211_hw *hw,
2101 enum nl80211_iftype type);
2102 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2103 bool check_bssid);
2104 void (*set_bw_mode) (struct ieee80211_hw *hw,
2105 enum nl80211_channel_type ch_type);
2106 u8(*switch_channel) (struct ieee80211_hw *hw);
2107 void (*set_qos) (struct ieee80211_hw *hw, int aci);
2108 void (*set_bcn_reg) (struct ieee80211_hw *hw);
2109 void (*set_bcn_intv) (struct ieee80211_hw *hw);
2110 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
2111 u32 add_msr, u32 rm_msr);
2112 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2113 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2114 void (*update_rate_tbl) (struct ieee80211_hw *hw,
2115 struct ieee80211_sta *sta, u8 rssi_level);
2116 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2117 u8 *desc, u8 queue_index,
2118 struct sk_buff *skb, dma_addr_t addr);
2119 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2120 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2121 u8 queue_index);
2122 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2123 u8 queue_index);
2124 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2125 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2126 u8 *pbd_desc_tx,
2127 struct ieee80211_tx_info *info,
2128 struct ieee80211_sta *sta,
2129 struct sk_buff *skb, u8 hw_queue,
2130 struct rtl_tcb_desc *ptcb_desc);
2131 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2132 u32 buffer_len, bool bIsPsPoll);
2133 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2134 bool firstseg, bool lastseg,
2135 struct sk_buff *skb);
2136 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2137 struct rtl_stats *stats,
2138 struct ieee80211_rx_status *rx_status,
2139 u8 *pdesc, struct sk_buff *skb);
2140 void (*set_channel_access) (struct ieee80211_hw *hw);
2141 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2142 void (*dm_watchdog) (struct ieee80211_hw *hw);
2143 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2144 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2145 enum rf_pwrstate rfpwr_state);
2146 void (*led_control) (struct ieee80211_hw *hw,
2147 enum led_ctl_mode ledaction);
2148 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2149 u8 desc_name, u8 *val);
2150 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2151 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2152 u8 hw_queue, u16 index);
2153 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2154 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2155 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2156 u8 *macaddr, bool is_group, u8 enc_algo,
2157 bool is_wepkey, bool clear_all);
2158 void (*init_sw_leds) (struct ieee80211_hw *hw);
2159 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2160 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2161 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2162 u32 data);
2163 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2164 u32 regaddr, u32 bitmask);
2165 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2166 u32 regaddr, u32 bitmask, u32 data);
2167 void (*linked_set_reg) (struct ieee80211_hw *hw);
2168 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2169 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2170 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2171 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2172 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2173 u8 *powerlevel);
2174 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2175 u8 *ppowerlevel, u8 channel);
2176 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2177 u8 configtype);
2178 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2179 u8 configtype);
2180 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2181 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2182 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2183 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2184 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2185 bool mstate);
2186 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2187 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2188 u32 cmd_len, u8 *p_cmdbuffer);
2189 bool (*get_btc_status) (void);
2190 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2191 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2192 const struct rtl_stats *status, struct sk_buff *skb);
2193 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2194 struct rtl_wow_pattern *rtl_pattern,
2195 u8 index);
2196 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2197 };
2198
2199 struct rtl_intf_ops {
2200 /*com */
2201 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2202 int (*adapter_start) (struct ieee80211_hw *hw);
2203 void (*adapter_stop) (struct ieee80211_hw *hw);
2204 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2205 struct rtl_priv **buddy_priv);
2206
2207 int (*adapter_tx) (struct ieee80211_hw *hw,
2208 struct ieee80211_sta *sta,
2209 struct sk_buff *skb,
2210 struct rtl_tcb_desc *ptcb_desc);
2211 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2212 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2213 bool (*waitq_insert) (struct ieee80211_hw *hw,
2214 struct ieee80211_sta *sta,
2215 struct sk_buff *skb);
2216
2217 /*pci */
2218 void (*disable_aspm) (struct ieee80211_hw *hw);
2219 void (*enable_aspm) (struct ieee80211_hw *hw);
2220
2221 /*usb */
2222 };
2223
2224 struct rtl_mod_params {
2225 /* default: 0 = using hardware encryption */
2226 bool sw_crypto;
2227
2228 /* default: 0 = DBG_EMERG (0)*/
2229 int debug;
2230
2231 /* default: 1 = using no linked power save */
2232 bool inactiveps;
2233
2234 /* default: 1 = using linked sw power save */
2235 bool swctrl_lps;
2236
2237 /* default: 1 = using linked fw power save */
2238 bool fwctrl_lps;
2239
2240 /* default: 0 = not using MSI interrupts mode
2241 * submodules should set their own default value
2242 */
2243 bool msi_support;
2244
2245 /* default 0: 1 means disable */
2246 bool disable_watchdog;
2247
2248 /* default 0: 1 means do not disable interrupts */
2249 bool int_clear;
2250
2251 /* select antenna */
2252 int ant_sel;
2253 };
2254
2255 struct rtl_hal_usbint_cfg {
2256 /* data - rx */
2257 u32 in_ep_num;
2258 u32 rx_urb_num;
2259 u32 rx_max_size;
2260
2261 /* op - rx */
2262 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2263 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2264 struct sk_buff_head *);
2265
2266 /* tx */
2267 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2268 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2269 struct sk_buff *);
2270 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2271 struct sk_buff_head *);
2272
2273 /* endpoint mapping */
2274 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2275 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2276 };
2277
2278 struct rtl_hal_cfg {
2279 u8 bar_id;
2280 bool write_readback;
2281 char *name;
2282 char *alt_fw_name;
2283 struct rtl_hal_ops *ops;
2284 struct rtl_mod_params *mod_params;
2285 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2286
2287 /*this map used for some registers or vars
2288 defined int HAL but used in MAIN */
2289 u32 maps[RTL_VAR_MAP_MAX];
2290
2291 };
2292
2293 struct rtl_locks {
2294 /* mutex */
2295 struct mutex conf_mutex;
2296 struct mutex ps_mutex;
2297
2298 /*spin lock */
2299 spinlock_t ips_lock;
2300 spinlock_t irq_th_lock;
2301 spinlock_t irq_pci_lock;
2302 spinlock_t tx_lock;
2303 spinlock_t h2c_lock;
2304 spinlock_t rf_ps_lock;
2305 spinlock_t rf_lock;
2306 spinlock_t lps_lock;
2307 spinlock_t waitq_lock;
2308 spinlock_t entry_list_lock;
2309 spinlock_t usb_lock;
2310
2311 /*FW clock change */
2312 spinlock_t fw_ps_lock;
2313
2314 /*Dual mac*/
2315 spinlock_t cck_and_rw_pagea_lock;
2316
2317 /*Easy concurrent*/
2318 spinlock_t check_sendpkt_lock;
2319
2320 spinlock_t iqk_lock;
2321 };
2322
2323 struct rtl_works {
2324 struct ieee80211_hw *hw;
2325
2326 /*timer */
2327 struct timer_list watchdog_timer;
2328 struct timer_list dualmac_easyconcurrent_retrytimer;
2329 struct timer_list fw_clockoff_timer;
2330 struct timer_list fast_antenna_training_timer;
2331 /*task */
2332 struct tasklet_struct irq_tasklet;
2333 struct tasklet_struct irq_prepare_bcn_tasklet;
2334
2335 /*work queue */
2336 struct workqueue_struct *rtl_wq;
2337 struct delayed_work watchdog_wq;
2338 struct delayed_work ips_nic_off_wq;
2339
2340 /* For SW LPS */
2341 struct delayed_work ps_work;
2342 struct delayed_work ps_rfon_wq;
2343 struct delayed_work fwevt_wq;
2344
2345 struct work_struct lps_change_work;
2346 struct work_struct fill_h2c_cmd;
2347 };
2348
2349 struct rtl_debug {
2350 u32 dbgp_type[DBGP_TYPE_MAX];
2351 int global_debuglevel;
2352 u64 global_debugcomponents;
2353
2354 /* add for proc debug */
2355 struct proc_dir_entry *proc_dir;
2356 char proc_name[20];
2357 };
2358
2359 #define MIMO_PS_STATIC 0
2360 #define MIMO_PS_DYNAMIC 1
2361 #define MIMO_PS_NOLIMIT 3
2362
2363 struct rtl_dualmac_easy_concurrent_ctl {
2364 enum band_type currentbandtype_backfordmdp;
2365 bool close_bbandrf_for_dmsp;
2366 bool change_to_dmdp;
2367 bool change_to_dmsp;
2368 bool switch_in_process;
2369 };
2370
2371 struct rtl_dmsp_ctl {
2372 bool activescan_for_slaveofdmsp;
2373 bool scan_for_anothermac_fordmsp;
2374 bool scan_for_itself_fordmsp;
2375 bool writedig_for_anothermacofdmsp;
2376 u32 curdigvalue_for_anothermacofdmsp;
2377 bool changecckpdstate_for_anothermacofdmsp;
2378 u8 curcckpdstate_for_anothermacofdmsp;
2379 bool changetxhighpowerlvl_for_anothermacofdmsp;
2380 u8 curtxhighlvl_for_anothermacofdmsp;
2381 long rssivalmin_for_anothermacofdmsp;
2382 };
2383
2384 struct ps_t {
2385 u8 pre_ccastate;
2386 u8 cur_ccasate;
2387 u8 pre_rfstate;
2388 u8 cur_rfstate;
2389 u8 initialize;
2390 long rssi_val_min;
2391 };
2392
2393 struct dig_t {
2394 u32 rssi_lowthresh;
2395 u32 rssi_highthresh;
2396 u32 fa_lowthresh;
2397 u32 fa_highthresh;
2398 long last_min_undec_pwdb_for_dm;
2399 long rssi_highpower_lowthresh;
2400 long rssi_highpower_highthresh;
2401 u32 recover_cnt;
2402 u32 pre_igvalue;
2403 u32 cur_igvalue;
2404 long rssi_val;
2405 u8 dig_enable_flag;
2406 u8 dig_ext_port_stage;
2407 u8 dig_algorithm;
2408 u8 dig_twoport_algorithm;
2409 u8 dig_dbgmode;
2410 u8 dig_slgorithm_switch;
2411 u8 cursta_cstate;
2412 u8 presta_cstate;
2413 u8 curmultista_cstate;
2414 u8 stop_dig;
2415 s8 back_val;
2416 s8 back_range_max;
2417 s8 back_range_min;
2418 u8 rx_gain_max;
2419 u8 rx_gain_min;
2420 u8 min_undec_pwdb_for_dm;
2421 u8 rssi_val_min;
2422 u8 pre_cck_cca_thres;
2423 u8 cur_cck_cca_thres;
2424 u8 pre_cck_pd_state;
2425 u8 cur_cck_pd_state;
2426 u8 pre_cck_fa_state;
2427 u8 cur_cck_fa_state;
2428 u8 pre_ccastate;
2429 u8 cur_ccasate;
2430 u8 large_fa_hit;
2431 u8 forbidden_igi;
2432 u8 dig_state;
2433 u8 dig_highpwrstate;
2434 u8 cur_sta_cstate;
2435 u8 pre_sta_cstate;
2436 u8 cur_ap_cstate;
2437 u8 pre_ap_cstate;
2438 u8 cur_pd_thstate;
2439 u8 pre_pd_thstate;
2440 u8 cur_cs_ratiostate;
2441 u8 pre_cs_ratiostate;
2442 u8 backoff_enable_flag;
2443 s8 backoffval_range_max;
2444 s8 backoffval_range_min;
2445 u8 dig_min_0;
2446 u8 dig_min_1;
2447 u8 bt30_cur_igi;
2448 bool media_connect_0;
2449 bool media_connect_1;
2450
2451 u32 antdiv_rssi_max;
2452 u32 rssi_max;
2453 };
2454
2455 struct rtl_global_var {
2456 /* from this list we can get
2457 * other adapter's rtl_priv */
2458 struct list_head glb_priv_list;
2459 spinlock_t glb_list_lock;
2460 };
2461
2462 struct rtl_btc_info {
2463 u8 bt_type;
2464 u8 btcoexist;
2465 u8 ant_num;
2466 };
2467
2468 struct bt_coexist_info {
2469 struct rtl_btc_ops *btc_ops;
2470 struct rtl_btc_info btc_info;
2471 /* EEPROM BT info. */
2472 u8 eeprom_bt_coexist;
2473 u8 eeprom_bt_type;
2474 u8 eeprom_bt_ant_num;
2475 u8 eeprom_bt_ant_isol;
2476 u8 eeprom_bt_radio_shared;
2477
2478 u8 bt_coexistence;
2479 u8 bt_ant_num;
2480 u8 bt_coexist_type;
2481 u8 bt_state;
2482 u8 bt_cur_state; /* 0:on, 1:off */
2483 u8 bt_ant_isolation; /* 0:good, 1:bad */
2484 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2485 u8 bt_service;
2486 u8 bt_radio_shared_type;
2487 u8 bt_rfreg_origin_1e;
2488 u8 bt_rfreg_origin_1f;
2489 u8 bt_rssi_state;
2490 u32 ratio_tx;
2491 u32 ratio_pri;
2492 u32 bt_edca_ul;
2493 u32 bt_edca_dl;
2494
2495 bool init_set;
2496 bool bt_busy_traffic;
2497 bool bt_traffic_mode_set;
2498 bool bt_non_traffic_mode_set;
2499
2500 bool fw_coexist_all_off;
2501 bool sw_coexist_all_off;
2502 bool hw_coexist_all_off;
2503 u32 cstate;
2504 u32 previous_state;
2505 u32 cstate_h;
2506 u32 previous_state_h;
2507
2508 u8 bt_pre_rssi_state;
2509 u8 bt_pre_rssi_state1;
2510
2511 u8 reg_bt_iso;
2512 u8 reg_bt_sco;
2513 bool balance_on;
2514 u8 bt_active_zero_cnt;
2515 bool cur_bt_disabled;
2516 bool pre_bt_disabled;
2517
2518 u8 bt_profile_case;
2519 u8 bt_profile_action;
2520 bool bt_busy;
2521 bool hold_for_bt_operation;
2522 u8 lps_counter;
2523 };
2524
2525 struct rtl_btc_ops {
2526 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2527 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2528 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2529 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2530 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2531 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2532 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2533 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2534 enum rt_media_status mstatus);
2535 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2536 void (*btc_halt_notify) (void);
2537 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2538 u8 *tmp_buf, u8 length);
2539 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2540 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2541 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2542 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2543 u8 pkt_type);
2544 };
2545
2546 struct proxim {
2547 bool proxim_on;
2548
2549 void *proximity_priv;
2550 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2551 struct sk_buff *skb);
2552 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2553 };
2554
2555 struct rtl_priv {
2556 struct ieee80211_hw *hw;
2557 struct completion firmware_loading_complete;
2558 struct list_head list;
2559 struct rtl_priv *buddy_priv;
2560 struct rtl_global_var *glb_var;
2561 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2562 struct rtl_dmsp_ctl dmsp_ctl;
2563 struct rtl_locks locks;
2564 struct rtl_works works;
2565 struct rtl_mac mac80211;
2566 struct rtl_hal rtlhal;
2567 struct rtl_regulatory regd;
2568 struct rtl_rfkill rfkill;
2569 struct rtl_io io;
2570 struct rtl_phy phy;
2571 struct rtl_dm dm;
2572 struct rtl_security sec;
2573 struct rtl_efuse efuse;
2574
2575 struct rtl_ps_ctl psc;
2576 struct rate_adaptive ra;
2577 struct dynamic_primary_cca primarycca;
2578 struct wireless_stats stats;
2579 struct rt_link_detect link_info;
2580 struct false_alarm_statistics falsealm_cnt;
2581
2582 struct rtl_rate_priv *rate_priv;
2583
2584 /* sta entry list for ap adhoc or mesh */
2585 struct list_head entry_list;
2586
2587 struct rtl_debug dbg;
2588 int max_fw_size;
2589
2590 /*
2591 *hal_cfg : for diff cards
2592 *intf_ops : for diff interrface usb/pcie
2593 */
2594 struct rtl_hal_cfg *cfg;
2595 const struct rtl_intf_ops *intf_ops;
2596
2597 /*this var will be set by set_bit,
2598 and was used to indicate status of
2599 interface or hardware */
2600 unsigned long status;
2601
2602 /* tables for dm */
2603 struct dig_t dm_digtable;
2604 struct ps_t dm_pstable;
2605
2606 u32 reg_874;
2607 u32 reg_c70;
2608 u32 reg_85c;
2609 u32 reg_a74;
2610 bool reg_init; /* true if regs saved */
2611 bool bt_operation_on;
2612 __le32 *usb_data;
2613 int usb_data_index;
2614 bool initialized;
2615 bool enter_ps; /* true when entering PS */
2616 u8 rate_mask[5];
2617
2618 /* intel Proximity, should be alloc mem
2619 * in intel Proximity module and can only
2620 * be used in intel Proximity mode
2621 */
2622 struct proxim proximity;
2623
2624 /*for bt coexist use*/
2625 struct bt_coexist_info btcoexist;
2626
2627 /* separate 92ee from other ICs,
2628 * 92ee use new trx flow.
2629 */
2630 bool use_new_trx_flow;
2631
2632 #ifdef CONFIG_PM
2633 struct wiphy_wowlan_support wowlan;
2634 #endif
2635 /*This must be the last item so
2636 that it points to the data allocated
2637 beyond this structure like:
2638 rtl_pci_priv or rtl_usb_priv */
2639 u8 priv[0] __aligned(sizeof(void *));
2640 };
2641
2642 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2643 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2644 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2645 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2646 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2647
2648
2649 /***************************************
2650 Bluetooth Co-existence Related
2651 ****************************************/
2652
2653 enum bt_ant_num {
2654 ANT_X2 = 0,
2655 ANT_X1 = 1,
2656 };
2657
2658 enum bt_co_type {
2659 BT_2WIRE = 0,
2660 BT_ISSC_3WIRE = 1,
2661 BT_ACCEL = 2,
2662 BT_CSR_BC4 = 3,
2663 BT_CSR_BC8 = 4,
2664 BT_RTL8756 = 5,
2665 BT_RTL8723A = 6,
2666 BT_RTL8821A = 7,
2667 BT_RTL8723B = 8,
2668 BT_RTL8192E = 9,
2669 BT_RTL8812A = 11,
2670 };
2671
2672 enum bt_total_ant_num {
2673 ANT_TOTAL_X2 = 0,
2674 ANT_TOTAL_X1 = 1
2675 };
2676
2677 enum bt_cur_state {
2678 BT_OFF = 0,
2679 BT_ON = 1,
2680 };
2681
2682 enum bt_service_type {
2683 BT_SCO = 0,
2684 BT_A2DP = 1,
2685 BT_HID = 2,
2686 BT_HID_IDLE = 3,
2687 BT_SCAN = 4,
2688 BT_IDLE = 5,
2689 BT_OTHER_ACTION = 6,
2690 BT_BUSY = 7,
2691 BT_OTHERBUSY = 8,
2692 BT_PAN = 9,
2693 };
2694
2695 enum bt_radio_shared {
2696 BT_RADIO_SHARED = 0,
2697 BT_RADIO_INDIVIDUAL = 1,
2698 };
2699
2700
2701 /****************************************
2702 mem access macro define start
2703 Call endian free function when
2704 1. Read/write packet content.
2705 2. Before write integer to IO.
2706 3. After read integer from IO.
2707 ****************************************/
2708 /* Convert little data endian to host ordering */
2709 #define EF1BYTE(_val) \
2710 ((u8)(_val))
2711 #define EF2BYTE(_val) \
2712 (le16_to_cpu(_val))
2713 #define EF4BYTE(_val) \
2714 (le32_to_cpu(_val))
2715
2716 /* Read data from memory */
2717 #define READEF1BYTE(_ptr) \
2718 EF1BYTE(*((u8 *)(_ptr)))
2719 /* Read le16 data from memory and convert to host ordering */
2720 #define READEF2BYTE(_ptr) \
2721 EF2BYTE(*(_ptr))
2722 #define READEF4BYTE(_ptr) \
2723 EF4BYTE(*(_ptr))
2724
2725 /* Write data to memory */
2726 #define WRITEEF1BYTE(_ptr, _val) \
2727 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2728 /* Write le16 data to memory in host ordering */
2729 #define WRITEEF2BYTE(_ptr, _val) \
2730 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2731 #define WRITEEF4BYTE(_ptr, _val) \
2732 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2733
2734 /* Create a bit mask
2735 * Examples:
2736 * BIT_LEN_MASK_32(0) => 0x00000000
2737 * BIT_LEN_MASK_32(1) => 0x00000001
2738 * BIT_LEN_MASK_32(2) => 0x00000003
2739 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2740 */
2741 #define BIT_LEN_MASK_32(__bitlen) \
2742 (0xFFFFFFFF >> (32 - (__bitlen)))
2743 #define BIT_LEN_MASK_16(__bitlen) \
2744 (0xFFFF >> (16 - (__bitlen)))
2745 #define BIT_LEN_MASK_8(__bitlen) \
2746 (0xFF >> (8 - (__bitlen)))
2747
2748 /* Create an offset bit mask
2749 * Examples:
2750 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2751 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2752 */
2753 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2754 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2755 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2756 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2757 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2758 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2759
2760 /*Description:
2761 * Return 4-byte value in host byte ordering from
2762 * 4-byte pointer in little-endian system.
2763 */
2764 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2765 (EF4BYTE(*((__le32 *)(__pstart))))
2766 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2767 (EF2BYTE(*((__le16 *)(__pstart))))
2768 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2769 (EF1BYTE(*((u8 *)(__pstart))))
2770
2771 /*Description:
2772 Translate subfield (continuous bits in little-endian) of 4-byte
2773 value to host byte ordering.*/
2774 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2775 ( \
2776 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2777 BIT_LEN_MASK_32(__bitlen) \
2778 )
2779 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2780 ( \
2781 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2782 BIT_LEN_MASK_16(__bitlen) \
2783 )
2784 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2785 ( \
2786 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2787 BIT_LEN_MASK_8(__bitlen) \
2788 )
2789
2790 /* Description:
2791 * Mask subfield (continuous bits in little-endian) of 4-byte value
2792 * and return the result in 4-byte value in host byte ordering.
2793 */
2794 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2795 ( \
2796 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2797 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2798 )
2799 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2800 ( \
2801 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2802 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2803 )
2804 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2805 ( \
2806 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2807 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2808 )
2809
2810 /* Description:
2811 * Set subfield of little-endian 4-byte value to specified value.
2812 */
2813 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2814 *((u32 *)(__pstart)) = \
2815 ( \
2816 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2817 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2818 );
2819 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2820 *((u16 *)(__pstart)) = \
2821 ( \
2822 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2823 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2824 );
2825 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2826 *((u8 *)(__pstart)) = EF1BYTE \
2827 ( \
2828 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2829 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2830 );
2831
2832 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2833 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2834
2835 /****************************************
2836 mem access macro define end
2837 ****************************************/
2838
2839 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2840
2841 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2842 #define RTL_WATCH_DOG_TIME 2000
2843 #define MSECS(t) msecs_to_jiffies(t)
2844 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2845 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2846 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2847 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2848 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2849
2850 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2851 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2852 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2853 /*NIC halt, re-initialize hw parameters*/
2854 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2855 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2856 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2857 /*Always enable ASPM and Clock Req in initialization.*/
2858 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2859 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2860 #define RT_PS_LEVEL_ASPM BIT(7)
2861 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2862 #define RT_RF_LPS_DISALBE_2R BIT(30)
2863 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2864 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2865 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2866 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2867 (ppsc->cur_ps_level &= (~(_ps_flg)))
2868 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2869 (ppsc->cur_ps_level |= _ps_flg)
2870
2871 #define container_of_dwork_rtl(x, y, z) \
2872 container_of(to_delayed_work(x), y, z)
2873
2874 #define FILL_OCTET_STRING(_os, _octet, _len) \
2875 (_os).octet = (u8 *)(_octet); \
2876 (_os).length = (_len);
2877
2878 #define CP_MACADDR(des, src) \
2879 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2880 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2881 (des)[4] = (src)[4], (des)[5] = (src)[5])
2882
2883 #define LDPC_HT_ENABLE_RX BIT(0)
2884 #define LDPC_HT_ENABLE_TX BIT(1)
2885 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2886 #define LDPC_HT_CAP_TX BIT(3)
2887
2888 #define STBC_HT_ENABLE_RX BIT(0)
2889 #define STBC_HT_ENABLE_TX BIT(1)
2890 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2891 #define STBC_HT_CAP_TX BIT(3)
2892
2893 #define LDPC_VHT_ENABLE_RX BIT(0)
2894 #define LDPC_VHT_ENABLE_TX BIT(1)
2895 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2896 #define LDPC_VHT_CAP_TX BIT(3)
2897
2898 #define STBC_VHT_ENABLE_RX BIT(0)
2899 #define STBC_VHT_ENABLE_TX BIT(1)
2900 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2901 #define STBC_VHT_CAP_TX BIT(3)
2902
2903 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2904
2905 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2906
rtl_read_byte(struct rtl_priv * rtlpriv,u32 addr)2907 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2908 {
2909 return rtlpriv->io.read8_sync(rtlpriv, addr);
2910 }
2911
rtl_read_word(struct rtl_priv * rtlpriv,u32 addr)2912 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2913 {
2914 return rtlpriv->io.read16_sync(rtlpriv, addr);
2915 }
2916
rtl_read_dword(struct rtl_priv * rtlpriv,u32 addr)2917 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2918 {
2919 return rtlpriv->io.read32_sync(rtlpriv, addr);
2920 }
2921
rtl_write_byte(struct rtl_priv * rtlpriv,u32 addr,u8 val8)2922 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2923 {
2924 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2925
2926 if (rtlpriv->cfg->write_readback)
2927 rtlpriv->io.read8_sync(rtlpriv, addr);
2928 }
2929
rtl_write_word(struct rtl_priv * rtlpriv,u32 addr,u16 val16)2930 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2931 {
2932 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2933
2934 if (rtlpriv->cfg->write_readback)
2935 rtlpriv->io.read16_sync(rtlpriv, addr);
2936 }
2937
rtl_write_dword(struct rtl_priv * rtlpriv,u32 addr,u32 val32)2938 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2939 u32 addr, u32 val32)
2940 {
2941 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2942
2943 if (rtlpriv->cfg->write_readback)
2944 rtlpriv->io.read32_sync(rtlpriv, addr);
2945 }
2946
rtl_get_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)2947 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2948 u32 regaddr, u32 bitmask)
2949 {
2950 struct rtl_priv *rtlpriv = hw->priv;
2951
2952 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2953 }
2954
rtl_set_bbreg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)2955 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2956 u32 bitmask, u32 data)
2957 {
2958 struct rtl_priv *rtlpriv = hw->priv;
2959
2960 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2961 }
2962
rtl_get_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)2963 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2964 enum radio_path rfpath, u32 regaddr,
2965 u32 bitmask)
2966 {
2967 struct rtl_priv *rtlpriv = hw->priv;
2968
2969 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2970 }
2971
rtl_set_rfreg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)2972 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2973 enum radio_path rfpath, u32 regaddr,
2974 u32 bitmask, u32 data)
2975 {
2976 struct rtl_priv *rtlpriv = hw->priv;
2977
2978 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2979 }
2980
is_hal_stop(struct rtl_hal * rtlhal)2981 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2982 {
2983 return (_HAL_STATE_STOP == rtlhal->state);
2984 }
2985
set_hal_start(struct rtl_hal * rtlhal)2986 static inline void set_hal_start(struct rtl_hal *rtlhal)
2987 {
2988 rtlhal->state = _HAL_STATE_START;
2989 }
2990
set_hal_stop(struct rtl_hal * rtlhal)2991 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2992 {
2993 rtlhal->state = _HAL_STATE_STOP;
2994 }
2995
get_rf_type(struct rtl_phy * rtlphy)2996 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2997 {
2998 return rtlphy->rf_type;
2999 }
3000
rtl_get_hdr(struct sk_buff * skb)3001 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3002 {
3003 return (struct ieee80211_hdr *)(skb->data);
3004 }
3005
rtl_get_fc(struct sk_buff * skb)3006 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3007 {
3008 return rtl_get_hdr(skb)->frame_control;
3009 }
3010
rtl_get_tid_h(struct ieee80211_hdr * hdr)3011 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3012 {
3013 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3014 }
3015
rtl_get_tid(struct sk_buff * skb)3016 static inline u16 rtl_get_tid(struct sk_buff *skb)
3017 {
3018 return rtl_get_tid_h(rtl_get_hdr(skb));
3019 }
3020
get_sta(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * bssid)3021 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3022 struct ieee80211_vif *vif,
3023 const u8 *bssid)
3024 {
3025 return ieee80211_find_sta(vif, bssid);
3026 }
3027
rtl_find_sta(struct ieee80211_hw * hw,u8 * mac_addr)3028 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3029 u8 *mac_addr)
3030 {
3031 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3032 return ieee80211_find_sta(mac->vif, mac_addr);
3033 }
3034
3035 #endif
3036