Lines Matching full:buffers

7 data which is available in various CPU internal buffers by using asynchronous
39 data into temporary microarchitectural structures (buffers). The data in
40 those buffers can be forwarded to load operations as an optimization.
54 executed loads may read data from those internal buffers and pass it to dependent
58 Because the buffers are potentially shared between Hyper-Threads cross
63 which in turn potenitally leaks data stored in the buffers.
100    * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101      - The system tries to clear the buffers but the microcode might not support the operation.
102    * - 'Mitigation: Clear CPU buffers'
103      - The microcode has been updated to clear the buffers. TSX is still enabled.
117 without a guarantee that they clear the CPU buffers.
166                 system it will clear CPU buffers on ring transitions. On
216                                           buffers. Cross-thread attacks are still
230 buffers.  For platforms without TSX control (MSR_IA32_ARCH_CAPABILITIES.MDS_NO=0)
244                                      VERW is not guaranteed to clear buffers