Lines Matching +full:i +full:- +full:cache +full:- +full:size

9 as CPU cache coherence, but may have different performance. For example,
20  +------------------+     +------------------+
21  | Compute Node 0   +-----+ Compute Node 1   |
23  +--------+---------+     +--------+---------+
25  +--------+---------+     +--------+---------+
27  +------------------+     +--------+---------+
30 CPUs or separate memory I/O devices that can initiate memory requests.
35 performance when accessing a given memory target. Each initiator-target
47 	# symlinks -v /sys/devices/system/node/nodeX/access0/targets/
48 	relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
50 	# symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
51 	relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
77 	# tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
79 	|-- read_bandwidth
80 	|-- read_latency
81 	|-- write_bandwidth
82 	`-- write_latency
92 NUMA Cache
100 higher performing memory to transparently cache access to progressively
104 hierarchy. Each increasing cache level provides higher performing
106 cache provided by the system.
108 This numbering is different than CPU caches where the cache level (ex:
109 L1, L2, L3) uses the CPU-side view where each increased level is lower
110 performing. In contrast, the memory cache level is centric to the last
111 level memory, so the higher numbered cache level corresponds to  memory
114 The memory-side caches are not directly addressable by software. When
116 near memory cache if it is present. If it is not present, the system
118 cache level, or it reaches far memory.
121 to use the system. Software may optionally query the memory cache
127 When the kernel first registers a memory cache with a node, the kernel
133 a memory-side cache, or that information is not accessible to the kernel.
135 The attributes for each level of cache is provided under its cache
142 Each cache level's directory provides its attributes. For example, the
143 following shows a single cache level and the attributes available for
148 	|-- index1
149 	|   |-- indexing
150 	|   |-- line_size
151 	|   |-- size
152 	|   `-- write_policy
154 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
155 for any other indexed based, multi-way associativity.
157 The "line_size" is the number of bytes accessed from the next cache
160 The "size" is the number of bytes provided by this cache level.
162 The "write_policy" will be 0 for write-back, and non-zero for
163 write-through caching.
170 - Section 5.2.27