Lines Matching +full:cache +full:-
2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
81 split-tlb type setups).
84 page table modification for address space 'vma->vm_mm' for
87 'vma->vm_mm' for virtual address 'addr'.
97 "vma->vm_mm", in the software page tables.
100 For example, it could use this event to pre-load TLB
104 Next, we have the cache flushing interfaces. In general, when Linux
105 is changing an existing virtual-->physical mapping to a new value,
120 The cache level flush will always be first, because this allows
122 a virtual-->physical translation to exist for a virtual address
123 when that virtual address is flushed from the cache. The HyperSparc
126 The cache flushing routines below need only deal with cache flushing
129 indexed caches which must be flushed when virtual-->physical
140 the caches. That is, after running, there will be no cache
149 the caches. That is, after running, there will be no cache
162 addresses from the cache. After running, there will be no
163 entries in the cache for 'vma->vm_mm' for virtual addresses in
164 the range 'start' to 'end-1'.
171 sized regions from the cache, instead of having the kernel
178 from the cache. The 'vma' is the backing structure used by
180 address space is available via vma->vm_mm. Also, one may
181 test (vma->vm_flags & VM_EXEC) to see if this region is
182 executable (and thus could be in the 'instruction cache' in
183 "Harvard" type cache layouts).
188 the cache.
190 After running, there will be no entries in the cache for
191 'vma->vm_mm' for virtual address 'addr' which translates
202 After running, there will be no entries in the cache for
212 of (kernel) virtual addresses from the cache. After running,
213 there will be no entries in the cache for the kernel address
214 space for virtual addresses in the range 'start' to 'end-1'.
220 There exists another whole class of cpu cache issues which currently
222 The biggest problem is that of virtual aliasing in the data cache
225 Is your port susceptible to virtual aliasing in its D-cache?
226 Well, if your D-cache is virtually indexed, is larger in size than
227 PAGE_SIZE, and does not prevent multiple cache lines for the same
230 If your D-cache has this problem, first define asm/shmparam.h SHMLBA
232 addressed D-cache (or if the size is variable, the largest possible
242 Next, you have to solve the D-cache aliasing issue for all
247 physical page into its address space, by implication the D-cache
255 pages. It allows a port to efficiently avoid D-cache alias
269 If D-cache aliasing is not an issue, these two routines may
274 Any time the kernel writes to a page cache page, _OR_
275 the kernel is about to read from a page cache page and
281 This routine need only be called for page cache pages
284 handling vfs symlinks in the page cache need not call
287 The phrase "kernel writes to a page cache page" means,
289 that dirty data in that page at the page->virtual mapping
291 D-cache aliasing, to make sure these kernel stores are
299 If D-cache aliasing is not an issue, this routine may
302 There is a bit set aside in page->flags (PG_arch_1) as
315 page->mapping->i_mmap is an empty tree, just mark the architecture
337 Any necessary cache flushing or other coherency operations
339 instruction cache does not snoop cpu stores, it is very
340 likely that you will need to flush the instruction cache
352 the cache of the page at vmaddr.
364 the kernel cache for page (using page_address(page)).
392 flushes the kernel cache for a given virtual address range in
401 the cache for a given virtual address range in the vmap area
402 which prevents the processor from making the cache stale by