Lines Matching +full:num +full:- +full:cs
4 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5 "fsl,ls2085a-dspi"
7 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8 "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9 "fsl,ls1088a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
10 - reg : Offset and length of the register set for the device
11 - interrupts : Should contain SPI controller interrupt
12 - clocks: from common clock binding: handle to dspi clock.
13 - clock-names: from common clock binding: Shall be "dspi".
14 - pinctrl-0: pin control group to be used for this controller.
15 - pinctrl-names: must contain a "default" entry.
16 - spi-num-chipselects : the number of the chipselect signals.
17 - bus-num : the slave chip chipselect signal number.
20 - big-endian: If present the dspi device's registers are implemented
24 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
26 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "fsl,vf610-dspi";
38 clock-names = "dspi";
39 spi-num-chipselects = <5>;
40 bus-num = <0>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_dspi0_1>;
43 big-endian;
46 #address-cells = <1>;
47 #size-cells = <1>;
49 spi-max-frequency = <16000000>;
50 spi-cpol;
51 spi-cpha;
55 fsl,spi-cs-sck-delay = <100>;
56 fsl,spi-sck-cs-delay = <50>;