Lines Matching full:cpu

2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
54   instruction set state". For ARMv7-a, the driver checks furthermore if CPU
61   state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
62   in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
72 domain and the CPU domain.
80                      |    Debug |**|   CPU      |
92 For CPU domain, the different SoC designs have different power management
97   respect to CPU power domain, the CPU power domain can be controlled by
99   to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
100   of CPU power down. As result, this can ensure the CPU power domain is
112   is a recipe for disaster; so we need preventing CPU low power states at boot
120 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
149 firstly constraint CPU idle states before enable CPU debugging feature; so can
157 It is possible to disable CPU idle states by way of the PM QoS
172 Disable specific CPU's specific idle state from cpuidle sysfs (see
175   # echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
183   coresight-cpu-debug 850000.debug: CPU[0]:
184   coresight-cpu-debug 850000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
185   coresight-cpu-debug 850000.debug:  EDPCSR:  handle_IPI+0x174/0x1d8
186   coresight-cpu-debug 850000.debug:  EDCIDSR: 00000000
187 …coresight-cpu-debug 850000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
188   coresight-cpu-debug 852000.debug: CPU[1]:
189   coresight-cpu-debug 852000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
190   coresight-cpu-debug 852000.debug:  EDPCSR:  debug_notifier_call+0x23c/0x358
191   coresight-cpu-debug 852000.debug:  EDCIDSR: 00000000
192 …coresight-cpu-debug 852000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…