Lines Matching refs:ARM
2 config ARM
127 The ARM series is a line of low-power-consumption RISC chip designs
128 licensed by ARM Ltd and targeted at embedded applications and
129 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
130 manufactured, but legacy ARM-based PC hardware remains popular in
131 Europe. There is an ARM Linux project with a web page at
307 # The "ARM system type" choice list is ordered alphabetically by option
311 prompt "ARM system type"
770 bool "ARM MPS2 platform"
835 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
839 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
844 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
849 It does not affect the MPCore. This option enables the ARM Ltd.
853 bool "ARM errata: Stale prediction on replaced interworking branch"
857 r1p* erratum. If a code sequence containing an ARM/Thumb
862 executing the new code sequence in the incorrect ARM or Thumb state.
869 bool "ARM errata: Processor deadlock when a false hazard is created"
883 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
896 bool "ARM errata: DMB operation may be faulty"
909 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
924 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
935 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
947 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
961 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
972 bool "ARM errata: possible faulty MMU translations following an ASID switch"
983 bool "ARM errata: no automatic Store Buffer drain"
994 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1006 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1020 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1030 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1040 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1049 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1063 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1073 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1082 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1090 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1099 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1111 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1157 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1160 The v7 ARM states that all cache and branch predictor maintenance
1222 Support ARM cpu topology definition. The MPIDR register defines
1224 topology of an ARM System.
1245 This option enables support for the ARM snoop control unit
1253 This option enables support for the ARM architected timer
1258 This options enables support for the ARM timer and watchdog unit
1346 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1352 management operations described in ARM document number ARM DEN
1354 ARM processors").
1467 The ARM compiler inserts calls to __aeabi_idiv() and
1481 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1486 ARM ABI (aka EABI). This is only useful if you are using a user
1502 new (ARM EABI) one. It also provides a compatibility layer to
1504 in memory differs between the legacy ABI and the new ARM EABI
1534 The address space of ARM processors is only 4 Gigabytes large
1627 ARM processors cannot fetch/store information which is not
1629 address divisible by 4. On 32-bit ARM processors, these non-aligned
1688 bool "Xen guest support on ARM"
1689 depends on ARM && AEABI && OF
1699 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1985 to be enabled much earlier than we do on ARM, which is non-trivial.