Lines Matching refs:clks
72 clocks = <&clks IMX27_CLK_CPU_DIV>;
95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 <&clks IMX27_CLK_DMA_AHB_GATE>;
106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 <&clks IMX27_CLK_PER1_GATE>;
122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 <&clks IMX27_CLK_PER1_GATE>;
131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 <&clks IMX27_CLK_PER1_GATE>;
141 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
142 <&clks IMX27_CLK_PER1_GATE>;
150 clocks = <&clks IMX27_CLK_CKIL>,
151 <&clks IMX27_CLK_RTC_IPG_GATE>;
159 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
166 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
174 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
175 <&clks IMX27_CLK_PER1_GATE>;
184 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
185 <&clks IMX27_CLK_PER1_GATE>;
194 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
195 <&clks IMX27_CLK_PER1_GATE>;
204 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
205 <&clks IMX27_CLK_PER1_GATE>;
216 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
217 <&clks IMX27_CLK_PER2_GATE>;
228 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
229 <&clks IMX27_CLK_PER2_GATE>;
239 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
251 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
264 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
272 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
273 <&clks IMX27_CLK_PER2_GATE>;
284 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
285 <&clks IMX27_CLK_PER2_GATE>;
302 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
313 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
324 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
335 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
346 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
357 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
369 clocks = <&clks IMX27_CLK_DUMMY>;
380 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
381 <&clks IMX27_CLK_PER2_GATE>;
390 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
391 <&clks IMX27_CLK_PER1_GATE>;
399 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
400 <&clks IMX27_CLK_PER1_GATE>;
408 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
409 <&clks IMX27_CLK_PER1_GATE>;
418 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
419 <&clks IMX27_CLK_PER1_GATE>;
430 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
438 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
439 <&clks IMX27_CLK_PER2_GATE>;
450 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
451 <&clks IMX27_CLK_PER1_GATE>;
467 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
468 <&clks IMX27_CLK_LCDC_AHB_GATE>,
469 <&clks IMX27_CLK_PER3_GATE>;
478 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
479 <&clks IMX27_CLK_VPU_AHB_GATE>;
488 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
489 <&clks IMX27_CLK_USB_AHB_GATE>,
490 <&clks IMX27_CLK_USB_DIV>;
500 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
501 <&clks IMX27_CLK_USB_AHB_GATE>,
502 <&clks IMX27_CLK_USB_DIV>;
513 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
514 <&clks IMX27_CLK_USB_AHB_GATE>,
515 <&clks IMX27_CLK_USB_DIV>;
532 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
533 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
537 clks: ccm@10027000{ label
547 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
554 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
555 <&clks IMX27_CLK_FEC_AHB_GATE>;
567 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
576 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;