Lines Matching refs:clks

91 		clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 						 <&clks IMX5_CLK_DUMMY>,
124 						 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 						 <&clks IMX5_CLK_DUMMY>,
136 						 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 						 <&clks IMX5_CLK_UART3_PER_GATE>;
158 					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
159 						 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
171 					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
183 					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
184 						 <&clks IMX5_CLK_DUMMY>,
185 						 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
195 					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
196 						 <&clks IMX5_CLK_DUMMY>,
197 						 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
208 				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
217 				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
274 				clocks = <&clks IMX5_CLK_DUMMY>;
281 				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
282 					 <&clks IMX5_CLK_GPT_HF_GATE>;
300 				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
301 					 <&clks IMX5_CLK_PWM1_HF_GATE>;
310 				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
311 					 <&clks IMX5_CLK_PWM2_HF_GATE>;
320 				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
321 					 <&clks IMX5_CLK_UART1_PER_GATE>;
330 				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
331 					 <&clks IMX5_CLK_UART2_PER_GATE>;
342 			clks: ccm@53fd4000{  label
377 				clocks = <&clks IMX5_CLK_I2C3_GATE>;
385 				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
386 					 <&clks IMX5_CLK_UART4_PER_GATE>;
403 				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
404 					 <&clks IMX5_CLK_UART5_PER_GATE>;
412 				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
422 				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
423 					 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
432 				clocks = <&clks IMX5_CLK_SDMA_GATE>,
433 					 <&clks IMX5_CLK_AHB>;
445 				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
446 					 <&clks IMX5_CLK_CSPI_IPG_GATE>;
457 				clocks = <&clks IMX5_CLK_I2C2_GATE>;
467 				clocks = <&clks IMX5_CLK_I2C1_GATE>;
477 				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
495 				clocks = <&clks IMX5_CLK_FEC_GATE>,
496 					 <&clks IMX5_CLK_FEC_GATE>,
497 					 <&clks IMX5_CLK_FEC_GATE>;