Lines Matching refs:clks
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
130 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
140 clocks = <&clks IMX5_CLK_IPU_GATE>,
141 <&clks IMX5_CLK_IPU_DI0_GATE>,
142 <&clks IMX5_CLK_IPU_DI1_GATE>;
179 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
180 <&clks IMX5_CLK_DUMMY>,
181 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
190 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
191 <&clks IMX5_CLK_DUMMY>,
192 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
202 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
203 <&clks IMX5_CLK_UART3_PER_GATE>;
214 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
215 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
225 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
226 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
239 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
240 <&clks IMX5_CLK_DUMMY>,
241 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
251 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
252 <&clks IMX5_CLK_DUMMY>,
253 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
269 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
279 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
289 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
299 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
356 clocks = <&clks IMX5_CLK_DUMMY>;
364 clocks = <&clks IMX5_CLK_DUMMY>;
371 clocks = <&clks IMX5_CLK_DUMMY>;
379 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
380 <&clks IMX5_CLK_GPT_HF_GATE>;
393 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
394 <&clks IMX5_CLK_PWM1_HF_GATE>;
403 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
404 <&clks IMX5_CLK_PWM2_HF_GATE>;
413 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
414 <&clks IMX5_CLK_UART1_PER_GATE>;
423 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
424 <&clks IMX5_CLK_UART2_PER_GATE>;
435 clks: ccm@73fd4000{ label
459 clocks = <&clks IMX5_CLK_IIM_GATE>;
471 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
481 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
482 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
491 clocks = <&clks IMX5_CLK_SDMA_GATE>,
492 <&clks IMX5_CLK_AHB>;
504 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
505 <&clks IMX5_CLK_CSPI_IPG_GATE>;
516 clocks = <&clks IMX5_CLK_I2C2_GATE>;
526 clocks = <&clks IMX5_CLK_I2C1_GATE>;
535 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
536 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
548 clocks = <&clks IMX5_CLK_DUMMY>;
563 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
581 clocks = <&clks IMX5_CLK_NFC_GATE>;
589 clocks = <&clks IMX5_CLK_PATA_GATE>;
598 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
599 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
612 clocks = <&clks IMX5_CLK_FEC_GATE>,
613 <&clks IMX5_CLK_FEC_GATE>,
614 <&clks IMX5_CLK_FEC_GATE>;
623 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
624 <&clks IMX5_CLK_VPU_GATE>;
634 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
635 <&clks IMX5_CLK_SAHARA_IPG_GATE>;