Lines Matching refs:clks
56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
243 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
244 <&clks IMX5_CLK_DUMMY>,
245 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
255 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
256 <&clks IMX5_CLK_DUMMY>,
257 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
267 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
268 <&clks IMX5_CLK_UART3_PER_GATE>;
281 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
282 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
294 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
295 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
308 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
309 <&clks IMX5_CLK_DUMMY>,
310 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
320 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
321 <&clks IMX5_CLK_DUMMY>,
322 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
338 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
348 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
359 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
369 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
379 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
426 clocks = <&clks IMX5_CLK_DUMMY>;
434 clocks = <&clks IMX5_CLK_DUMMY>;
441 clocks = <&clks IMX5_CLK_DUMMY>;
449 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
450 <&clks IMX5_CLK_GPT_HF_GATE>;
458 clocks = <&clks IMX5_CLK_SRTC_GATE>;
477 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
478 <&clks IMX5_CLK_LDB_DI1_SEL>,
479 <&clks IMX5_CLK_IPU_DI0_SEL>,
480 <&clks IMX5_CLK_IPU_DI1_SEL>,
481 <&clks IMX5_CLK_LDB_DI0_GATE>,
482 <&clks IMX5_CLK_LDB_DI1_GATE>;
531 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
532 <&clks IMX5_CLK_PWM1_HF_GATE>;
541 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
542 <&clks IMX5_CLK_PWM2_HF_GATE>;
551 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
552 <&clks IMX5_CLK_UART1_PER_GATE>;
563 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
564 <&clks IMX5_CLK_UART2_PER_GATE>;
575 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
576 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
585 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
586 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
597 clks: ccm@53fd4000{ label
640 clocks = <&clks IMX5_CLK_I2C3_GATE>;
648 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
649 <&clks IMX5_CLK_UART4_PER_GATE>;
673 clocks = <&clks IMX5_CLK_IIM_GATE>;
680 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
681 <&clks IMX5_CLK_UART5_PER_GATE>;
696 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
706 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
707 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
716 clocks = <&clks IMX5_CLK_SDMA_GATE>,
717 <&clks IMX5_CLK_AHB>;
729 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
730 <&clks IMX5_CLK_CSPI_IPG_GATE>;
741 clocks = <&clks IMX5_CLK_I2C2_GATE>;
751 clocks = <&clks IMX5_CLK_I2C1_GATE>;
761 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
762 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
781 clocks = <&clks IMX5_CLK_NFC_GATE>;
791 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
792 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
805 clocks = <&clks IMX5_CLK_FEC_GATE>,
806 <&clks IMX5_CLK_FEC_GATE>,
807 <&clks IMX5_CLK_FEC_GATE>;
816 clocks = <&clks IMX5_CLK_TVE_GATE>,
817 <&clks IMX5_CLK_IPU_DI1_SEL>;
832 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
833 <&clks IMX5_CLK_VPU_GATE>;
843 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
844 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
852 clocks = <&clks IMX5_CLK_OCRAM>;