Lines Matching refs:clks
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
113 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
167 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
168 <&clks IMX6SLL_CLK_OSC>,
169 <&clks IMX6SLL_CLK_SPDIF>,
170 <&clks IMX6SLL_CLK_DUMMY>,
171 <&clks IMX6SLL_CLK_DUMMY>,
172 <&clks IMX6SLL_CLK_DUMMY>,
173 <&clks IMX6SLL_CLK_IPG>,
174 <&clks IMX6SLL_CLK_DUMMY>,
175 <&clks IMX6SLL_CLK_DUMMY>,
176 <&clks IMX6SLL_CLK_SPBA>;
191 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
192 <&clks IMX6SLL_CLK_ECSPI1>;
203 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
204 <&clks IMX6SLL_CLK_ECSPI2>;
215 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
216 <&clks IMX6SLL_CLK_ECSPI3>;
227 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
228 <&clks IMX6SLL_CLK_ECSPI4>;
240 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
241 <&clks IMX6SLL_CLK_UART4_SERIAL>;
253 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
254 <&clks IMX6SLL_CLK_UART1_SERIAL>;
266 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
267 <&clks IMX6SLL_CLK_UART2_SERIAL>;
279 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
280 <&clks IMX6SLL_CLK_SSI1>;
292 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
293 <&clks IMX6SLL_CLK_SSI2>;
305 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
306 <&clks IMX6SLL_CLK_SSI3>;
318 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
319 <&clks IMX6SLL_CLK_UART3_SERIAL>;
329 clocks = <&clks IMX6SLL_CLK_PWM1>,
330 <&clks IMX6SLL_CLK_PWM1>;
339 clocks = <&clks IMX6SLL_CLK_PWM2>,
340 <&clks IMX6SLL_CLK_PWM2>;
349 clocks = <&clks IMX6SLL_CLK_PWM3>,
350 <&clks IMX6SLL_CLK_PWM3>;
359 clocks = <&clks IMX6SLL_CLK_PWM4>,
360 <&clks IMX6SLL_CLK_PWM4>;
369 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
370 <&clks IMX6SLL_CLK_GPT_SERIAL>;
379 clocks = <&clks IMX6SLL_CLK_GPIO1>;
392 clocks = <&clks IMX6SLL_CLK_GPIO2>;
405 clocks = <&clks IMX6SLL_CLK_GPIO3>;
420 clocks = <&clks IMX6SLL_CLK_GPIO4>;
441 clocks = <&clks IMX6SLL_CLK_GPIO5>;
464 clocks = <&clks IMX6SLL_CLK_GPIO6>;
475 clocks = <&clks IMX6SLL_CLK_KPP>;
483 clocks = <&clks IMX6SLL_CLK_WDOG1>;
490 clocks = <&clks IMX6SLL_CLK_WDOG2>;
494 clks: clock-controller@20c4000 { label
503 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
504 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
539 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
549 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
616 clocks = <&clks IMX6SLL_CLK_DUMMY>,
617 <&clks IMX6SLL_CLK_CSI>,
618 <&clks IMX6SLL_CLK_DUMMY>;
627 clocks = <&clks IMX6SLL_CLK_IPG>,
628 <&clks IMX6SLL_CLK_SDMA>;
639 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
640 <&clks IMX6SLL_CLK_LCDIF_APB>,
641 <&clks IMX6SLL_CLK_DUMMY>;
652 clocks = <&clks IMX6SLL_CLK_DCP>;
669 clocks = <&clks IMX6SLL_CLK_USBOH3>;
684 clocks = <&clks IMX6SLL_CLK_USBOH3>;
704 clocks = <&clks IMX6SLL_CLK_USDHC1>,
705 <&clks IMX6SLL_CLK_USDHC1>,
706 <&clks IMX6SLL_CLK_USDHC1>;
718 clocks = <&clks IMX6SLL_CLK_USDHC2>,
719 <&clks IMX6SLL_CLK_USDHC2>,
720 <&clks IMX6SLL_CLK_USDHC2>;
732 clocks = <&clks IMX6SLL_CLK_USDHC3>,
733 <&clks IMX6SLL_CLK_USDHC3>,
734 <&clks IMX6SLL_CLK_USDHC3>;
748 clocks = <&clks IMX6SLL_CLK_I2C1>;
758 clocks = <&clks IMX6SLL_CLK_I2C2>;
768 clocks = <&clks IMX6SLL_CLK_I2C3>;
775 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
783 clocks = <&clks IMX6SLL_CLK_OCOTP>;
807 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
808 <&clks IMX6SLL_CLK_UART5_SERIAL>;