172 void cpu_icache_inval_page(unsigned long start)  in cpu_icache_inval_page()  argument
177 	end = start + PAGE_SIZE;  in cpu_icache_inval_page()
188 	} while (end != start);  in cpu_icache_inval_page()
192 void cpu_dcache_inval_page(unsigned long start)  in cpu_dcache_inval_page()  argument
197 	end = start + PAGE_SIZE;  in cpu_dcache_inval_page()
208 	} while (end != start);  in cpu_dcache_inval_page()
211 void cpu_dcache_wb_page(unsigned long start)  in cpu_dcache_wb_page()  argument
217 	end = start + PAGE_SIZE;  in cpu_dcache_wb_page()
228 	} while (end != start);  in cpu_dcache_wb_page()
233 void cpu_dcache_wbinval_page(unsigned long start)  in cpu_dcache_wbinval_page()  argument
238 	end = start + PAGE_SIZE;  in cpu_dcache_wbinval_page()
261 	} while (end != start);  in cpu_dcache_wbinval_page()
275 void cpu_icache_inval_range(unsigned long start, unsigned long end)  in cpu_icache_inval_range()  argument
281 	while (end > start) {  in cpu_icache_inval_range()
282 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start));  in cpu_icache_inval_range()
283 		start += line_size;  in cpu_icache_inval_range()
288 void cpu_dcache_inval_range(unsigned long start, unsigned long end)  in cpu_dcache_inval_range()  argument
294 	while (end > start) {  in cpu_dcache_inval_range()
295 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));  in cpu_dcache_inval_range()
296 		start += line_size;  in cpu_dcache_inval_range()
300 void cpu_dcache_wb_range(unsigned long start, unsigned long end)  in cpu_dcache_wb_range()  argument
307 	while (end > start) {  in cpu_dcache_wb_range()
308 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));  in cpu_dcache_wb_range()
309 		start += line_size;  in cpu_dcache_wb_range()
315 void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)  in cpu_dcache_wbinval_range()  argument
321 	while (end > start) {  in cpu_dcache_wbinval_range()
323 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));  in cpu_dcache_wbinval_range()
325 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));  in cpu_dcache_wbinval_range()
326 		start += line_size;  in cpu_dcache_wbinval_range()
331 void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)  in cpu_cache_wbinval_range()  argument
336 	align_start = start & ~(line_size - 1);  in cpu_cache_wbinval_range()
342 		align_start = start & ~(line_size - 1);  in cpu_cache_wbinval_range()
349 				   unsigned long start, unsigned long end,  in cpu_cache_wbinval_range_check()  argument
357 	start = start & ~(line_size - 1);  in cpu_cache_wbinval_range_check()
360 	if ((end - start) > (8 * PAGE_SIZE)) {  in cpu_cache_wbinval_range_check()
368 	t_start = (start + PAGE_SIZE) & PAGE_MASK;  in cpu_cache_wbinval_range_check()
371 	if ((start & PAGE_MASK) == t_end) {  in cpu_cache_wbinval_range_check()
372 		if (va_present(vma->vm_mm, start)) {  in cpu_cache_wbinval_range_check()
374 				cpu_dcache_wbinval_range(start, end);  in cpu_cache_wbinval_range_check()
376 				cpu_icache_inval_range(start, end);  in cpu_cache_wbinval_range_check()
381 	if (va_present(vma->vm_mm, start)) {  in cpu_cache_wbinval_range_check()
383 			cpu_dcache_wbinval_range(start, t_start);  in cpu_cache_wbinval_range_check()
385 			cpu_icache_inval_range(start, t_start);  in cpu_cache_wbinval_range_check()
407 static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)  in cpu_l2cache_op()  argument
410 		unsigned long p_start = __pa(start);  in cpu_l2cache_op()
434 #define cpu_l2cache_op(start,end,op) do { } while (0)  argument
439 void cpu_dma_wb_range(unsigned long start, unsigned long end)  in cpu_dma_wb_range()  argument
444 	start = start & (~(line_size - 1));  in cpu_dma_wb_range()
446 	if (unlikely(start == end))  in cpu_dma_wb_range()
450 	cpu_dcache_wb_range(start, end);  in cpu_dma_wb_range()
451 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);  in cpu_dma_wb_range()
456 void cpu_dma_inval_range(unsigned long start, unsigned long end)  in cpu_dma_inval_range()  argument
459 	unsigned long old_start = start;  in cpu_dma_inval_range()
463 	start = start & (~(line_size - 1));  in cpu_dma_inval_range()
465 	if (unlikely(start == end))  in cpu_dma_inval_range()
468 	if (start != old_start) {  in cpu_dma_inval_range()
469 		cpu_dcache_wbinval_range(start, start + line_size);  in cpu_dma_inval_range()
470 		cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL);  in cpu_dma_inval_range()
476 	cpu_dcache_inval_range(start, end);  in cpu_dma_inval_range()
477 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);  in cpu_dma_inval_range()
483 void cpu_dma_wbinval_range(unsigned long start, unsigned long end)  in cpu_dma_wbinval_range()  argument
488 	start = start & (~(line_size - 1));  in cpu_dma_wbinval_range()
490 	if (unlikely(start == end))  in cpu_dma_wbinval_range()
494 	cpu_dcache_wbinval_range(start, end);  in cpu_dma_wbinval_range()
495 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);  in cpu_dma_wbinval_range()