Lines Matching refs:pe
275 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag) in eeh_dump_pe_log() argument
280 eeh_pe_for_each_dev(pe, edev, tmp) in eeh_dump_pe_log()
297 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) in eeh_slot_error_detail() argument
317 if (!(pe->type & EEH_PE_PHB)) { in eeh_slot_error_detail()
320 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); in eeh_slot_error_detail()
334 eeh_ops->configure_bridge(pe); in eeh_slot_error_detail()
335 if (!(pe->state & EEH_PE_CFG_BLOCKED)) { in eeh_slot_error_detail()
336 eeh_pe_restore_bars(pe); in eeh_slot_error_detail()
339 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen); in eeh_slot_error_detail()
343 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); in eeh_slot_error_detail()
387 static int eeh_phb_check_failure(struct eeh_pe *pe) in eeh_phb_check_failure() argument
397 phb_pe = eeh_phb_pe_get(pe->phb); in eeh_phb_check_failure()
400 __func__, pe->phb->global_number); in eeh_phb_check_failure()
452 struct eeh_pe *pe, *parent_pe; in eeh_dev_check_failure() local
466 pe = eeh_dev_to_pe(edev); in eeh_dev_check_failure()
469 if (!pe) { in eeh_dev_check_failure()
475 if (!pe->addr && !pe->config_addr) { in eeh_dev_check_failure()
484 ret = eeh_phb_check_failure(pe); in eeh_dev_check_failure()
493 if (eeh_pe_passed(pe)) in eeh_dev_check_failure()
504 if (pe->state & EEH_PE_ISOLATED) { in eeh_dev_check_failure()
505 pe->check_count++; in eeh_dev_check_failure()
506 if (pe->check_count % EEH_MAX_FAILS == 0) { in eeh_dev_check_failure()
512 pe->check_count, in eeh_dev_check_failure()
529 ret = eeh_ops->get_state(pe, NULL); in eeh_dev_check_failure()
540 pe->false_positives++; in eeh_dev_check_failure()
550 parent_pe = pe->parent; in eeh_dev_check_failure()
559 pe = parent_pe; in eeh_dev_check_failure()
561 pe->phb->global_number, pe->addr, in eeh_dev_check_failure()
562 pe->phb->global_number, parent_pe->addr); in eeh_dev_check_failure()
575 eeh_pe_mark_isolated(pe); in eeh_dev_check_failure()
583 __func__, pe->phb->global_number, pe->addr); in eeh_dev_check_failure()
584 eeh_send_failure_event(pe); in eeh_dev_check_failure()
632 int eeh_pci_enable(struct eeh_pe *pe, int function) in eeh_pci_enable() argument
664 rc = eeh_ops->get_state(pe, NULL); in eeh_pci_enable()
679 rc = eeh_ops->set_option(pe, function); in eeh_pci_enable()
683 __func__, function, pe->phb->global_number, in eeh_pci_enable()
684 pe->addr, rc); in eeh_pci_enable()
688 rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); in eeh_pci_enable()
815 struct eeh_pe *pe = eeh_dev_to_pe(edev); in pcibios_set_pcie_reset_state() local
817 if (!pe) { in pcibios_set_pcie_reset_state()
825 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); in pcibios_set_pcie_reset_state()
826 eeh_unfreeze_pe(pe); in pcibios_set_pcie_reset_state()
827 if (!(pe->type & EEH_PE_VF)) in pcibios_set_pcie_reset_state()
828 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); in pcibios_set_pcie_reset_state()
829 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev); in pcibios_set_pcie_reset_state()
830 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); in pcibios_set_pcie_reset_state()
833 eeh_pe_mark_isolated(pe); in pcibios_set_pcie_reset_state()
834 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); in pcibios_set_pcie_reset_state()
835 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in pcibios_set_pcie_reset_state()
836 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); in pcibios_set_pcie_reset_state()
837 if (!(pe->type & EEH_PE_VF)) in pcibios_set_pcie_reset_state()
838 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); in pcibios_set_pcie_reset_state()
839 eeh_ops->reset(pe, EEH_RESET_HOT); in pcibios_set_pcie_reset_state()
842 eeh_pe_mark_isolated(pe); in pcibios_set_pcie_reset_state()
843 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true); in pcibios_set_pcie_reset_state()
844 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in pcibios_set_pcie_reset_state()
845 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev); in pcibios_set_pcie_reset_state()
846 if (!(pe->type & EEH_PE_VF)) in pcibios_set_pcie_reset_state()
847 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); in pcibios_set_pcie_reset_state()
848 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); in pcibios_set_pcie_reset_state()
851 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true); in pcibios_set_pcie_reset_state()
880 struct eeh_pe *pe; in eeh_pe_refreeze_passed() local
883 eeh_for_each_pe(root, pe) { in eeh_pe_refreeze_passed()
884 if (eeh_pe_passed(pe)) { in eeh_pe_refreeze_passed()
885 state = eeh_ops->get_state(pe, NULL); in eeh_pe_refreeze_passed()
889 pe->phb->global_number, pe->addr); in eeh_pe_refreeze_passed()
890 eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE); in eeh_pe_refreeze_passed()
908 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed) in eeh_pe_reset_full() argument
920 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); in eeh_pe_reset_full()
926 eeh_pe_state_mark(pe, reset_state); in eeh_pe_reset_full()
930 ret = eeh_pe_reset(pe, type, include_passed); in eeh_pe_reset_full()
932 ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE, in eeh_pe_reset_full()
937 state, pe->phb->global_number, pe->addr, i + 1); in eeh_pe_reset_full()
942 pe->phb->global_number, pe->addr, i + 1); in eeh_pe_reset_full()
945 state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); in eeh_pe_reset_full()
948 pe->phb->global_number, pe->addr); in eeh_pe_reset_full()
956 pe->phb->global_number, pe->addr, state, i + 1); in eeh_pe_reset_full()
963 eeh_pe_refreeze_passed(pe); in eeh_pe_reset_full()
965 eeh_pe_state_clear(pe, reset_state, true); in eeh_pe_reset_full()
1285 if (!edev || !edev->pdev || !edev->pe) { in eeh_remove_device()
1306 if (!(edev->pe->state & EEH_PE_KEEP)) in eeh_remove_device()
1324 int eeh_unfreeze_pe(struct eeh_pe *pe) in eeh_unfreeze_pe() argument
1328 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); in eeh_unfreeze_pe()
1331 __func__, ret, pe->phb->global_number, pe->addr); in eeh_unfreeze_pe()
1335 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA); in eeh_unfreeze_pe()
1338 __func__, ret, pe->phb->global_number, pe->addr); in eeh_unfreeze_pe()
1353 static int eeh_pe_change_owner(struct eeh_pe *pe) in eeh_pe_change_owner() argument
1361 ret = eeh_ops->get_state(pe, NULL); in eeh_pe_change_owner()
1370 eeh_pe_for_each_dev(pe, edev, tmp) { in eeh_pe_change_owner()
1389 return eeh_pe_reset_and_recover(pe); in eeh_pe_change_owner()
1393 ret = eeh_unfreeze_pe(pe); in eeh_pe_change_owner()
1395 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true); in eeh_pe_change_owner()
1421 if (!edev || !edev->pe) in eeh_dev_open()
1430 ret = eeh_pe_change_owner(edev->pe); in eeh_dev_open()
1435 atomic_inc(&edev->pe->pass_dev_cnt); in eeh_dev_open()
1465 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) in eeh_dev_release()
1469 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0); in eeh_dev_release()
1470 eeh_pe_change_owner(edev->pe); in eeh_dev_release()
1516 if (!edev || !edev->pe) in eeh_iommu_group_to_pe()
1519 return edev->pe; in eeh_iommu_group_to_pe()
1533 int eeh_pe_set_option(struct eeh_pe *pe, int option) in eeh_pe_set_option() argument
1538 if (!pe) in eeh_pe_set_option()
1549 ret = eeh_pe_change_owner(pe); in eeh_pe_set_option()
1564 ret = eeh_pci_enable(pe, option); in eeh_pe_set_option()
1583 int eeh_pe_get_state(struct eeh_pe *pe) in eeh_pe_get_state() argument
1589 if (!pe) in eeh_pe_get_state()
1601 if (pe->parent && in eeh_pe_get_state()
1602 !(pe->state & EEH_PE_REMOVED) && in eeh_pe_get_state()
1603 (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING))) in eeh_pe_get_state()
1606 result = eeh_ops->get_state(pe, NULL); in eeh_pe_get_state()
1626 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed) in eeh_pe_reenable_devices() argument
1632 eeh_pe_restore_bars(pe); in eeh_pe_reenable_devices()
1638 eeh_pe_for_each_dev(pe, edev, tmp) { in eeh_pe_reenable_devices()
1652 if (include_passed || !eeh_pe_passed(pe)) { in eeh_pe_reenable_devices()
1653 ret = eeh_unfreeze_pe(pe); in eeh_pe_reenable_devices()
1656 pe->phb->global_number, pe->addr); in eeh_pe_reenable_devices()
1658 eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed); in eeh_pe_reenable_devices()
1672 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed) in eeh_pe_reset() argument
1677 if (!pe) in eeh_pe_reset()
1685 ret = eeh_ops->reset(pe, option); in eeh_pe_reset()
1686 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed); in eeh_pe_reset()
1690 ret = eeh_pe_reenable_devices(pe, include_passed); in eeh_pe_reset()
1699 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in eeh_pe_reset()
1701 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED); in eeh_pe_reset()
1702 ret = eeh_ops->reset(pe, option); in eeh_pe_reset()
1722 int eeh_pe_configure(struct eeh_pe *pe) in eeh_pe_configure() argument
1727 if (!pe) in eeh_pe_configure()
1746 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, in eeh_pe_inject_err() argument
1750 if (!pe) in eeh_pe_inject_err()
1765 return eeh_ops->err_inject(pe, type, func, addr, mask); in eeh_pe_inject_err()
1825 struct eeh_pe *pe; in eeh_force_recover_write() local
1853 pe = eeh_pe_get(hose, pe_no, 0); in eeh_force_recover_write()
1854 if (!pe) in eeh_force_recover_write()
1864 __eeh_send_failure_event(pe); in eeh_force_recover_write()