Lines Matching refs:wp
108 u32 wp[2]; member
199 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
200 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
201 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
202 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
203 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
204 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
209 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
210 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
211 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
220 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
222 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
225 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
234 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
238 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
242 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
276 vc.wp[1] = 0; in do_spe_mathemu()
280 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
300 vc.wp[1] = 0; in do_spe_mathemu()
303 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
311 vc.wp[1] = 0; in do_spe_mathemu()
314 FP_TO_INT_S(vc.wp[1], SB, 32, in do_spe_mathemu()
327 FP_PACK_SP(vc.wp + 1, SR); in do_spe_mathemu()
406 vc.wp[1] = 0; in do_spe_mathemu()
410 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
418 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
441 vc.wp[1] = 0; in do_spe_mathemu()
444 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
452 vc.wp[1] = 0; in do_spe_mathemu()
455 FP_TO_INT_D(vc.wp[1], DB, 32, in do_spe_mathemu()
493 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
494 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
496 FP_UNPACK_SP(SB0, vb.wp); in do_spe_mathemu()
497 FP_UNPACK_SP(SB1, vb.wp + 1); in do_spe_mathemu()
500 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
501 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
516 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; in do_spe_mathemu()
517 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
521 vc.wp[0] = va.wp[0] | SIGN_BIT_S; in do_spe_mathemu()
522 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
526 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; in do_spe_mathemu()
527 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
565 vc.wp[0] = 0; in do_spe_mathemu()
569 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
573 vc.wp[1] = 0; in do_spe_mathemu()
577 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
585 vc.wp[0] = 0; in do_spe_mathemu()
588 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
592 vc.wp[1] = 0; in do_spe_mathemu()
595 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
603 vc.wp[0] = 0; in do_spe_mathemu()
606 FP_TO_INT_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
610 vc.wp[1] = 0; in do_spe_mathemu()
613 FP_TO_INT_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
629 FP_PACK_SP(vc.wp, SR0); in do_spe_mathemu()
630 FP_PACK_SP(vc.wp + 1, SR1); in do_spe_mathemu()
681 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
682 regs->gpr[fc] = vc.wp[1]; in do_spe_mathemu()
687 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
688 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
689 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
753 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
754 fgpr.wp[1] = regs->gpr[fc]; in speround_handler()
787 if (fgpr.wp[1] == 0) in speround_handler()
795 if (fgpr.wp[1] == 0) in speround_handler()
797 if (fgpr.wp[0] == 0) in speround_handler()
806 if (fgpr.wp[1] == 0) in speround_handler()
815 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
824 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
828 fgpr.wp[1]++; /* Z < 0, choose Z2 */ in speround_handler()
830 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
841 fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
848 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
856 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ in speround_handler()
858 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ in speround_handler()
862 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ in speround_handler()
864 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ in speround_handler()
868 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ in speround_handler()
870 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ in speround_handler()
879 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
880 regs->gpr[fc] = fgpr.wp[1]; in speround_handler()
882 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()