384 #define VIRT_CTR(stagger, i) ((i) + ((num_counters) * (stagger)))  argument
390 	int i;  in p4_shutdown()  local
392 	for (i = 0; i < num_counters; ++i) {  in p4_shutdown()
393 		if (msrs->counters[i].addr)  in p4_shutdown()
394 			release_perfctr_nmi(msrs->counters[i].addr);  in p4_shutdown()
401 	for (i = num_counters; i < num_controls; ++i) {  in p4_shutdown()
402 		if (msrs->controls[i].addr)  in p4_shutdown()
403 			release_evntsel_nmi(msrs->controls[i].addr);  in p4_shutdown()
409 	unsigned int i;  in p4_fill_in_addresses()  local
416 	for (i = 0; i < num_counters; ++i) {  in p4_fill_in_addresses()
417 		addr = p4_counters[VIRT_CTR(stag, i)].counter_address;  in p4_fill_in_addresses()
418 		cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address;  in p4_fill_in_addresses()
420 			msrs->counters[i].addr = addr;  in p4_fill_in_addresses()
421 			msrs->controls[i].addr = cccraddr;  in p4_fill_in_addresses()
427 	     addr < MSR_P4_IQ_ESCR0; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
429 			msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
436 		     addr <= MSR_P4_BSU_ESCR1; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
438 				msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
442 		     addr <= MSR_P4_IQ_ESCR1; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
444 				msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
449 	     addr <= MSR_P4_SSU_ESCR0; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
451 			msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
455 	     addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
457 			msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
461 	     addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) {  in p4_fill_in_addresses()
463 			msrs->controls[i].addr = addr;  in p4_fill_in_addresses()
471 			msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;  in p4_fill_in_addresses()
473 			msrs->controls[i++].addr = MSR_P4_CRU_ESCR4;  in p4_fill_in_addresses()
479 			msrs->controls[i++].addr = MSR_P4_CRU_ESCR4;  in p4_fill_in_addresses()
485 			msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;  in p4_fill_in_addresses()
486 			msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;  in p4_fill_in_addresses()
490 	for (i = 0; i < num_counters; ++i) {  in p4_fill_in_addresses()
491 		if (!counter_config[i].enabled)  in p4_fill_in_addresses()
493 		if (msrs->controls[i].addr)  in p4_fill_in_addresses()
495 		op_x86_warn_reserved(i);  in p4_fill_in_addresses()
506 	int i;  in pmc_setup_one_p4_counter()  local
530 	for (i = 0; i < maxbind; i++) {  in pmc_setup_one_p4_counter()
531 		if (ev->bindings[i].virt_counter & counter_bit) {  in pmc_setup_one_p4_counter()
534 			rdmsr(ev->bindings[i].escr_address, escr, high);  in pmc_setup_one_p4_counter()
545 			wrmsr(ev->bindings[i].escr_address, escr, high);  in pmc_setup_one_p4_counter()
572 	unsigned int i;  in p4_setup_ctrs()  local
585 	for (i = 0; i < num_counters; i++) {  in p4_setup_ctrs()
586 		if (unlikely(!msrs->controls[i].addr))  in p4_setup_ctrs()
588 		rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_setup_ctrs()
591 		wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_setup_ctrs()
595 	for (i = num_counters; i < num_controls; i++) {  in p4_setup_ctrs()
596 		if (unlikely(!msrs->controls[i].addr))  in p4_setup_ctrs()
598 		wrmsr(msrs->controls[i].addr, 0, 0);  in p4_setup_ctrs()
602 	for (i = 0; i < num_counters; ++i) {  in p4_setup_ctrs()
603 		if (counter_config[i].enabled && msrs->controls[i].addr) {  in p4_setup_ctrs()
604 			reset_value[i] = counter_config[i].count;  in p4_setup_ctrs()
605 			pmc_setup_one_p4_counter(i);  in p4_setup_ctrs()
606 			wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address,  in p4_setup_ctrs()
607 			       -(u64)counter_config[i].count);  in p4_setup_ctrs()
609 			reset_value[i] = 0;  in p4_setup_ctrs()
619 	int i;  in p4_check_ctrs()  local
623 	for (i = 0; i < num_counters; ++i) {  in p4_check_ctrs()
625 		if (!reset_value[i])  in p4_check_ctrs()
645 		real = VIRT_CTR(stag, i);  in p4_check_ctrs()
650 			oprofile_add_sample(regs, i);  in p4_check_ctrs()
652 			       -(u64)reset_value[i]);  in p4_check_ctrs()
656 			       -(u64)reset_value[i]);  in p4_check_ctrs()
671 	int i;  in p4_start()  local
675 	for (i = 0; i < num_counters; ++i) {  in p4_start()
676 		if (!reset_value[i])  in p4_start()
678 		rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_start()
680 		wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_start()
688 	int i;  in p4_stop()  local
692 	for (i = 0; i < num_counters; ++i) {  in p4_stop()
693 		if (!reset_value[i])  in p4_stop()
695 		rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_stop()
697 		wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);  in p4_stop()