Lines Matching refs:mmio_base
234 void __iomem *mmio_base; member
268 return hpriv->mmio_base + ap->port_no * PORT_SIZE; in inic_port_base()
426 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); in inic_interrupt()
754 static int init_controller(void __iomem *mmio_base, u16 hctl) in init_controller() argument
764 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); in init_controller()
765 readw(mmio_base + HOST_CTL); /* flush */ in init_controller()
769 val = readw(mmio_base + HOST_CTL); in init_controller()
779 void __iomem *port_base = mmio_base + i * PORT_SIZE; in init_controller()
786 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); in init_controller()
787 val = readw(mmio_base + HOST_IRQ_MASK); in init_controller()
789 writew(val, mmio_base + HOST_IRQ_MASK); in init_controller()
806 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); in inic_pci_device_resume()
854 hpriv->mmio_base = iomap[mmio_bar]; in inic_init_one()
855 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL); in inic_init_one()
871 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl); in inic_init_one()