Lines Matching refs:divby4
650 int divby4; in si5351_msynth_round_rate() local
662 divby4 = 0; in si5351_msynth_round_rate()
664 divby4 = 1; in si5351_msynth_round_rate()
672 if (divby4 == 0) { in si5351_msynth_round_rate()
697 if (divby4) { in si5351_msynth_round_rate()
699 divby4 = 0; in si5351_msynth_round_rate()
731 if (divby4) { in si5351_msynth_round_rate()
749 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate()
761 int divby4 = 0; in si5351_msynth_set_rate() local
767 divby4 = 1; in si5351_msynth_set_rate()
773 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); in si5351_msynth_set_rate()
783 divby4, parent_rate, rate); in si5351_msynth_set_rate()