Lines Matching refs:STM32F4_RCC_CFGR
29 #define STM32F4_RCC_CFGR 0x08 macro
424 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
436 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
1186 STM32F4_RCC_CFGR, 23, 1,
1213 STM32F4_RCC_CFGR, 23, 1,
1258 STM32F4_RCC_CFGR, 23, 1,
1404 STM32F4_RCC_CFGR, 23, 1,
1788 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock); in stm32f4_rcc_init()
1791 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
1795 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
1801 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
1852 0, base + STM32F4_RCC_CFGR, 16, 5, 0, in stm32f4_rcc_init()