Lines Matching refs:base
63 void __iomem *base; in imx7ulp_clk_scg1_init() local
83 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
84 WARN_ON(!base); in imx7ulp_clk_scg1_init()
87 …clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_… in imx7ulp_clk_scg1_init()
88 …clks[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_… in imx7ulp_clk_scg1_init()
91 …clks[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0… in imx7ulp_clk_scg1_init()
92 …clks[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0… in imx7ulp_clk_scg1_init()
95 clks[IMX7ULP_CLK_APLL] = imx_clk_pllv4("apll", "apll_pre_div", base + 0x500); in imx7ulp_clk_scg1_init()
96 clks[IMX7ULP_CLK_SPLL] = imx_clk_pllv4("spll", "spll_pre_div", base + 0x600); in imx7ulp_clk_scg1_init()
99 clks[IMX7ULP_CLK_APLL_PFD0] = imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); in imx7ulp_clk_scg1_init()
100 clks[IMX7ULP_CLK_APLL_PFD1] = imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1); in imx7ulp_clk_scg1_init()
101 clks[IMX7ULP_CLK_APLL_PFD2] = imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2); in imx7ulp_clk_scg1_init()
102 clks[IMX7ULP_CLK_APLL_PFD3] = imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3); in imx7ulp_clk_scg1_init()
105 clks[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0); in imx7ulp_clk_scg1_init()
106 clks[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1); in imx7ulp_clk_scg1_init()
107 clks[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2); in imx7ulp_clk_scg1_init()
108 clks[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3); in imx7ulp_clk_scg1_init()
111 …clks[IMX7ULP_CLK_APLL_PFD_SEL] = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pf… in imx7ulp_clk_scg1_init()
112 …clks[IMX7ULP_CLK_SPLL_PFD_SEL] = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pf… in imx7ulp_clk_scg1_init()
113 …clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY… in imx7ulp_clk_scg1_init()
114 …clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY… in imx7ulp_clk_scg1_init()
116 …LK] = imx_clk_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, u… in imx7ulp_clk_scg1_init()
119 …clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(sc… in imx7ulp_clk_scg1_init()
120 …clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, A… in imx7ulp_clk_scg1_init()
121 …clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(ni… in imx7ulp_clk_scg1_init()
122 …clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SI… in imx7ulp_clk_scg1_init()
124 …clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, C… in imx7ulp_clk_scg1_init()
125 …clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base… in imx7ulp_clk_scg1_init()
127 …mx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, in imx7ulp_clk_scg1_init()
130 …clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4,… in imx7ulp_clk_scg1_init()
131 …clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4,… in imx7ulp_clk_scg1_init()
132 …clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic0_clk", base + 0x40,… in imx7ulp_clk_scg1_init()
134 clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4); in imx7ulp_clk_scg1_init()
136 …clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, … in imx7ulp_clk_scg1_init()
138 …clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, … in imx7ulp_clk_scg1_init()
151 void __iomem *base; in imx7ulp_clk_pcc2_init() local
163 base = of_iomap(np, 0); in imx7ulp_clk_pcc2_init()
164 WARN_ON(!base); in imx7ulp_clk_pcc2_init()
166 clks[IMX7ULP_CLK_DMA1] = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30); in imx7ulp_clk_pcc2_init()
167 clks[IMX7ULP_CLK_RGPIO2P1] = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30); in imx7ulp_clk_pcc2_init()
168 clks[IMX7ULP_CLK_DMA_MUX1] = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30); in imx7ulp_clk_pcc2_init()
169 clks[IMX7ULP_CLK_CAAM] = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30); in imx7ulp_clk_pcc2_init()
170 …composite("lptpm4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); in imx7ulp_clk_pcc2_init()
171 …composite("lptpm5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); in imx7ulp_clk_pcc2_init()
172 …composite("lpit1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); in imx7ulp_clk_pcc2_init()
173 …composite("lpspi2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4); in imx7ulp_clk_pcc2_init()
174 …composite("lpspi3", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8); in imx7ulp_clk_pcc2_init()
175 …composite("lpi2c4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac); in imx7ulp_clk_pcc2_init()
176 …composite("lpi2c5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0); in imx7ulp_clk_pcc2_init()
177 …composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4); in imx7ulp_clk_pcc2_init()
178 …composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8); in imx7ulp_clk_pcc2_init()
179 …composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4); in imx7ulp_clk_pcc2_init()
180 …mposite("usb0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xcc); in imx7ulp_clk_pcc2_init()
181 …mposite("usb1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xd0); in imx7ulp_clk_pcc2_init()
182 clks[IMX7ULP_CLK_USB_PHY] = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xd4, 30); in imx7ulp_clk_pcc2_init()
183 …mposite("usdhc0", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xdc); in imx7ulp_clk_pcc2_init()
184 …mposite("usdhc1", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xe0); in imx7ulp_clk_pcc2_init()
185 …composite("wdg1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xf4); in imx7ulp_clk_pcc2_init()
186 …omposite("sdg2", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0x10c); in imx7ulp_clk_pcc2_init()
206 void __iomem *base; in imx7ulp_clk_pcc3_init() local
218 base = of_iomap(np, 0); in imx7ulp_clk_pcc3_init()
219 WARN_ON(!base); in imx7ulp_clk_pcc3_init()
221 …composite("lptpm6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84); in imx7ulp_clk_pcc3_init()
222 …composite("lptpm7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88); in imx7ulp_clk_pcc3_init()
225 base + 0xac, 30, 0, &imx_ccm_lock); in imx7ulp_clk_pcc3_init()
226 …composite("lpi2c6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90); in imx7ulp_clk_pcc3_init()
227 …composite("lpi2c7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94); in imx7ulp_clk_pcc3_init()
228 …composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98); in imx7ulp_clk_pcc3_init()
229 …composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c); in imx7ulp_clk_pcc3_init()
230 …composite("dsi", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true, true, base + 0xa4); in imx7ulp_clk_pcc3_init()
231 …mposite("lcdif", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true, true, base + 0xa8); in imx7ulp_clk_pcc3_init()
233 clks[IMX7ULP_CLK_VIU] = imx_clk_hw_gate("viu", "nic1_clk", base + 0xa0, 30); in imx7ulp_clk_pcc3_init()
234 clks[IMX7ULP_CLK_PCTLC] = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30); in imx7ulp_clk_pcc3_init()
235 clks[IMX7ULP_CLK_PCTLD] = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30); in imx7ulp_clk_pcc3_init()
236 clks[IMX7ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30); in imx7ulp_clk_pcc3_init()
237 clks[IMX7ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30); in imx7ulp_clk_pcc3_init()
239 …posite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); in imx7ulp_clk_pcc3_init()
240 …posite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); in imx7ulp_clk_pcc3_init()
260 void __iomem *base; in imx7ulp_clk_smc1_init() local
271 base = of_iomap(np, 0); in imx7ulp_clk_smc1_init()
272 WARN_ON(!base); in imx7ulp_clk_smc1_init()
274 …clks[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_se… in imx7ulp_clk_smc1_init()