113 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,  in crystalcove_update_irq_mask()  argument
119 	if (cg->set_irq_mask)  in crystalcove_update_irq_mask()
120 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);  in crystalcove_update_irq_mask()
122 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);  in crystalcove_update_irq_mask()
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)  in crystalcove_update_irq_ctrl()  argument
129 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);  in crystalcove_update_irq_ctrl()
134 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dir_in()  local
140 	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);  in crystalcove_gpio_dir_in()
146 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dir_out()  local
152 	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);  in crystalcove_gpio_dir_out()
157 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_get()  local
164 	ret = regmap_read(cg->regmap, reg, &val);  in crystalcove_gpio_get()
174 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_set()  local
181 		regmap_update_bits(cg->regmap, reg, 1, 1);  in crystalcove_gpio_set()
183 		regmap_update_bits(cg->regmap, reg, 1, 0);  in crystalcove_gpio_set()
188 	struct crystalcove_gpio *cg =  in crystalcove_irq_type()  local
196 		cg->intcnt_value = CTLI_INTCNT_DIS;  in crystalcove_irq_type()
199 		cg->intcnt_value = CTLI_INTCNT_BE;  in crystalcove_irq_type()
202 		cg->intcnt_value = CTLI_INTCNT_PE;  in crystalcove_irq_type()
205 		cg->intcnt_value = CTLI_INTCNT_NE;  in crystalcove_irq_type()
211 	cg->update |= UPDATE_IRQ_TYPE;  in crystalcove_irq_type()
218 	struct crystalcove_gpio *cg =  in crystalcove_bus_lock()  local
221 	mutex_lock(&cg->buslock);  in crystalcove_bus_lock()
226 	struct crystalcove_gpio *cg =  in crystalcove_bus_sync_unlock()  local
230 	if (cg->update & UPDATE_IRQ_TYPE)  in crystalcove_bus_sync_unlock()
231 		crystalcove_update_irq_ctrl(cg, gpio);  in crystalcove_bus_sync_unlock()
232 	if (cg->update & UPDATE_IRQ_MASK)  in crystalcove_bus_sync_unlock()
233 		crystalcove_update_irq_mask(cg, gpio);  in crystalcove_bus_sync_unlock()
234 	cg->update = 0;  in crystalcove_bus_sync_unlock()
236 	mutex_unlock(&cg->buslock);  in crystalcove_bus_sync_unlock()
241 	struct crystalcove_gpio *cg =  in crystalcove_irq_unmask()  local
245 		cg->set_irq_mask = false;  in crystalcove_irq_unmask()
246 		cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_unmask()
252 	struct crystalcove_gpio *cg =  in crystalcove_irq_mask()  local
256 		cg->set_irq_mask = true;  in crystalcove_irq_mask()
257 		cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_mask()
273 	struct crystalcove_gpio *cg = data;  in crystalcove_gpio_irq_handler()  local
279 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||  in crystalcove_gpio_irq_handler()
280 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))  in crystalcove_gpio_irq_handler()
283 	regmap_write(cg->regmap, GPIO0IRQ, p0);  in crystalcove_gpio_irq_handler()
284 	regmap_write(cg->regmap, GPIO1IRQ, p1);  in crystalcove_gpio_irq_handler()
289 		virq = irq_find_mapping(cg->chip.irq.domain, gpio);  in crystalcove_gpio_irq_handler()
299 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);  in crystalcove_gpio_dbg_show()  local
304 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);  in crystalcove_gpio_dbg_show()
305 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);  in crystalcove_gpio_dbg_show()
306 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,  in crystalcove_gpio_dbg_show()
308 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,  in crystalcove_gpio_dbg_show()
310 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,  in crystalcove_gpio_dbg_show()
329 	struct crystalcove_gpio *cg;  in crystalcove_gpio_probe()  local
337 	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);  in crystalcove_gpio_probe()
338 	if (!cg)  in crystalcove_gpio_probe()
341 	platform_set_drvdata(pdev, cg);  in crystalcove_gpio_probe()
343 	mutex_init(&cg->buslock);  in crystalcove_gpio_probe()
344 	cg->chip.label = KBUILD_MODNAME;  in crystalcove_gpio_probe()
345 	cg->chip.direction_input = crystalcove_gpio_dir_in;  in crystalcove_gpio_probe()
346 	cg->chip.direction_output = crystalcove_gpio_dir_out;  in crystalcove_gpio_probe()
347 	cg->chip.get = crystalcove_gpio_get;  in crystalcove_gpio_probe()
348 	cg->chip.set = crystalcove_gpio_set;  in crystalcove_gpio_probe()
349 	cg->chip.base = -1;  in crystalcove_gpio_probe()
350 	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;  in crystalcove_gpio_probe()
351 	cg->chip.can_sleep = true;  in crystalcove_gpio_probe()
352 	cg->chip.parent = dev;  in crystalcove_gpio_probe()
353 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;  in crystalcove_gpio_probe()
354 	cg->regmap = pmic->regmap;  in crystalcove_gpio_probe()
356 	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);  in crystalcove_gpio_probe()
362 	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,  in crystalcove_gpio_probe()
366 				      IRQF_ONESHOT, KBUILD_MODNAME, cg);  in crystalcove_gpio_probe()
373 	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);  in crystalcove_gpio_probe()
380 	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);  in crystalcove_gpio_remove()  local
384 		free_irq(irq, cg);  in crystalcove_gpio_remove()