122 	void __iomem *base_addr;  member
227 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
230 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
235 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
238 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
243 		data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
283 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
313 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
315 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
342 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
344 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
347 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
349 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
373 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_get_direction()
395 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
416 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
436 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
487 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
489 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
491 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
526 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
528 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
530 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
642 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
644 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
658 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
661 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
663 		gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
665 		gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
668 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
671 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
674 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
684 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_restore_context()
687 			       gpio->base_addr +  in zynq_gpio_restore_context()
690 			       gpio->base_addr +  in zynq_gpio_restore_context()
693 			       gpio->base_addr +  in zynq_gpio_restore_context()
696 			       gpio->base_addr +  in zynq_gpio_restore_context()
699 			       gpio->base_addr +  in zynq_gpio_restore_context()
702 			       gpio->base_addr +  in zynq_gpio_restore_context()
705 			       gpio->base_addr +  in zynq_gpio_restore_context()
850 	gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);  in zynq_gpio_probe()
851 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
852 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
893 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()