699 	u32 num_heads;     /* number of active crtcs */  member
892 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +  in dce_v10_0_latency_watermark()
893 		(wm->num_heads * cursor_line_pair_return_time);  in dce_v10_0_latency_watermark()
899 	if (wm->num_heads == 0)  in dce_v10_0_latency_watermark()
913 	b.full = dfixed_const(wm->num_heads);  in dce_v10_0_latency_watermark()
948 	    (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))  in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
968 	    (dce_v10_0_available_bandwidth(wm) / wm->num_heads))  in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1022 					u32 lb_size, u32 num_heads)  in dce_v10_0_program_watermarks()  argument
1031 	if (amdgpu_crtc->base.enabled && num_heads && mode) {  in dce_v10_0_program_watermarks()
1063 		wm_high.num_heads = num_heads;  in dce_v10_0_program_watermarks()
1102 		wm_low.num_heads = num_heads;  in dce_v10_0_program_watermarks()
1155 	u32 num_heads = 0, lb_size;  in dce_v10_0_bandwidth_update()  local
1162 			num_heads++;  in dce_v10_0_bandwidth_update()
1168 					    lb_size, num_heads);  in dce_v10_0_bandwidth_update()