Lines Matching refs:gfx
800 adev->gfx.scratch.num_reg = 8; in gfx_v9_0_scratch_init()
801 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_scratch_init()
802 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; in gfx_v9_0_scratch_init()
934 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
935 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
936 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
937 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
938 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
939 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
940 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
941 adev->gfx.rlc_fw = NULL; in gfx_v9_0_free_microcode()
942 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
943 adev->gfx.mec_fw = NULL; in gfx_v9_0_free_microcode()
944 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_free_microcode()
945 adev->gfx.mec2_fw = NULL; in gfx_v9_0_free_microcode()
947 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
954 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_ext_microcode()
955 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
956 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
957 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v9_0_init_rlc_ext_microcode()
958 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v9_0_init_rlc_ext_microcode()
959 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
960 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
961 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
962 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v9_0_init_rlc_ext_microcode()
963 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in gfx_v9_0_init_rlc_ext_microcode()
964 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in gfx_v9_0_init_rlc_ext_microcode()
965 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
966 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in gfx_v9_0_init_rlc_ext_microcode()
967 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v9_0_init_rlc_ext_microcode()
973 adev->gfx.me_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
974 adev->gfx.mec_fw_write_wait = false; in gfx_v9_0_check_fw_write_wait()
976 if ((adev->gfx.mec_fw_version < 0x000001a5) || in gfx_v9_0_check_fw_write_wait()
977 (adev->gfx.mec_feature_version < 46) || in gfx_v9_0_check_fw_write_wait()
978 (adev->gfx.pfp_fw_version < 0x000000b7) || in gfx_v9_0_check_fw_write_wait()
979 (adev->gfx.pfp_feature_version < 46)) in gfx_v9_0_check_fw_write_wait()
985 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
986 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
987 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
988 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
989 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
991 if ((adev->gfx.mec_fw_version >= 0x00000193) && in gfx_v9_0_check_fw_write_wait()
992 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
993 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
996 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
997 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
998 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
999 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1000 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1002 if ((adev->gfx.mec_fw_version >= 0x00000196) && in gfx_v9_0_check_fw_write_wait()
1003 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1004 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1007 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1008 (adev->gfx.me_feature_version >= 44) && in gfx_v9_0_check_fw_write_wait()
1009 (adev->gfx.pfp_fw_version >= 0x000000b2) && in gfx_v9_0_check_fw_write_wait()
1010 (adev->gfx.pfp_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1011 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1013 if ((adev->gfx.mec_fw_version >= 0x00000197) && in gfx_v9_0_check_fw_write_wait()
1014 (adev->gfx.mec_feature_version >= 44)) in gfx_v9_0_check_fw_write_wait()
1015 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1018 if ((adev->gfx.me_fw_version >= 0x0000009c) && in gfx_v9_0_check_fw_write_wait()
1019 (adev->gfx.me_feature_version >= 42) && in gfx_v9_0_check_fw_write_wait()
1020 (adev->gfx.pfp_fw_version >= 0x000000b1) && in gfx_v9_0_check_fw_write_wait()
1021 (adev->gfx.pfp_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1022 adev->gfx.me_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1024 if ((adev->gfx.mec_fw_version >= 0x00000192) && in gfx_v9_0_check_fw_write_wait()
1025 (adev->gfx.mec_feature_version >= 42)) in gfx_v9_0_check_fw_write_wait()
1026 adev->gfx.mec_fw_write_wait = true; in gfx_v9_0_check_fw_write_wait()
1044 !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */ in gfx_v9_0_check_if_need_gfxoff()
1073 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1076 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1079 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1080 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1081 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1084 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1087 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1090 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1091 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1092 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1095 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_gfx_microcode()
1098 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1101 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v9_0_init_cp_gfx_microcode()
1102 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_gfx_microcode()
1103 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_gfx_microcode()
1108 info->fw = adev->gfx.pfp_fw; in gfx_v9_0_init_cp_gfx_microcode()
1115 info->fw = adev->gfx.me_fw; in gfx_v9_0_init_cp_gfx_microcode()
1122 info->fw = adev->gfx.ce_fw; in gfx_v9_0_init_cp_gfx_microcode()
1133 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_init_cp_gfx_microcode()
1134 adev->gfx.pfp_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1135 release_firmware(adev->gfx.me_fw); in gfx_v9_0_init_cp_gfx_microcode()
1136 adev->gfx.me_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1137 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_init_cp_gfx_microcode()
1138 adev->gfx.ce_fw = NULL; in gfx_v9_0_init_cp_gfx_microcode()
1177 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v9_0_init_rlc_microcode()
1180 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1181 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()
1186 adev->gfx.rlc.is_rlc_v2_1 = true; in gfx_v9_0_init_rlc_microcode()
1188 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v9_0_init_rlc_microcode()
1189 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v9_0_init_rlc_microcode()
1190 adev->gfx.rlc.save_and_restore_offset = in gfx_v9_0_init_rlc_microcode()
1192 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v9_0_init_rlc_microcode()
1194 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v9_0_init_rlc_microcode()
1196 adev->gfx.rlc.reg_restore_list_size = in gfx_v9_0_init_rlc_microcode()
1198 adev->gfx.rlc.reg_list_format_start = in gfx_v9_0_init_rlc_microcode()
1200 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v9_0_init_rlc_microcode()
1202 adev->gfx.rlc.starting_offsets_start = in gfx_v9_0_init_rlc_microcode()
1204 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v9_0_init_rlc_microcode()
1206 adev->gfx.rlc.reg_list_size_bytes = in gfx_v9_0_init_rlc_microcode()
1208 adev->gfx.rlc.register_list_format = in gfx_v9_0_init_rlc_microcode()
1209 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in gfx_v9_0_init_rlc_microcode()
1210 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in gfx_v9_0_init_rlc_microcode()
1211 if (!adev->gfx.rlc.register_list_format) { in gfx_v9_0_init_rlc_microcode()
1218 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) in gfx_v9_0_init_rlc_microcode()
1219 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_rlc_microcode()
1221 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in gfx_v9_0_init_rlc_microcode()
1225 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) in gfx_v9_0_init_rlc_microcode()
1226 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in gfx_v9_0_init_rlc_microcode()
1228 if (adev->gfx.rlc.is_rlc_v2_1) in gfx_v9_0_init_rlc_microcode()
1234 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1239 if (adev->gfx.rlc.is_rlc_v2_1 && in gfx_v9_0_init_rlc_microcode()
1240 adev->gfx.rlc.save_restore_list_cntl_size_bytes && in gfx_v9_0_init_rlc_microcode()
1241 adev->gfx.rlc.save_restore_list_gpm_size_bytes && in gfx_v9_0_init_rlc_microcode()
1242 adev->gfx.rlc.save_restore_list_srm_size_bytes) { in gfx_v9_0_init_rlc_microcode()
1245 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1247 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1251 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1253 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1257 info->fw = adev->gfx.rlc_fw; in gfx_v9_0_init_rlc_microcode()
1259 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in gfx_v9_0_init_rlc_microcode()
1268 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_init_rlc_microcode()
1269 adev->gfx.rlc_fw = NULL; in gfx_v9_0_init_rlc_microcode()
1284 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_compute_microcode()
1287 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1290 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_init_cp_compute_microcode()
1291 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v9_0_init_cp_compute_microcode()
1292 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v9_0_init_cp_compute_microcode()
1296 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v9_0_init_cp_compute_microcode()
1298 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1302 adev->gfx.mec2_fw->data; in gfx_v9_0_init_cp_compute_microcode()
1303 adev->gfx.mec2_fw_version = in gfx_v9_0_init_cp_compute_microcode()
1305 adev->gfx.mec2_feature_version = in gfx_v9_0_init_cp_compute_microcode()
1309 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1315 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_cp_compute_microcode()
1323 info->fw = adev->gfx.mec_fw; in gfx_v9_0_init_cp_compute_microcode()
1327 if (adev->gfx.mec2_fw) { in gfx_v9_0_init_cp_compute_microcode()
1330 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_cp_compute_microcode()
1341 info->fw = adev->gfx.mec2_fw; in gfx_v9_0_init_cp_compute_microcode()
1356 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_init_cp_compute_microcode()
1357 adev->gfx.mec_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1358 release_firmware(adev->gfx.mec2_fw); in gfx_v9_0_init_cp_compute_microcode()
1359 adev->gfx.mec2_fw = NULL; in gfx_v9_0_init_cp_compute_microcode()
1452 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1464 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1488 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; in gfx_v9_0_init_always_on_cu_mask()
1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_init_always_on_cu_mask()
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
1509 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_init_always_on_cu_mask()
1643 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1645 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1656 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
1680 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v9_0_csb_vram_pin()
1684 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, in gfx_v9_0_csb_vram_pin()
1687 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v9_0_csb_vram_pin()
1688 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_pin()
1690 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_pin()
1699 if (!adev->gfx.rlc.clear_state_obj) in gfx_v9_0_csb_vram_unpin()
1702 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); in gfx_v9_0_csb_vram_unpin()
1704 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_unpin()
1705 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v9_0_csb_vram_unpin()
1711 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1712 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v9_0_mec_fini()
1726 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v9_0_mec_init()
1730 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()
1734 &adev->gfx.mec.hpd_eop_obj, in gfx_v9_0_mec_init()
1735 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v9_0_mec_init()
1743 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); in gfx_v9_0_mec_init()
1745 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1746 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v9_0_mec_init()
1748 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()
1751 (adev->gfx.mec_fw->data + in gfx_v9_0_mec_init()
1757 &adev->gfx.mec.mec_fw_obj, in gfx_v9_0_mec_init()
1758 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v9_0_mec_init()
1768 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1769 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v9_0_mec_init()
1860 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; in gfx_v9_0_gpu_early_init()
1864 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1865 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1866 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1867 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1868 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1872 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1873 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1874 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1875 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1876 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1881 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1882 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1883 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1884 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1885 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1895 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1896 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1897 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1898 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1899 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1906 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1907 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1908 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1909 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v9_0_gpu_early_init()
1910 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1916 adev->gfx.config.max_hw_contexts = 8; in gfx_v9_0_gpu_early_init()
1917 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v9_0_gpu_early_init()
1918 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v9_0_gpu_early_init()
1919 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v9_0_gpu_early_init()
1920 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v9_0_gpu_early_init()
1930 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v9_0_gpu_early_init()
1932 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()
1934 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1938 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
1939 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()
1941 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()
1943 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1946 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()
1948 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1951 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()
1953 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1956 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()
1958 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1961 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
1963 adev->gfx.config.gb_addr_config, in gfx_v9_0_gpu_early_init()
1983 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; in gfx_v9_0_ngg_create_buf()
2003 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, in gfx_v9_0_ngg_fini()
2004 &adev->gfx.ngg.buf[i].gpu_addr, in gfx_v9_0_ngg_fini()
2007 memset(&adev->gfx.ngg.buf[0], 0, in gfx_v9_0_ngg_fini()
2010 adev->gfx.ngg.init = false; in gfx_v9_0_ngg_fini()
2019 if (!amdgpu_ngg || adev->gfx.ngg.init == true) in gfx_v9_0_ngg_init()
2023 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); in gfx_v9_0_ngg_init()
2024 adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size; in gfx_v9_0_ngg_init()
2025 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); in gfx_v9_0_ngg_init()
2026 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); in gfx_v9_0_ngg_init()
2029 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], in gfx_v9_0_ngg_init()
2038 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], in gfx_v9_0_ngg_init()
2047 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], in gfx_v9_0_ngg_init()
2059 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], in gfx_v9_0_ngg_init()
2068 adev->gfx.ngg.init = true; in gfx_v9_0_ngg_init()
2077 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_ngg_en()
2086 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); in gfx_v9_0_ngg_en()
2088 adev->gfx.ngg.buf[NGG_POS].size >> 8); in gfx_v9_0_ngg_en()
2092 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); in gfx_v9_0_ngg_en()
2094 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); in gfx_v9_0_ngg_en()
2098 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); in gfx_v9_0_ngg_en()
2102 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); in gfx_v9_0_ngg_en()
2106 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); in gfx_v9_0_ngg_en()
2110 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); in gfx_v9_0_ngg_en()
2114 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); in gfx_v9_0_ngg_en()
2118 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); in gfx_v9_0_ngg_en()
2133 adev->gfx.ngg.gds_reserve_size)); in gfx_v9_0_ngg_en()
2141 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); in gfx_v9_0_ngg_en()
2144 adev->gfx.ngg.gds_reserve_size); in gfx_v9_0_ngg_en()
2159 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2161 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v9_0_compute_ring_init()
2171 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v9_0_compute_ring_init()
2176 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v9_0_compute_ring_init()
2181 &adev->gfx.eop_irq, irq_type); in gfx_v9_0_compute_ring_init()
2203 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2206 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2210 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v9_0_sw_init()
2211 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v9_0_sw_init()
2214 …_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); in gfx_v9_0_sw_init()
2220 &adev->gfx.priv_reg_irq); in gfx_v9_0_sw_init()
2226 &adev->gfx.priv_inst_irq); in gfx_v9_0_sw_init()
2232 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2238 &adev->gfx.cp_ecc_error_irq); in gfx_v9_0_sw_init()
2242 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v9_0_sw_init()
2252 r = adev->gfx.rlc.funcs->init(adev); in gfx_v9_0_sw_init()
2265 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v9_0_sw_init()
2266 ring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_sw_init()
2275 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); in gfx_v9_0_sw_init()
2282 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
2283 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v9_0_sw_init()
2284 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v9_0_sw_init()
2305 kiq = &adev->gfx.kiq; in gfx_v9_0_sw_init()
2315 adev->gfx.ce_ram_size = 0x8000; in gfx_v9_0_sw_init()
2335 adev->gfx.ras_if) { in gfx_v9_0_sw_fini()
2336 struct ras_common_if *ras_if = adev->gfx.ras_if; in gfx_v9_0_sw_fini()
2348 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_sw_fini()
2349 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v9_0_sw_fini()
2350 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()
2351 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v9_0_sw_fini()
2354 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); in gfx_v9_0_sw_fini()
2359 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); in gfx_v9_0_sw_fini()
2361 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v9_0_sw_fini()
2362 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v9_0_sw_fini()
2363 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v9_0_sw_fini()
2408 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()
2409 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2419 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
2420 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2423 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_setup_rb()
2424 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2427 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2434 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v9_0_setup_rb()
2435 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v9_0_setup_rb()
2507 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v9_0_constants_init()
2508 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); in gfx_v9_0_constants_init()
2550 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_wait_for_rlc_serdes()
2551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
2599 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2601 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
2603 adev->gfx.rlc.clear_state_size); in gfx_v9_0_init_csb()
2656 kmemdup(adev->gfx.rlc.register_list_format, in gfx_v9_1_init_rlc_save_restore_list()
2657 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); in gfx_v9_1_init_rlc_save_restore_list()
2664 adev->gfx.rlc.reg_list_format_direct_reg_list_length, in gfx_v9_1_init_rlc_save_restore_list()
2665 adev->gfx.rlc.reg_list_format_size_bytes >> 2, in gfx_v9_1_init_rlc_save_restore_list()
2680 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) in gfx_v9_1_init_rlc_save_restore_list()
2682 adev->gfx.rlc.register_restore[i]); in gfx_v9_1_init_rlc_save_restore_list()
2686 adev->gfx.rlc.reg_list_format_start); in gfx_v9_1_init_rlc_save_restore_list()
2689 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) in gfx_v9_1_init_rlc_save_restore_list()
2694 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { in gfx_v9_1_init_rlc_save_restore_list()
2716 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; in gfx_v9_1_init_rlc_save_restore_list()
2719 adev->gfx.rlc.reg_restore_list_size); in gfx_v9_1_init_rlc_save_restore_list()
2724 adev->gfx.rlc.starting_offsets_start); in gfx_v9_1_init_rlc_save_restore_list()
2925 if (adev->gfx.rlc.is_rlc_v2_1) { in gfx_v9_0_init_pg()
2940 adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v9_0_init_pg()
2980 rlc_ucode_ver, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_start()
2998 if (!adev->gfx.rlc_fw) in gfx_v9_0_rlc_load_microcode()
3001 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_rlc_load_microcode()
3004 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v9_0_rlc_load_microcode()
3012 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
3026 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_rlc_resume()
3057 adev->gfx.rlc.funcs->start(adev); in gfx_v9_0_rlc_resume()
3071 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_cp_gfx_enable()
3072 adev->gfx.gfx_ring[i].sched.ready = false; in gfx_v9_0_cp_gfx_enable()
3086 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
3090 adev->gfx.pfp_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3092 adev->gfx.ce_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3094 adev->gfx.me_fw->data; in gfx_v9_0_cp_gfx_load_microcode()
3104 (adev->gfx.pfp_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3110 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3114 (adev->gfx.ce_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3120 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3124 (adev->gfx.me_fw->data + in gfx_v9_0_cp_gfx_load_microcode()
3130 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
3137 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_start()
3143 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v9_0_cp_gfx_start()
3211 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_gfx_resume()
3276 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_cp_compute_enable()
3277 adev->gfx.compute_ring[i].sched.ready = false; in gfx_v9_0_cp_compute_enable()
3278 adev->gfx.kiq.ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3290 if (!adev->gfx.mec_fw) in gfx_v9_0_cp_compute_load_microcode()
3295 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_cp_compute_load_microcode()
3299 (adev->gfx.mec_fw->data + in gfx_v9_0_cp_compute_load_microcode()
3307 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); in gfx_v9_0_cp_compute_load_microcode()
3309 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v9_0_cp_compute_load_microcode()
3319 adev->gfx.mec_fw_version); in gfx_v9_0_cp_compute_load_microcode()
3342 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_kcq_enable()
3347 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) in gfx_v9_0_kiq_kcq_enable()
3361 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); in gfx_v9_0_kiq_kcq_enable()
3377 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kiq_kcq_enable()
3378 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kiq_kcq_enable()
3704 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
3705 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3727 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kiq_init_queue()
3728 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3738 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v9_0_kcq_init_queue()
3750 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3751 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3754 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v9_0_kcq_init_queue()
3755 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3772 ring = &adev->gfx.kiq.ring; in gfx_v9_0_kiq_resume()
3797 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()
3798 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kcq_resume()
3855 ring = &adev->gfx.gfx_ring[0]; in gfx_v9_0_cp_resume()
3861 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()
3862 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_cp_resume()
3892 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v9_0_hw_init()
3912 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v9_0_kcq_disable()
3914 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v9_0_kcq_disable()
3918 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_disable()
3919 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_kcq_disable()
3943 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v9_0_hw_fini()
3944 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_hw_fini()
3945 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_hw_fini()
3966 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, in gfx_v9_0_hw_fini()
3967 adev->gfx.kiq.ring.pipe, in gfx_v9_0_hw_fini()
3968 adev->gfx.kiq.ring.queue, 0); in gfx_v9_0_hw_fini()
3969 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); in gfx_v9_0_hw_fini()
3975 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_hw_fini()
4050 adev->gfx.rlc.funcs->stop(adev); in gfx_v9_0_soft_reset()
4083 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4087 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v9_0_get_gpu_clock_counter()
4217 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gds_workarounds()
4260 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; in gfx_v9_0_do_edc_gpr_workarounds()
4398 adev->gfx.num_gfx_rings = 0; in gfx_v9_0_early_init()
4400 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; in gfx_v9_0_early_init()
4401 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; in gfx_v9_0_early_init()
4417 struct ras_common_if **ras_if = &adev->gfx.ras_if; in gfx_v9_0_ecc_late_init()
4497 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in gfx_v9_0_ecc_late_init()
4520 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v9_0_late_init()
4524 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v9_0_late_init()
4839 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); in gfx_v9_0_set_powergating_state()
4868 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); in gfx_v9_0_set_powergating_state()
5162 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; in gfx_v9_0_ring_set_pipe_percent()
5182 mutex_lock(&adev->gfx.pipe_reserve_mutex); in gfx_v9_0_pipe_reserve_resources()
5185 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
5187 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
5189 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { in gfx_v9_0_pipe_reserve_resources()
5191 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) in gfx_v9_0_pipe_reserve_resources()
5192 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], in gfx_v9_0_pipe_reserve_resources()
5195 for (i = 0; i < adev->gfx.num_compute_rings; ++i) in gfx_v9_0_pipe_reserve_resources()
5196 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], in gfx_v9_0_pipe_reserve_resources()
5200 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { in gfx_v9_0_pipe_reserve_resources()
5201 iring = &adev->gfx.gfx_ring[i]; in gfx_v9_0_pipe_reserve_resources()
5206 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
5210 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { in gfx_v9_0_pipe_reserve_resources()
5211 iring = &adev->gfx.compute_ring[i]; in gfx_v9_0_pipe_reserve_resources()
5216 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); in gfx_v9_0_pipe_reserve_resources()
5221 mutex_unlock(&adev->gfx.pipe_reserve_mutex); in gfx_v9_0_pipe_reserve_resources()
5458 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; in gfx_v9_0_ring_emit_reg_write_reg_wait()
5678 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v9_0_eop_irq()
5682 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()
5683 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_eop_irq()
5708 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v9_0_fault()
5712 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()
5713 ring = &adev->gfx.compute_ring[i]; in gfx_v9_0_fault()
5746 if (adev->gfx.funcs->query_ras_error_count) in gfx_v9_0_process_ras_data_cb()
5747 adev->gfx.funcs->query_ras_error_count(adev, err_data); in gfx_v9_0_process_ras_data_cb()
6111 for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) { in gfx_v9_0_query_ras_error_count()
6164 struct ras_common_if *ras_if = adev->gfx.ras_if; in gfx_v9_0_cp_ecc_error_irq()
6316 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; in gfx_v9_0_set_ring_funcs()
6318 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v9_0_set_ring_funcs()
6319 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; in gfx_v9_0_set_ring_funcs()
6321 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
6322 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; in gfx_v9_0_set_ring_funcs()
6348 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
6349 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; in gfx_v9_0_set_irq_funcs()
6351 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
6352 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; in gfx_v9_0_set_irq_funcs()
6354 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
6355 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; in gfx_v9_0_set_irq_funcs()
6357 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ in gfx_v9_0_set_irq_funcs()
6358 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; in gfx_v9_0_set_irq_funcs()
6370 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; in gfx_v9_0_set_rlc_funcs()
6446 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()
6464 if (adev->gfx.config.max_shader_engines * in gfx_v9_0_get_cu_info()
6465 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
6469 adev->gfx.config.max_shader_engines, in gfx_v9_0_get_cu_info()
6470 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
6473 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v9_0_get_cu_info()
6474 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
6480 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); in gfx_v9_0_get_cu_info()
6497 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()
6499 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()