Lines Matching refs:ctx
94 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
97 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
98 writel(val, ctx->addr + reg); in decon_set_bits()
103 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
112 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
114 enable_irq(ctx->irq); in decon_enable_vblank()
115 if (!(ctx->out_type & I80_HW_TRG)) in decon_enable_vblank()
116 enable_irq(ctx->te_irq); in decon_enable_vblank()
123 struct decon_context *ctx = crtc->ctx; in decon_disable_vblank() local
125 if (!(ctx->out_type & I80_HW_TRG)) in decon_disable_vblank()
126 disable_irq_nosync(ctx->te_irq); in decon_disable_vblank()
127 disable_irq_nosync(ctx->irq); in decon_disable_vblank()
129 writel(0, ctx->addr + DECON_VIDINTCON0); in decon_disable_vblank()
133 static u32 decon_get_frame_count(struct decon_context *ctx, bool end) in decon_get_frame_count() argument
141 frm = readl(ctx->addr + DECON_CRFMID); in decon_get_frame_count()
143 status = readl(ctx->addr + DECON_VIDCON1); in decon_get_frame_count()
145 frm = readl(ctx->addr + DECON_CRFMID); in decon_get_frame_count()
156 if (!(ctx->crtc->i80_mode)) in decon_get_frame_count()
174 static void decon_setup_trigger(struct decon_context *ctx) in decon_setup_trigger() argument
176 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) in decon_setup_trigger()
179 if (!(ctx->out_type & I80_HW_TRG)) { in decon_setup_trigger()
182 ctx->addr + DECON_TRIGCON); in decon_setup_trigger()
187 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON); in decon_setup_trigger()
189 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX, in decon_setup_trigger()
191 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n"); in decon_setup_trigger()
196 struct decon_context *ctx = crtc->ctx; in decon_commit() local
201 if (ctx->out_type & IFTYPE_HDMI) { in decon_commit()
210 decon_setup_trigger(ctx); in decon_commit()
222 writel(val, ctx->addr + DECON_VIDOUTCON0); in decon_commit()
230 writel(val, ctx->addr + DECON_VIDTCON2); in decon_commit()
239 writel(val, ctx->addr + DECON_VIDTCON00); in decon_commit()
243 writel(val, ctx->addr + DECON_VIDTCON01); in decon_commit()
249 writel(val, ctx->addr + DECON_VIDTCON10); in decon_commit()
253 writel(val, ctx->addr + DECON_VIDTCON11); in decon_commit()
257 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); in decon_commit()
259 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_commit()
262 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win, in decon_win_set_bldeq() argument
285 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); in decon_win_set_bldeq()
288 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, in decon_win_set_bldmod() argument
305 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); in decon_win_set_bldmod()
311 decon_set_bits(ctx, DECON_VIDOSDxC(win), in decon_win_set_bldmod()
313 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); in decon_win_set_bldmod()
317 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, in decon_win_set_pixfmt() argument
320 struct exynos_drm_plane plane = ctx->planes[win]; in decon_win_set_pixfmt()
332 val = readl(ctx->addr + DECON_WINCONx(win)); in decon_win_set_pixfmt()
359 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]); in decon_win_set_pixfmt()
373 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); in decon_win_set_pixfmt()
376 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha); in decon_win_set_pixfmt()
377 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha); in decon_win_set_pixfmt()
381 static void decon_shadow_protect(struct decon_context *ctx, bool protect) in decon_shadow_protect() argument
383 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK, in decon_shadow_protect()
389 struct decon_context *ctx = crtc->ctx; in decon_atomic_begin() local
391 decon_shadow_protect(ctx, true); in decon_atomic_begin()
403 struct decon_context *ctx = crtc->ctx; in decon_update_plane() local
414 writel(val, ctx->addr + DECON_VIDOSDxA(win)); in decon_update_plane()
418 writel(val, ctx->addr + DECON_VIDOSDxB(win)); in decon_update_plane()
421 writel(val, ctx->addr + DECON_VIDOSDxA(win)); in decon_update_plane()
425 writel(val, ctx->addr + DECON_VIDOSDxB(win)); in decon_update_plane()
430 writel(val, ctx->addr + DECON_VIDOSDxC(win)); in decon_update_plane()
434 writel(val, ctx->addr + DECON_VIDOSDxD(win)); in decon_update_plane()
436 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); in decon_update_plane()
439 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); in decon_update_plane()
441 if (!(ctx->out_type & IFTYPE_HDMI)) in decon_update_plane()
447 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); in decon_update_plane()
449 decon_win_set_pixfmt(ctx, win, fb); in decon_update_plane()
452 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); in decon_update_plane()
458 struct decon_context *ctx = crtc->ctx; in decon_disable_plane() local
461 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_disable_plane()
466 struct decon_context *ctx = crtc->ctx; in decon_atomic_flush() local
469 spin_lock_irqsave(&ctx->vblank_lock, flags); in decon_atomic_flush()
471 decon_shadow_protect(ctx, false); in decon_atomic_flush()
473 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_atomic_flush()
475 ctx->frame_id = decon_get_frame_count(ctx, true); in decon_atomic_flush()
479 spin_unlock_irqrestore(&ctx->vblank_lock, flags); in decon_atomic_flush()
482 static void decon_swreset(struct decon_context *ctx) in decon_swreset() argument
488 writel(0, ctx->addr + DECON_VIDCON0); in decon_swreset()
489 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, in decon_swreset()
492 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); in decon_swreset()
493 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, in decon_swreset()
498 spin_lock_irqsave(&ctx->vblank_lock, flags); in decon_swreset()
499 ctx->frame_id = 0; in decon_swreset()
500 spin_unlock_irqrestore(&ctx->vblank_lock, flags); in decon_swreset()
502 if (!(ctx->out_type & IFTYPE_HDMI)) in decon_swreset()
505 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); in decon_swreset()
506 decon_set_bits(ctx, DECON_CMU, in decon_swreset()
508 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); in decon_swreset()
510 ctx->addr + DECON_CRCCTRL); in decon_swreset()
515 struct decon_context *ctx = crtc->ctx; in decon_enable() local
517 pm_runtime_get_sync(ctx->dev); in decon_enable()
521 decon_swreset(ctx); in decon_enable()
523 decon_commit(ctx->crtc); in decon_enable()
528 struct decon_context *ctx = crtc->ctx; in decon_disable() local
531 if (!(ctx->out_type & I80_HW_TRG)) in decon_disable()
532 synchronize_irq(ctx->te_irq); in decon_disable()
533 synchronize_irq(ctx->irq); in decon_disable()
540 for (i = ctx->first_win; i < WINDOWS_NR; i++) in decon_disable()
541 decon_disable_plane(crtc, &ctx->planes[i]); in decon_disable()
543 decon_swreset(ctx); in decon_disable()
547 pm_runtime_put_sync(ctx->dev); in decon_disable()
552 struct decon_context *ctx = dev_id; in decon_te_irq_handler() local
554 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); in decon_te_irq_handler()
561 struct decon_context *ctx = crtc->ctx; in decon_clear_channels() local
565 ret = clk_prepare_enable(ctx->clks[i]); in decon_clear_channels()
570 decon_shadow_protect(ctx, true); in decon_clear_channels()
572 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_clear_channels()
573 decon_shadow_protect(ctx, false); in decon_clear_channels()
575 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_clear_channels()
582 clk_disable_unprepare(ctx->clks[i]); in decon_clear_channels()
588 struct decon_context *ctx = crtc->ctx; in decon_mode_valid() local
590 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; in decon_mode_valid()
592 if (ctx->irq) in decon_mode_valid()
595 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", in decon_mode_valid()
615 struct decon_context *ctx = dev_get_drvdata(dev); in decon_bind() local
622 ctx->drm_dev = drm_dev; in decon_bind()
624 for (win = ctx->first_win; win < WINDOWS_NR; win++) { in decon_bind()
625 ctx->configs[win].pixel_formats = decon_formats; in decon_bind()
626 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); in decon_bind()
627 ctx->configs[win].zpos = win - ctx->first_win; in decon_bind()
628 ctx->configs[win].type = decon_win_types[win]; in decon_bind()
629 ctx->configs[win].capabilities = capabilities[win]; in decon_bind()
631 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, in decon_bind()
632 &ctx->configs[win]); in decon_bind()
637 exynos_plane = &ctx->planes[PRIMARY_WIN]; in decon_bind()
638 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI in decon_bind()
640 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in decon_bind()
641 out_type, &decon_crtc_ops, ctx); in decon_bind()
642 if (IS_ERR(ctx->crtc)) in decon_bind()
643 return PTR_ERR(ctx->crtc); in decon_bind()
645 decon_clear_channels(ctx->crtc); in decon_bind()
652 struct decon_context *ctx = dev_get_drvdata(dev); in decon_unbind() local
654 decon_disable(ctx->crtc); in decon_unbind()
657 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); in decon_unbind()
665 static void decon_handle_vblank(struct decon_context *ctx) in decon_handle_vblank() argument
669 spin_lock(&ctx->vblank_lock); in decon_handle_vblank()
671 frm = decon_get_frame_count(ctx, true); in decon_handle_vblank()
673 if (frm != ctx->frame_id) { in decon_handle_vblank()
675 if ((s32)(frm - ctx->frame_id) > 0) in decon_handle_vblank()
676 drm_crtc_handle_vblank(&ctx->crtc->base); in decon_handle_vblank()
677 ctx->frame_id = frm; in decon_handle_vblank()
680 spin_unlock(&ctx->vblank_lock); in decon_handle_vblank()
685 struct decon_context *ctx = dev_id; in decon_irq_handler() local
688 val = readl(ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
692 writel(val, ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
693 if (ctx->out_type & IFTYPE_HDMI) { in decon_irq_handler()
694 val = readl(ctx->addr + DECON_VIDOUTCON0); in decon_irq_handler()
700 decon_handle_vblank(ctx); in decon_irq_handler()
709 struct decon_context *ctx = dev_get_drvdata(dev); in exynos5433_decon_suspend() local
713 clk_disable_unprepare(ctx->clks[i]); in exynos5433_decon_suspend()
720 struct decon_context *ctx = dev_get_drvdata(dev); in exynos5433_decon_resume() local
724 ret = clk_prepare_enable(ctx->clks[i]); in exynos5433_decon_resume()
733 clk_disable_unprepare(ctx->clks[i]); in exynos5433_decon_resume()
759 static int decon_conf_irq(struct decon_context *ctx, const char *name, in decon_conf_irq() argument
762 struct platform_device *pdev = to_platform_device(ctx->dev); in decon_conf_irq()
773 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); in decon_conf_irq()
778 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx); in decon_conf_irq()
780 dev_err(ctx->dev, "IRQ %s request failed\n", name); in decon_conf_irq()
790 struct decon_context *ctx; in exynos5433_decon_probe() local
795 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); in exynos5433_decon_probe()
796 if (!ctx) in exynos5433_decon_probe()
799 ctx->dev = dev; in exynos5433_decon_probe()
800 ctx->out_type = (unsigned long)of_device_get_match_data(dev); in exynos5433_decon_probe()
801 spin_lock_init(&ctx->vblank_lock); in exynos5433_decon_probe()
803 if (ctx->out_type & IFTYPE_HDMI) in exynos5433_decon_probe()
804 ctx->first_win = 1; in exynos5433_decon_probe()
809 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); in exynos5433_decon_probe()
813 ctx->clks[i] = clk; in exynos5433_decon_probe()
817 ctx->addr = devm_ioremap_resource(dev, res); in exynos5433_decon_probe()
818 if (IS_ERR(ctx->addr)) { in exynos5433_decon_probe()
820 return PTR_ERR(ctx->addr); in exynos5433_decon_probe()
823 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); in exynos5433_decon_probe()
826 ctx->irq_vsync = ret; in exynos5433_decon_probe()
828 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); in exynos5433_decon_probe()
831 ctx->irq_lcd_sys = ret; in exynos5433_decon_probe()
833 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, in exynos5433_decon_probe()
838 ctx->te_irq = ret; in exynos5433_decon_probe()
839 ctx->out_type &= ~I80_HW_TRG; in exynos5433_decon_probe()
842 if (ctx->out_type & I80_HW_TRG) { in exynos5433_decon_probe()
843 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, in exynos5433_decon_probe()
845 if (IS_ERR(ctx->sysreg)) { in exynos5433_decon_probe()
847 return PTR_ERR(ctx->sysreg); in exynos5433_decon_probe()
851 platform_set_drvdata(pdev, ctx); in exynos5433_decon_probe()