249 	const unsigned int *reg_values;  member
396 static const unsigned int reg_values[] = {  variable
459 	.reg_values = reg_values,
471 	.reg_values = reg_values,
481 	.reg_values = reg_values,
492 	.reg_values = exynos5433_reg_values,
503 	.reg_values = exynos5422_reg_values,
530 	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];  in exynos_dsi_reset()
613 	writel(driver_data->reg_values[PLL_TIMER],  in exynos_dsi_set_pll()
692 	const unsigned int *reg_values = driver_data->reg_values;  in exynos_dsi_set_phy_ctrl()  local
699 	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |  in exynos_dsi_set_phy_ctrl()
700 		reg_values[PHYCTRL_SLEW_UP];  in exynos_dsi_set_phy_ctrl()
708 	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];  in exynos_dsi_set_phy_ctrl()
724 	reg = reg_values[PHYTIMING_CLK_PREPARE] |  in exynos_dsi_set_phy_ctrl()
725 		reg_values[PHYTIMING_CLK_ZERO] |  in exynos_dsi_set_phy_ctrl()
726 		reg_values[PHYTIMING_CLK_POST] |  in exynos_dsi_set_phy_ctrl()
727 		reg_values[PHYTIMING_CLK_TRAIL];  in exynos_dsi_set_phy_ctrl()
740 	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |  in exynos_dsi_set_phy_ctrl()
741 		reg_values[PHYTIMING_HS_TRAIL];  in exynos_dsi_set_phy_ctrl()
872 	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);  in exynos_dsi_init_link()
1318 	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)  in exynos_dsi_init()