Lines Matching refs:clock
213 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) in cdv_dpll_set_clock_cdv() argument
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
292 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
295 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
312 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
326 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) in cdv_intel_clock() argument
394 clock->m = clock->m2 + 2; in cdv_intel_clock()
395 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
396 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
397 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
406 struct gma_clock_t clock; in cdv_intel_find_dp_pll() local
411 clock.p1 = 2; in cdv_intel_find_dp_pll()
412 clock.p2 = 10; in cdv_intel_find_dp_pll()
413 clock.n = 1; in cdv_intel_find_dp_pll()
414 clock.m1 = 0; in cdv_intel_find_dp_pll()
415 clock.m2 = 118; in cdv_intel_find_dp_pll()
417 clock.p1 = 1; in cdv_intel_find_dp_pll()
418 clock.p2 = 10; in cdv_intel_find_dp_pll()
419 clock.n = 1; in cdv_intel_find_dp_pll()
420 clock.m1 = 0; in cdv_intel_find_dp_pll()
421 clock.m2 = 98; in cdv_intel_find_dp_pll()
427 clock.p1 = 2; in cdv_intel_find_dp_pll()
428 clock.p2 = 10; in cdv_intel_find_dp_pll()
429 clock.n = 5; in cdv_intel_find_dp_pll()
430 clock.m1 = 0; in cdv_intel_find_dp_pll()
431 clock.m2 = 160; in cdv_intel_find_dp_pll()
433 clock.p1 = 1; in cdv_intel_find_dp_pll()
434 clock.p2 = 10; in cdv_intel_find_dp_pll()
435 clock.n = 5; in cdv_intel_find_dp_pll()
436 clock.m1 = 0; in cdv_intel_find_dp_pll()
437 clock.m2 = 133; in cdv_intel_find_dp_pll()
445 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
446 memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); in cdv_intel_find_dp_pll()
580 struct gma_clock_t clock; in cdv_intel_crtc_mode_set() local
655 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in cdv_intel_crtc_mode_set()
656 &clock); in cdv_intel_crtc_mode_set()
659 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
729 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); in cdv_intel_crtc_mode_set()
748 if (clock.p2 == 7) in cdv_intel_crtc_mode_set()
783 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; in cdv_intel_crtc_mode_set()
830 static void i8xx_clock(int refclk, struct gma_clock_t *clock) in i8xx_clock() argument
832 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in i8xx_clock()
833 clock->p = clock->p1 * clock->p2; in i8xx_clock()
834 clock->vco = refclk * clock->m / (clock->n + 2); in i8xx_clock()
835 clock->dot = clock->vco / clock->p; in i8xx_clock()
848 struct gma_clock_t clock; in cdv_intel_crtc_clock_get() local
871 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in cdv_intel_crtc_clock_get()
872 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; in cdv_intel_crtc_clock_get()
873 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; in cdv_intel_crtc_clock_get()
876 clock.p1 = in cdv_intel_crtc_clock_get()
880 if (clock.p1 == 0) { in cdv_intel_crtc_clock_get()
881 clock.p1 = 4; in cdv_intel_crtc_clock_get()
884 clock.p2 = 14; in cdv_intel_crtc_clock_get()
889 i8xx_clock(66000, &clock); in cdv_intel_crtc_clock_get()
891 i8xx_clock(48000, &clock); in cdv_intel_crtc_clock_get()
894 clock.p1 = 2; in cdv_intel_crtc_clock_get()
896 clock.p1 = in cdv_intel_crtc_clock_get()
902 clock.p2 = 4; in cdv_intel_crtc_clock_get()
904 clock.p2 = 2; in cdv_intel_crtc_clock_get()
906 i8xx_clock(48000, &clock); in cdv_intel_crtc_clock_get()
914 return clock.dot; in cdv_intel_crtc_clock_get()
949 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); in cdv_intel_crtc_mode_get()
983 .clock = cdv_intel_clock,