75 #define CHECK_PIPE(pipe) ({			\  argument
76 	const typeof(pipe) __pipe = (pipe);	\
80 #define CHECK_PIPE(pipe) (pipe)  argument
86 #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400)  argument
89 #define MIPI_DEVICE_READY_REG(pipe)		(0xb000 + REG_OFFSET(pipe))  argument
90 #define MIPI_INTR_STAT_REG(pipe)		(0xb004 + REG_OFFSET(pipe))  argument
91 #define MIPI_INTR_EN_REG(pipe)			(0xb008 + REG_OFFSET(pipe))  argument
92 #define MIPI_DSI_FUNC_PRG_REG(pipe)		(0xb00c + REG_OFFSET(pipe))  argument
93 #define MIPI_HS_TX_TIMEOUT_REG(pipe)		(0xb010 + REG_OFFSET(pipe))  argument
94 #define MIPI_LP_RX_TIMEOUT_REG(pipe)		(0xb014 + REG_OFFSET(pipe))  argument
95 #define MIPI_TURN_AROUND_TIMEOUT_REG(pipe)	(0xb018 + REG_OFFSET(pipe))  argument
96 #define MIPI_DEVICE_RESET_TIMER_REG(pipe)	(0xb01c + REG_OFFSET(pipe))  argument
97 #define MIPI_DPI_RESOLUTION_REG(pipe)		(0xb020 + REG_OFFSET(pipe))  argument
98 #define MIPI_DBI_FIFO_THROTTLE_REG(pipe)	(0xb024 + REG_OFFSET(pipe))  argument
99 #define MIPI_HSYNC_COUNT_REG(pipe)		(0xb028 + REG_OFFSET(pipe))  argument
100 #define MIPI_HBP_COUNT_REG(pipe)		(0xb02c + REG_OFFSET(pipe))  argument
101 #define MIPI_HFP_COUNT_REG(pipe)		(0xb030 + REG_OFFSET(pipe))  argument
102 #define MIPI_HACTIVE_COUNT_REG(pipe)		(0xb034 + REG_OFFSET(pipe))  argument
103 #define MIPI_VSYNC_COUNT_REG(pipe)		(0xb038 + REG_OFFSET(pipe))  argument
104 #define MIPI_VBP_COUNT_REG(pipe)		(0xb03c + REG_OFFSET(pipe))  argument
105 #define MIPI_VFP_COUNT_REG(pipe)		(0xb040 + REG_OFFSET(pipe))  argument
106 #define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe)	(0xb044 + REG_OFFSET(pipe))  argument
107 #define MIPI_DPI_CONTROL_REG(pipe)		(0xb048 + REG_OFFSET(pipe))  argument
108 #define MIPI_DPI_DATA_REG(pipe)			(0xb04c + REG_OFFSET(pipe))  argument
109 #define MIPI_INIT_COUNT_REG(pipe)		(0xb050 + REG_OFFSET(pipe))  argument
110 #define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe)	(0xb054 + REG_OFFSET(pipe))  argument
111 #define MIPI_VIDEO_MODE_FORMAT_REG(pipe)	(0xb058 + REG_OFFSET(pipe))  argument
112 #define MIPI_EOT_DISABLE_REG(pipe)		(0xb05c + REG_OFFSET(pipe))  argument
113 #define MIPI_LP_BYTECLK_REG(pipe)		(0xb060 + REG_OFFSET(pipe))  argument
114 #define MIPI_LP_GEN_DATA_REG(pipe)		(0xb064 + REG_OFFSET(pipe))  argument
115 #define MIPI_HS_GEN_DATA_REG(pipe)		(0xb068 + REG_OFFSET(pipe))  argument
116 #define MIPI_LP_GEN_CTRL_REG(pipe)		(0xb06c + REG_OFFSET(pipe))  argument
117 #define MIPI_HS_GEN_CTRL_REG(pipe)		(0xb070 + REG_OFFSET(pipe))  argument
118 #define MIPI_GEN_FIFO_STAT_REG(pipe)		(0xb074 + REG_OFFSET(pipe))  argument
119 #define MIPI_HS_LS_DBI_ENABLE_REG(pipe)		(0xb078 + REG_OFFSET(pipe))  argument
120 #define MIPI_DPHY_PARAM_REG(pipe)		(0xb080 + REG_OFFSET(pipe))  argument
121 #define MIPI_DBI_BW_CTRL_REG(pipe)		(0xb084 + REG_OFFSET(pipe))  argument
122 #define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe)	(0xb088 + REG_OFFSET(pipe))  argument
124 #define MIPI_CTRL_REG(pipe)			(0xb104 + REG_OFFSET(pipe))  argument
125 #define MIPI_DATA_ADD_REG(pipe)			(0xb108 + REG_OFFSET(pipe))  argument
126 #define MIPI_DATA_LEN_REG(pipe)			(0xb10c + REG_OFFSET(pipe))  argument
127 #define MIPI_CMD_ADD_REG(pipe)			(0xb110 + REG_OFFSET(pipe))  argument
128 #define MIPI_CMD_LEN_REG(pipe)			(0xb114 + REG_OFFSET(pipe))  argument
131 #define MIPI_PORT_CONTROL(pipe)		(CHECK_PIPE(pipe) ? MIPI_C : MIPI)  argument
232 	int pipe;  member
357 	return connector->pipe;  in mdfld_dsi_encoder_get_pipe()
364 					int pipe);
365 extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
368 					int pipe,
371 					int pipe);
375 extern int mdfld_dsi_panel_reset(int pipe);